2025-04-27 03:30:27 [INFO] transceiver.py:125 Init transceiver 'BTS@172.18.127.20:5700'
2025-04-27 03:30:27 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:5702 <-> R:172.18.127.20:5802)
2025-04-27 03:30:27 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:5701 <-> R:172.18.127.20:5801)
2025-04-27 03:30:27 [INFO] transceiver.py:125 Init transceiver 'MS@172.18.127.22:6700'
2025-04-27 03:30:27 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:6702 <-> R:172.18.127.22:6802)
2025-04-27 03:30:27 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:6701 <-> R:172.18.127.22:6801)
2025-04-27 03:30:27 [INFO] transceiver.py:125 Init transceiver 'TRX1@172.18.127.20:5700/1'
2025-04-27 03:30:27 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:5704 <-> R:172.18.127.20:5804)
2025-04-27 03:30:27 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:5703 <-> R:172.18.127.20:5803)
2025-04-27 03:30:27 [INFO] transceiver.py:125 Init transceiver 'TRX2@172.18.127.20:5700/2'
2025-04-27 03:30:27 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:5706 <-> R:172.18.127.20:5806)
2025-04-27 03:30:27 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:5705 <-> R:172.18.127.20:5805)
2025-04-27 03:30:27 [INFO] transceiver.py:125 Init transceiver 'TRX3@172.18.127.20:5700/3'
2025-04-27 03:30:27 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:5708 <-> R:172.18.127.20:5808)
2025-04-27 03:30:27 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:5707 <-> R:172.18.127.20:5807)
2025-04-27 03:30:27 [INFO] fake_trx.py:423 Init complete
2025-04-27 03:30:28 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:30:28 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:30:28 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:30:28 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:30:28 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:30:28 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:30:32 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:30:32 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:30:32 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:30:32 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:30:32 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 0 -> 1
2025-04-27 03:30:32 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 03:30:32 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 03:30:32 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:30:32 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:30:32 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:30:32 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 03:30:32 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:30:32 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 0 -> 1
2025-04-27 03:30:32 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 03:30:32 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 03:30:32 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:30:32 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:30:32 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 03:30:32 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:30:32 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:30:32 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 0 -> 1
2025-04-27 03:30:32 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 03:30:32 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 03:30:32 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:30:32 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:30:32 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 03:30:32 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:30:32 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:30:32 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 0 -> 1
2025-04-27 03:30:32 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 03:30:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 03:30:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 03:30:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 03:30:32 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 03:30:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 03:30:32 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 03:30:32 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 03:30:32 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 03:30:32 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 03:30:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 03:30:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 03:30:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:30:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:30:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:30:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:30:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:30:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:30:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:30:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:30:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:30:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:30:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:30:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:30:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 03:30:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:30:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:30:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:30:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:30:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:30:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:30:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:30:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:30:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:30:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 03:30:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:30:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:30:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:30:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:30:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:30:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:30:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:30:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:30:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:30:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:30:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:30:32 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 03:30:32 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 03:30:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:32 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 03:30:32 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 03:30:32 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 03:30:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:30:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:30:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:30:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:30:32 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:30:32 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:30:32 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:30:32 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:30:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:32 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:30:32 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:30:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:30:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:30:33 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 03:30:33 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:30:33 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:30:33 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:30:33 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:30:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:30:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:30:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:30:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:30:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:30:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:30:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:30:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:30:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:30:33 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:30:33 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:30:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:30:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:30:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:30:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:30:33 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 03:30:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:30:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:30:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:30:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:30:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:30:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:30:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:30:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:30:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:30:33 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:30:33 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:30:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:34 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 03:30:34 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:30:34 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:30:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:30:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:30:34 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:30:34 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:30:34 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:30:34 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:30:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:30:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:30:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:30:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:30:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:30:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:30:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:30:34 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:30:34 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:30:34 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:30:34 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:30:34 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 03:30:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:34 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:30:34 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:30:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:30:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:30:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:30:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:30:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:30:35 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 03:30:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:30:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:30:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:30:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:30:35 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:30:35 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:30:35 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:30:35 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:30:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:35 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:30:35 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:30:35 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:30:35 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:30:35 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:30:35 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:30:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:30:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:30:35 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 03:30:36 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 03:30:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:30:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:36 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:30:36 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:30:36 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:30:36 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:30:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:30:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:30:36 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:30:36 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:30:36 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:30:36 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:30:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:36 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:30:36 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:30:36 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:30:36 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:30:36 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:30:36 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:30:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:30:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:30:36 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 03:30:36 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 03:30:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:30:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:30:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:30:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:30:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:30:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:30:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:30:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:30:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:30:37 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:30:37 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:30:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:30:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:30:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:30:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:30:37 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 03:30:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:30:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:30:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:30:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:30:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:30:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:30:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:30:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:30:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:30:37 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:30:37 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:30:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:30:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:37 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 03:30:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:30:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:30:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:30:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:30:38 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 03:30:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:30:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:30:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:30:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:30:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:30:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:30:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:30:38 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:30:38 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:30:38 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:30:38 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:30:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:38 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 03:30:38 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:30:38 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:30:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:30:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:30:39 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 03:30:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:30:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:30:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:30:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:30:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:30:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:30:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:30:39 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:30:39 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:30:39 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:30:39 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:30:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:30:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:39 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 03:30:39 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:30:39 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:30:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:30:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:30:40 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 03:30:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:30:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:30:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:30:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:30:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:30:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:30:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:30:40 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:30:40 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:30:40 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:30:40 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:30:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:40 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 03:30:40 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:30:40 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:30:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:30:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:30:41 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 03:30:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:30:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:30:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:30:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:30:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:30:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:30:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:30:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:30:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:30:41 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:30:41 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:30:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:41 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 03:30:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:30:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:30:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:30:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:30:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:30:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:30:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:30:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:30:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:30:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:30:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:30:42 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:30:42 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:30:42 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:30:42 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:30:42 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 03:30:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:42 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:30:42 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:30:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:30:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:30:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:30:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:30:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:30:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:30:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:30:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:30:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:30:42 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:30:42 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:30:42 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:30:42 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:30:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:42 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:30:42 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:30:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:30:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:30:42 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 03:30:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:30:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:30:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:30:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:30:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:30:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:30:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:30:42 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:30:42 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:30:42 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:30:42 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:30:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:42 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:30:42 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:30:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:30:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:30:43 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-27 03:30:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:30:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:30:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:30:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:30:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:30:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:30:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:30:43 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:30:43 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:30:43 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:30:43 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:30:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:43 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:30:43 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:30:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:30:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:30:43 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-27 03:30:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:30:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:30:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:30:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:30:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:30:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:30:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:30:43 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:30:43 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:30:43 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:30:43 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:30:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:44 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-27 03:30:44 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:30:44 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:30:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:30:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:30:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:30:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:30:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:30:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:30:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:30:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:30:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:30:44 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:30:44 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:30:44 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:30:44 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:30:44 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-27 03:30:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:44 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:30:44 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:30:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:30:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:30:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:30:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:45 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:30:45 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:30:45 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:30:45 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:30:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:30:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:30:45 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:30:45 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:30:45 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:30:45 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:30:45 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-27 03:30:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:45 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:30:45 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:30:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:30:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:30:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:30:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:45 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:30:45 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:30:45 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:30:45 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:30:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:30:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:30:45 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:30:45 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:30:45 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:30:45 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:30:45 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-27 03:30:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:45 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:30:45 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:30:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:30:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:30:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:30:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:46 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:30:46 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:30:46 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:30:46 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:30:46 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:30:46 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:30:46 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:30:46 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:30:46 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-27 03:30:46 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:30:46 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:30:46 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:30:46 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 03:30:46 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:30:51 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:30:51 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:30:51 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:30:51 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:30:51 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:30:51 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:30:51 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:30:51 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:30:51 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 03:30:51 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 03:30:51 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:30:51 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 03:30:51 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 03:30:51 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 03:30:51 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 03:30:51 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:30:51 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
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2025-04-27 03:30:52 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 03:30:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
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2025-04-27 03:30:52 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:30:52 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:30:52 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:30:52 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:30:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
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2025-04-27 03:30:52 [DEBUG] clck_gen.py:102 IND CLOCK 306
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2025-04-27 03:30:52 [DEBUG] clck_gen.py:102 IND CLOCK 408
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2025-04-27 03:30:53 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:30:53 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:30:53 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:30:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:53 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:30:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
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2025-04-27 03:30:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:53 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 03:30:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:53 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:30:53 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:30:53 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:30:53 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:30:53 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:30:53 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:30:53 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:30:53 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:30:53 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:30:53 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 03:30:53 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:30:53 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=522 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:30:53 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=522 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:30:53 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=522 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:30:53 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=522 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:30:53 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=522 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:30:53 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=522 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:30:53 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=523 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:30:53 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=523 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:30:53 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=523 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:30:53 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=523 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:30:53 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=523 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:30:53 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=523 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:30:53 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=523 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:30:53 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=523 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:30:53 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=524 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:30:53 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=524 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:30:53 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=524 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:30:53 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=524 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:30:53 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=524 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:30:53 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=524 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:30:53 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=524 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:30:53 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=524 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:30:53 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=525 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:30:53 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=525 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:30:53 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=525 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:30:53 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=525 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:30:53 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=525 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:30:53 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=525 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:30:53 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=525 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:30:53 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=525 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:30:53 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=526 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:30:53 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=526 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:30:53 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=526 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:30:53 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=526 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:30:53 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=526 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:30:53 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=526 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:30:53 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=526 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:30:53 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=526 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:30:53 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=527 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:30:53 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=527 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:30:53 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=527 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:30:53 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=527 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:30:53 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=527 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:30:53 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=527 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:30:53 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=527 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:30:53 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=527 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:30:58 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:30:58 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:30:58 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:30:58 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:30:58 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:30:58 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:30:58 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:30:58 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:30:58 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:30:58 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:30:58 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 03:30:58 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 03:30:58 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 03:30:58 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:30:58 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:30:58 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:30:58 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 03:30:58 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:30:58 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 03:30:58 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 03:30:58 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 03:30:58 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:30:58 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:30:58 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:30:58 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 03:30:58 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:30:58 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 03:30:58 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 03:30:58 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 03:30:58 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:30:58 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:30:58 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:30:58 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 03:30:58 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:30:58 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 03:30:58 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 03:30:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 03:30:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 03:30:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 03:30:58 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 03:30:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 03:30:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 03:30:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 03:30:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 03:30:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:30:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:30:58 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 03:30:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:30:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:30:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:30:58 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 03:30:58 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 03:30:58 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 03:30:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:30:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:30:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:30:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 03:30:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:30:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:30:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:30:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:30:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:30:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:30:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:30:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:30:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:30:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:30:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:30:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:30:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:30:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:30:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:30:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:30:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:30:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:30:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:30:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:30:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:30:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:30:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:30:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:30:58 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 03:30:59 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 03:30:59 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 03:30:59 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 03:30:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:59 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 03:30:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:30:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:30:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:30:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:30:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:30:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:30:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:30:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:30:59 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:30:59 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:30:59 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:30:59 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:30:59 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 03:30:59 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:30:59 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:30:59 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=125 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:30:59 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=125 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:30:59 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=125 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:30:59 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=125 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:30:59 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=125 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:30:59 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=125 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:30:59 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=125 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:30:59 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=126 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:30:59 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=126 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:30:59 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=126 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:30:59 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=126 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:30:59 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=126 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:30:59 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=126 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:30:59 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=126 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:30:59 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=126 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:31:04 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:31:04 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:31:04 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:31:04 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:31:04 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:31:04 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:31:04 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:31:04 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:31:04 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:31:04 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:31:04 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 03:31:04 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 03:31:04 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 03:31:04 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:31:04 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:31:04 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:31:04 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 03:31:04 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:31:04 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 03:31:04 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 03:31:04 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 03:31:04 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:31:04 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:31:04 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:31:04 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 03:31:04 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:31:04 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 03:31:04 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 03:31:04 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 03:31:04 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:31:04 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:31:04 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:31:04 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 03:31:04 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:31:04 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 03:31:04 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 03:31:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 03:31:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 03:31:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 03:31:04 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 03:31:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 03:31:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 03:31:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 03:31:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 03:31:04 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 03:31:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:31:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:31:04 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 03:31:04 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 03:31:04 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 03:31:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:31:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:31:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:31:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 03:31:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:31:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:31:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:31:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:31:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:31:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:31:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:31:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:31:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:31:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:31:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:31:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:31:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:31:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:31:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:31:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:31:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:31:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:31:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:31:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:31:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:31:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:31:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:31:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:31:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:31:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:31:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:31:04 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 03:31:04 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 03:31:04 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 03:31:04 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 03:31:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:31:04 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 03:31:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:31:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:31:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:31:04 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:31:04 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:31:04 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:31:04 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:31:04 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:31:04 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:31:04 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:31:04 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:31:04 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 03:31:04 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:31:04 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:31:04 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=120 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:31:04 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=120 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:31:04 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=120 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:31:04 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=120 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:31:04 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=120 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:31:09 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:31:09 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:31:09 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:31:09 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:31:09 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:31:09 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:31:09 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:31:09 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:31:09 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:31:09 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:31:09 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 03:31:09 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 03:31:09 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 03:31:09 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:31:09 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:31:09 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:31:09 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 03:31:09 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:31:09 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 03:31:09 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 03:31:09 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 03:31:09 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:31:09 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:31:09 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:31:09 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 03:31:09 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:31:09 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 03:31:09 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 03:31:09 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 03:31:09 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:31:09 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:31:09 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:31:09 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 03:31:09 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:31:09 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 03:31:09 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 03:31:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 03:31:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 03:31:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 03:31:09 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 03:31:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 03:31:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 03:31:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 03:31:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:31:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 03:31:09 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 03:31:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:31:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:31:09 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 03:31:09 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 03:31:09 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 03:31:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:31:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:31:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:31:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 03:31:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:31:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:31:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:31:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:31:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:31:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:31:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:31:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:31:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:31:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:31:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:31:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:31:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:31:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:31:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:31:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:31:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:31:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:31:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:31:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:31:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:31:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:31:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:31:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:31:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:31:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:31:09 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 03:31:10 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 03:31:10 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 03:31:10 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 03:31:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:31:10 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 03:31:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:31:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:31:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:31:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:31:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:31:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:31:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:31:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:31:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:31:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:31:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:31:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:31:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:31:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:31:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:31:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:31:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:31:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:31:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:31:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:31:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:31:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:31:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:31:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:31:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:31:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:31:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:31:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:31:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:31:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:31:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:31:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:31:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:31:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:31:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:31:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:31:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:31:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:31:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:31:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:31:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:31:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:31:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:31:10 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:31:10 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:31:10 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:31:10 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:31:10 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:31:10 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 03:31:10 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:31:15 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:31:15 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:31:15 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:31:15 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:31:15 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:31:15 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:31:15 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:31:15 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:31:15 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:31:15 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:31:15 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 03:31:15 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 03:31:15 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 03:31:15 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:31:15 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:31:15 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:31:15 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 03:31:15 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:31:15 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 03:31:15 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 03:31:15 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 03:31:15 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:31:15 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:31:15 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:31:15 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 03:31:15 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:31:15 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 03:31:15 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 03:31:15 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 03:31:15 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:31:15 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:31:15 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:31:15 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 03:31:15 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:31:15 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 03:31:15 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 03:31:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 03:31:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 03:31:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 03:31:15 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 03:31:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 03:31:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 03:31:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 03:31:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:31:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 03:31:15 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 03:31:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:31:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:31:15 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 03:31:15 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 03:31:15 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 03:31:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:31:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:31:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:31:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 03:31:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:31:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:31:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:31:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:31:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:31:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:31:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:31:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:31:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:31:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:31:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:31:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:31:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:31:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:31:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:31:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:31:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:31:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:31:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:31:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:31:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:31:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:31:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:31:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:31:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:31:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:31:15 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 03:31:15 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 03:31:16 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 03:31:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:31:16 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 03:31:16 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 03:31:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:31:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:31:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:31:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:31:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:31:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:31:16 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:31:16 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:31:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:31:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:31:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:31:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:31:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:31:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:31:16 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 03:31:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:31:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:31:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:31:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:31:16 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 03:31:17 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 03:31:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:31:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:31:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:31:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:31:17 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 03:31:18 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 03:31:18 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:31:18 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:31:18 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:31:18 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:31:18 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 03:31:19 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 03:31:19 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:31:19 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:31:19 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:31:19 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:31:19 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 03:31:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:31:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:31:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:31:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:31:20 [WARNING] transceiver.py:250 (MS@172.18.127.22:6700) RX TRXD message (fn=1009 tn=5 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:31:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:31:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:31:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:31:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:31:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:31:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:31:20 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:31:20 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:31:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:31:20 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 03:31:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:31:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:31:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:31:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:31:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:31:20 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:31:20 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:31:20 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:31:20 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:31:20 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 03:31:21 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 03:31:21 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 03:31:22 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 03:31:22 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 03:31:23 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 03:31:23 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 03:31:24 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 03:31:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:31:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:31:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:31:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:31:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:31:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:31:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:31:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:31:24 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:31:24 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:31:24 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:31:24 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:31:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:31:24 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:31:24 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:31:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:31:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:31:24 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 03:31:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:31:24 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 03:31:25 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 03:31:25 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 03:31:26 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-27 03:31:26 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-27 03:31:27 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-27 03:31:27 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-27 03:31:28 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-27 03:31:28 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-27 03:31:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:31:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:31:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:31:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:31:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:31:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:31:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:31:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:31:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:31:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:31:28 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:31:28 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:31:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:31:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:31:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:31:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:31:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:31:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:31:29 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-27 03:31:29 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-27 03:31:30 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-27 03:31:30 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-27 03:31:31 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-27 03:31:31 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-27 03:31:32 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-27 03:31:32 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-27 03:31:33 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-27 03:31:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:31:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:31:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:31:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:31:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:31:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:31:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:31:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:31:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:31:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:31:33 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:31:33 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:31:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:31:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:31:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:31:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:31:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:31:33 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-27 03:31:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:31:33 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2025-04-27 03:31:34 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2025-04-27 03:31:34 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2025-04-27 03:31:35 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2025-04-27 03:31:35 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2025-04-27 03:31:36 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2025-04-27 03:31:36 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2025-04-27 03:31:37 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2025-04-27 03:31:37 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2025-04-27 03:31:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:31:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:31:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:31:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:31:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:31:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:31:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:31:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:31:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:31:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:31:37 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:31:37 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:31:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:31:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:31:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:31:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:31:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:31:38 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2025-04-27 03:31:38 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2025-04-27 03:31:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:31:39 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2025-04-27 03:31:39 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2025-04-27 03:31:40 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2025-04-27 03:31:40 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2025-04-27 03:31:41 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2025-04-27 03:31:41 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2025-04-27 03:31:42 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2025-04-27 03:31:42 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2025-04-27 03:31:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:31:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:31:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:31:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:31:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:31:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:31:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:31:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:31:42 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:31:42 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:31:42 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:31:42 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:31:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:31:42 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:31:42 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:31:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:31:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:31:42 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2025-04-27 03:31:43 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2025-04-27 03:31:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:31:43 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2025-04-27 03:31:44 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2025-04-27 03:31:44 [DEBUG] clck_gen.py:102 IND CLOCK 6324
2025-04-27 03:31:45 [DEBUG] clck_gen.py:102 IND CLOCK 6426
2025-04-27 03:31:45 [DEBUG] clck_gen.py:102 IND CLOCK 6528
2025-04-27 03:31:46 [DEBUG] clck_gen.py:102 IND CLOCK 6630
2025-04-27 03:31:46 [DEBUG] clck_gen.py:102 IND CLOCK 6732
2025-04-27 03:31:47 [DEBUG] clck_gen.py:102 IND CLOCK 6834
2025-04-27 03:31:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:31:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:31:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:31:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:31:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:31:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:31:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:31:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:31:47 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:31:47 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:31:47 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:31:47 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:31:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:31:47 [DEBUG] clck_gen.py:102 IND CLOCK 6936
2025-04-27 03:31:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:31:47 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:31:47 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:31:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:31:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:31:48 [DEBUG] clck_gen.py:102 IND CLOCK 7038
2025-04-27 03:31:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:31:48 [DEBUG] clck_gen.py:102 IND CLOCK 7140
2025-04-27 03:31:49 [DEBUG] clck_gen.py:102 IND CLOCK 7242
2025-04-27 03:31:49 [DEBUG] clck_gen.py:102 IND CLOCK 7344
2025-04-27 03:31:50 [DEBUG] clck_gen.py:102 IND CLOCK 7446
2025-04-27 03:31:50 [DEBUG] clck_gen.py:102 IND CLOCK 7548
2025-04-27 03:31:51 [DEBUG] clck_gen.py:102 IND CLOCK 7650
2025-04-27 03:31:51 [DEBUG] clck_gen.py:102 IND CLOCK 7752
2025-04-27 03:31:51 [DEBUG] clck_gen.py:102 IND CLOCK 7854
2025-04-27 03:31:52 [DEBUG] clck_gen.py:102 IND CLOCK 7956
2025-04-27 03:31:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:31:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:31:52 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:31:52 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:31:52 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:31:52 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:31:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:31:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:31:52 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:31:52 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:31:52 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:31:52 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:31:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:31:52 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:31:52 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:31:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:31:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:31:52 [DEBUG] clck_gen.py:102 IND CLOCK 8058
2025-04-27 03:31:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:31:53 [DEBUG] clck_gen.py:102 IND CLOCK 8160
2025-04-27 03:31:53 [DEBUG] clck_gen.py:102 IND CLOCK 8262
2025-04-27 03:31:54 [DEBUG] clck_gen.py:102 IND CLOCK 8364
2025-04-27 03:31:54 [DEBUG] clck_gen.py:102 IND CLOCK 8466
2025-04-27 03:31:55 [DEBUG] clck_gen.py:102 IND CLOCK 8568
2025-04-27 03:31:55 [DEBUG] clck_gen.py:102 IND CLOCK 8670
2025-04-27 03:31:56 [DEBUG] clck_gen.py:102 IND CLOCK 8772
2025-04-27 03:31:56 [DEBUG] clck_gen.py:102 IND CLOCK 8874
2025-04-27 03:31:57 [DEBUG] clck_gen.py:102 IND CLOCK 8976
2025-04-27 03:31:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:31:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:31:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:31:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:31:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:31:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:31:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:31:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:31:57 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:31:57 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:31:57 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:31:57 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:31:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:31:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:31:57 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:31:57 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:31:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:31:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:31:57 [DEBUG] clck_gen.py:102 IND CLOCK 9078
2025-04-27 03:31:58 [DEBUG] clck_gen.py:102 IND CLOCK 9180
2025-04-27 03:31:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:31:58 [DEBUG] clck_gen.py:102 IND CLOCK 9282
2025-04-27 03:31:59 [DEBUG] clck_gen.py:102 IND CLOCK 9384
2025-04-27 03:31:59 [DEBUG] clck_gen.py:102 IND CLOCK 9486
2025-04-27 03:32:00 [DEBUG] clck_gen.py:102 IND CLOCK 9588
2025-04-27 03:32:00 [DEBUG] clck_gen.py:102 IND CLOCK 9690
2025-04-27 03:32:00 [DEBUG] clck_gen.py:102 IND CLOCK 9792
2025-04-27 03:32:01 [DEBUG] clck_gen.py:102 IND CLOCK 9894
2025-04-27 03:32:01 [DEBUG] clck_gen.py:102 IND CLOCK 9996
2025-04-27 03:32:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:32:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:32:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:32:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:32:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:32:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:32:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:32:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:32:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:32:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:32:02 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:32:02 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:32:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:32:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:32:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:32:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:32:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:32:02 [DEBUG] clck_gen.py:102 IND CLOCK 10098
2025-04-27 03:32:02 [DEBUG] clck_gen.py:102 IND CLOCK 10200
2025-04-27 03:32:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:32:03 [DEBUG] clck_gen.py:102 IND CLOCK 10302
2025-04-27 03:32:03 [DEBUG] clck_gen.py:102 IND CLOCK 10404
2025-04-27 03:32:04 [DEBUG] clck_gen.py:102 IND CLOCK 10506
2025-04-27 03:32:04 [DEBUG] clck_gen.py:102 IND CLOCK 10608
2025-04-27 03:32:05 [DEBUG] clck_gen.py:102 IND CLOCK 10710
2025-04-27 03:32:05 [DEBUG] clck_gen.py:102 IND CLOCK 10812
2025-04-27 03:32:06 [DEBUG] clck_gen.py:102 IND CLOCK 10914
2025-04-27 03:32:06 [DEBUG] clck_gen.py:102 IND CLOCK 11016
2025-04-27 03:32:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:32:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:32:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:32:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:32:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:32:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:32:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:32:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:32:07 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:32:07 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:32:07 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:32:07 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:32:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:32:07 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:32:07 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:32:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:32:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:32:07 [DEBUG] clck_gen.py:102 IND CLOCK 11118
2025-04-27 03:32:07 [DEBUG] clck_gen.py:102 IND CLOCK 11220
2025-04-27 03:32:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:32:08 [DEBUG] clck_gen.py:102 IND CLOCK 11322
2025-04-27 03:32:08 [DEBUG] clck_gen.py:102 IND CLOCK 11424
2025-04-27 03:32:09 [DEBUG] clck_gen.py:102 IND CLOCK 11526
2025-04-27 03:32:09 [DEBUG] clck_gen.py:102 IND CLOCK 11628
2025-04-27 03:32:10 [DEBUG] clck_gen.py:102 IND CLOCK 11730
2025-04-27 03:32:10 [DEBUG] clck_gen.py:102 IND CLOCK 11832
2025-04-27 03:32:10 [DEBUG] clck_gen.py:102 IND CLOCK 11934
2025-04-27 03:32:11 [DEBUG] clck_gen.py:102 IND CLOCK 12036
2025-04-27 03:32:11 [DEBUG] clck_gen.py:102 IND CLOCK 12138
2025-04-27 03:32:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:32:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:32:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:32:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:32:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:32:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:32:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:32:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:32:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:32:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:32:11 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:32:11 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:32:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:32:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:32:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:32:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:32:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:32:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:32:12 [DEBUG] clck_gen.py:102 IND CLOCK 12240
2025-04-27 03:32:12 [DEBUG] clck_gen.py:102 IND CLOCK 12342
2025-04-27 03:32:13 [DEBUG] clck_gen.py:102 IND CLOCK 12444
2025-04-27 03:32:13 [DEBUG] clck_gen.py:102 IND CLOCK 12546
2025-04-27 03:32:14 [DEBUG] clck_gen.py:102 IND CLOCK 12648
2025-04-27 03:32:14 [DEBUG] clck_gen.py:102 IND CLOCK 12750
2025-04-27 03:32:15 [DEBUG] clck_gen.py:102 IND CLOCK 12852
2025-04-27 03:32:15 [DEBUG] clck_gen.py:102 IND CLOCK 12954
2025-04-27 03:32:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:32:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:32:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:32:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:32:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:32:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:32:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:32:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:32:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:32:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:32:16 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:32:16 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:32:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:32:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:32:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:32:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:32:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:32:16 [DEBUG] clck_gen.py:102 IND CLOCK 13056
2025-04-27 03:32:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:32:16 [DEBUG] clck_gen.py:102 IND CLOCK 13158
2025-04-27 03:32:17 [DEBUG] clck_gen.py:102 IND CLOCK 13260
2025-04-27 03:32:17 [DEBUG] clck_gen.py:102 IND CLOCK 13362
2025-04-27 03:32:18 [DEBUG] clck_gen.py:102 IND CLOCK 13464
2025-04-27 03:32:18 [DEBUG] clck_gen.py:102 IND CLOCK 13566
2025-04-27 03:32:19 [DEBUG] clck_gen.py:102 IND CLOCK 13668
2025-04-27 03:32:19 [DEBUG] clck_gen.py:102 IND CLOCK 13770
2025-04-27 03:32:19 [DEBUG] clck_gen.py:102 IND CLOCK 13872
2025-04-27 03:32:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:32:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:32:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:32:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:32:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:32:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:32:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:32:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:32:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:32:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:32:20 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:32:20 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:32:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:32:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:32:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:32:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:32:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:32:20 [DEBUG] clck_gen.py:102 IND CLOCK 13974
2025-04-27 03:32:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:32:20 [DEBUG] clck_gen.py:102 IND CLOCK 14076
2025-04-27 03:32:21 [DEBUG] clck_gen.py:102 IND CLOCK 14178
2025-04-27 03:32:21 [DEBUG] clck_gen.py:102 IND CLOCK 14280
2025-04-27 03:32:22 [DEBUG] clck_gen.py:102 IND CLOCK 14382
2025-04-27 03:32:22 [DEBUG] clck_gen.py:102 IND CLOCK 14484
2025-04-27 03:32:23 [DEBUG] clck_gen.py:102 IND CLOCK 14586
2025-04-27 03:32:23 [DEBUG] clck_gen.py:102 IND CLOCK 14688
2025-04-27 03:32:24 [DEBUG] clck_gen.py:102 IND CLOCK 14790
2025-04-27 03:32:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:32:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:32:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:32:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:32:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:32:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:32:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:32:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:32:24 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:32:24 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:32:24 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:32:24 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:32:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:32:24 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:32:24 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:32:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:32:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:32:24 [DEBUG] clck_gen.py:102 IND CLOCK 14892
2025-04-27 03:32:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:32:25 [DEBUG] clck_gen.py:102 IND CLOCK 14994
2025-04-27 03:32:25 [DEBUG] clck_gen.py:102 IND CLOCK 15096
2025-04-27 03:32:26 [DEBUG] clck_gen.py:102 IND CLOCK 15198
2025-04-27 03:32:26 [DEBUG] clck_gen.py:102 IND CLOCK 15300
2025-04-27 03:32:27 [DEBUG] clck_gen.py:102 IND CLOCK 15402
2025-04-27 03:32:27 [DEBUG] clck_gen.py:102 IND CLOCK 15504
2025-04-27 03:32:28 [DEBUG] clck_gen.py:102 IND CLOCK 15606
2025-04-27 03:32:28 [DEBUG] clck_gen.py:102 IND CLOCK 15708
2025-04-27 03:32:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:32:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:32:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:32:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:32:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:32:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:32:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:32:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:32:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:32:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:32:28 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:32:28 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:32:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:32:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:32:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:32:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:32:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:32:28 [DEBUG] clck_gen.py:102 IND CLOCK 15810
2025-04-27 03:32:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:32:29 [DEBUG] clck_gen.py:102 IND CLOCK 15912
2025-04-27 03:32:29 [DEBUG] clck_gen.py:102 IND CLOCK 16014
2025-04-27 03:32:30 [DEBUG] clck_gen.py:102 IND CLOCK 16116
2025-04-27 03:32:30 [DEBUG] clck_gen.py:102 IND CLOCK 16218
2025-04-27 03:32:31 [DEBUG] clck_gen.py:102 IND CLOCK 16320
2025-04-27 03:32:31 [DEBUG] clck_gen.py:102 IND CLOCK 16422
2025-04-27 03:32:32 [DEBUG] clck_gen.py:102 IND CLOCK 16524
2025-04-27 03:32:32 [DEBUG] clck_gen.py:102 IND CLOCK 16626
2025-04-27 03:32:33 [DEBUG] clck_gen.py:102 IND CLOCK 16728
2025-04-27 03:32:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:32:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:32:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:32:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:32:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:32:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:32:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:32:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:32:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:32:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:32:33 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:32:33 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:32:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:32:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:32:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:32:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:32:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:32:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:32:33 [DEBUG] clck_gen.py:102 IND CLOCK 16830
2025-04-27 03:32:34 [DEBUG] clck_gen.py:102 IND CLOCK 16932
2025-04-27 03:32:34 [DEBUG] clck_gen.py:102 IND CLOCK 17034
2025-04-27 03:32:35 [DEBUG] clck_gen.py:102 IND CLOCK 17136
2025-04-27 03:32:35 [DEBUG] clck_gen.py:102 IND CLOCK 17238
2025-04-27 03:32:36 [DEBUG] clck_gen.py:102 IND CLOCK 17340
2025-04-27 03:32:36 [DEBUG] clck_gen.py:102 IND CLOCK 17442
2025-04-27 03:32:37 [DEBUG] clck_gen.py:102 IND CLOCK 17544
2025-04-27 03:32:37 [DEBUG] clck_gen.py:102 IND CLOCK 17646
2025-04-27 03:32:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:32:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:32:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:32:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:32:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:32:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:32:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:32:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:32:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:32:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:32:37 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:32:37 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:32:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:32:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:32:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:32:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:32:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:32:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:32:37 [DEBUG] clck_gen.py:102 IND CLOCK 17748
2025-04-27 03:32:38 [DEBUG] clck_gen.py:102 IND CLOCK 17850
2025-04-27 03:32:38 [DEBUG] clck_gen.py:102 IND CLOCK 17952
2025-04-27 03:32:39 [DEBUG] clck_gen.py:102 IND CLOCK 18054
2025-04-27 03:32:39 [DEBUG] clck_gen.py:102 IND CLOCK 18156
2025-04-27 03:32:40 [DEBUG] clck_gen.py:102 IND CLOCK 18258
2025-04-27 03:32:40 [DEBUG] clck_gen.py:102 IND CLOCK 18360
2025-04-27 03:32:41 [DEBUG] clck_gen.py:102 IND CLOCK 18462
2025-04-27 03:32:41 [DEBUG] clck_gen.py:102 IND CLOCK 18564
2025-04-27 03:32:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:32:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:32:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:32:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:32:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:32:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:32:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:32:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:32:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:32:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:32:41 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:32:41 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:32:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:32:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:32:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:32:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:32:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:32:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:32:42 [DEBUG] clck_gen.py:102 IND CLOCK 18666
2025-04-27 03:32:42 [DEBUG] clck_gen.py:102 IND CLOCK 18768
2025-04-27 03:32:43 [DEBUG] clck_gen.py:102 IND CLOCK 18870
2025-04-27 03:32:43 [DEBUG] clck_gen.py:102 IND CLOCK 18972
2025-04-27 03:32:44 [DEBUG] clck_gen.py:102 IND CLOCK 19074
2025-04-27 03:32:44 [DEBUG] clck_gen.py:102 IND CLOCK 19176
2025-04-27 03:32:45 [DEBUG] clck_gen.py:102 IND CLOCK 19278
2025-04-27 03:32:45 [DEBUG] clck_gen.py:102 IND CLOCK 19380
2025-04-27 03:32:46 [DEBUG] clck_gen.py:102 IND CLOCK 19482
2025-04-27 03:32:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:32:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:32:46 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:32:46 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:32:46 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:32:46 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:32:46 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:32:46 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:32:46 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:32:46 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:32:46 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:32:46 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:32:46 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:32:46 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 03:32:46 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:32:51 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:32:51 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:32:51 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:32:51 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:32:51 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:32:51 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:32:51 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:32:51 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:32:51 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:32:51 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:32:51 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 03:32:51 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 03:32:51 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 03:32:51 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:32:51 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:32:51 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:32:51 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 03:32:51 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:32:51 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 03:32:51 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 03:32:51 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 03:32:51 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:32:51 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:32:51 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:32:51 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 03:32:51 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:32:51 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 03:32:51 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 03:32:51 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 03:32:51 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:32:51 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:32:51 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:32:51 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 03:32:51 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:32:51 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 03:32:51 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 03:32:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 03:32:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 03:32:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 03:32:51 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 03:32:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 03:32:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 03:32:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 03:32:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 03:32:51 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 03:32:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:32:51 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 03:32:51 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 03:32:51 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 03:32:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:32:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:32:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:32:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 03:32:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:32:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:32:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:32:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:32:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:32:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:32:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:32:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:32:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:32:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:32:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:32:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:32:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:32:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:32:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:32:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:32:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:32:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:32:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:32:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:32:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:32:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:32:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:32:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:32:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:32:51 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:32:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:32:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:32:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:32:51 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:32:51 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:32:51 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:32:51 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:32:51 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:32:51 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 03:32:56 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:32:56 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:32:56 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:32:56 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:32:56 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:32:56 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:32:56 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:32:56 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:32:56 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:32:56 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:32:56 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 03:32:56 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 03:32:56 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 03:32:56 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:32:56 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:32:56 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:32:56 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 03:32:56 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:32:56 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 03:32:56 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 03:32:56 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 03:32:56 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:32:56 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:32:56 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:32:56 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 03:32:56 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:32:56 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 03:32:56 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 03:32:56 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 03:32:56 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:32:56 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:32:56 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:32:56 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 03:32:56 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:32:56 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 03:32:56 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 03:32:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 03:32:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 03:32:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 03:32:56 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 03:32:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 03:32:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 03:32:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 03:32:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:32:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 03:32:56 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 03:32:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:32:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:32:56 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 03:32:56 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 03:32:56 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 03:32:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:32:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:32:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:32:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 03:32:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:32:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:32:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:32:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:32:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:32:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:32:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:32:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:32:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:32:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:32:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:32:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:32:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:32:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:32:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:32:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:32:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:32:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:32:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:32:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:32:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:32:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:32:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:32:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:32:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:32:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:32:56 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 03:32:56 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 03:32:56 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 03:32:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:32:56 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 03:32:56 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 03:32:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:32:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:32:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:32:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:32:56 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:32:56 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:32:56 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:32:56 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:32:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:32:56 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:32:56 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:32:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:32:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:32:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:32:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:32:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:32:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:32:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:32:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:32:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:32:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:32:56 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:32:56 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:32:56 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:32:56 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:32:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:32:57 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:32:57 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:32:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:32:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:32:57 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 03:32:57 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:32:57 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:32:57 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:32:57 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:32:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:32:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:32:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:32:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:32:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:32:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:32:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:32:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:32:57 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:32:57 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:32:57 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:32:57 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:32:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:32:57 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:32:57 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:32:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:32:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:32:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:32:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:32:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:32:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:32:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:32:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:32:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:32:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:32:57 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:32:57 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:32:57 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:32:57 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:32:57 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 03:32:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:32:57 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:32:57 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:32:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:32:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:32:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:32:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:32:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:32:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:32:58 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 03:32:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:32:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:32:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:32:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:32:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:32:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:32:58 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:32:58 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:32:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:32:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:32:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:32:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:32:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:32:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:32:58 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:32:58 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:32:58 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:32:58 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 03:32:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:32:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:32:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:32:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:32:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:32:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:32:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:32:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:32:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:32:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:32:58 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:32:58 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:32:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:32:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:32:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:32:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:32:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:32:59 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 03:32:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:32:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:32:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:32:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:32:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:32:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:32:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:32:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:32:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:32:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:32:59 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:32:59 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:32:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:32:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:32:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:32:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:32:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:32:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:32:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:32:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:32:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:32:59 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 03:32:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:32:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:32:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:32:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:32:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:32:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:32:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:32:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:32:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:32:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:32:59 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:32:59 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:32:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:32:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:32:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:32:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:32:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:32:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:00 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 03:33:00 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:33:00 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:33:00 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:33:00 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:33:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:33:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:33:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:33:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:33:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:33:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:33:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:33:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:33:00 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:33:00 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:33:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:33:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:33:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:33:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:00 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 03:33:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:33:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:33:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:33:00 [WARNING] transceiver.py:250 (MS@172.18.127.22:6700) RX TRXD message (fn=988 tn=6 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:33:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:33:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:33:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:33:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:33:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:33:00 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:33:00 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:33:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:33:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:33:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:33:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:33:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:01 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 03:33:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:33:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:33:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:33:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:33:01 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 03:33:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:33:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:33:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:33:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:33:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:33:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:33:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:33:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:33:01 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:33:01 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:33:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:33:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:33:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:33:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:01 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 03:33:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:33:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:33:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:33:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:33:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:33:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:33:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:33:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:33:02 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:33:02 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:33:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:33:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:33:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:33:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:02 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 03:33:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:33:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:33:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:33:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:33:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:33:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:33:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:33:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:33:02 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:33:02 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:33:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:33:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:33:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:33:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:02 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 03:33:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:33:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:33:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:33:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:33:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:33:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:33:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:33:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:33:03 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:33:03 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:33:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:33:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:33:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:33:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:03 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 03:33:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:33:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:33:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:33:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:33:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:33:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:33:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:33:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:33:03 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:33:03 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:33:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:33:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:33:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:33:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:03 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 03:33:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:33:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:33:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:33:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:33:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:33:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:33:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:33:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:33:04 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:33:04 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:33:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:33:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:33:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:33:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:04 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 03:33:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:33:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:33:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:33:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:33:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:33:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:33:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:33:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:33:04 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:33:04 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:33:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:33:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:33:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:33:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:33:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:33:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:33:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:33:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:33:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:33:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:33:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:33:04 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:33:04 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:33:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:33:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:33:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:33:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:04 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 03:33:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:33:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:33:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:33:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:33:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:33:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:33:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:33:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:33:05 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:33:05 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:33:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:33:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:33:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:33:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:05 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 03:33:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:33:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:33:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:33:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:33:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:33:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:33:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:33:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:33:05 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:33:05 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:33:05 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 03:33:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:33:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:33:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:33:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:33:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:33:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:33:06 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:33:06 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:33:06 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:33:06 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:33:06 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:33:06 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:33:06 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:33:06 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:33:06 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:33:06 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 03:33:06 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2143 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:33:06 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:33:06 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2143 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:33:06 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2143 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:33:06 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2143 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:33:06 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2143 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:33:06 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2143 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:33:06 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2143 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:33:06 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2143 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:33:11 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:33:11 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:33:11 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:33:11 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:33:11 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:33:11 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:33:11 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:33:11 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:33:11 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:33:11 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:33:11 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 03:33:11 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 03:33:11 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 03:33:11 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:33:11 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:33:11 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:33:11 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 03:33:11 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:33:11 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 03:33:11 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 03:33:11 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 03:33:11 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:33:11 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:33:11 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:33:11 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 03:33:11 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:33:11 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 03:33:11 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 03:33:11 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 03:33:11 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:33:11 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:33:11 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:33:11 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 03:33:11 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:33:11 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 03:33:11 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 03:33:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 03:33:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 03:33:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 03:33:11 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 03:33:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 03:33:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 03:33:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 03:33:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 03:33:11 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 03:33:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:33:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:33:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:33:11 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 03:33:11 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 03:33:11 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 03:33:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:33:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:33:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:33:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 03:33:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:33:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:33:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:33:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:33:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:33:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:33:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:33:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:33:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:33:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:33:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:33:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:33:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:33:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:33:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:33:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:33:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:33:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:33:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:33:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:33:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:33:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:33:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:33:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:33:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:33:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:33:11 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 03:33:11 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 03:33:11 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 03:33:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:33:11 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 03:33:11 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 03:33:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:33:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:33:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:33:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:33:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:33:11 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:33:11 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:33:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:33:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:33:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:33:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:12 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 03:33:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:33:12 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:33:12 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:33:12 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:33:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:33:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:33:12 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 03:33:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:33:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:33:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:33:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:33:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:33:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:33:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:33:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:33:12 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:33:12 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:33:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:33:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:33:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:33:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:13 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 03:33:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:33:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:33:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:33:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:33:13 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 03:33:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:33:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:33:14 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 03:33:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:33:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:33:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:33:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:33:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:33:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:33:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:33:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:33:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:33:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:33:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:14 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:33:14 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:33:14 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:33:14 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:33:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:33:14 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:33:14 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:33:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:14 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 03:33:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:33:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:33:15 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 03:33:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:33:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:33:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:33:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:33:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:33:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:33:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:33:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:33:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:33:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:33:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:15 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:33:15 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:33:15 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:33:15 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:33:15 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 03:33:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:33:15 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:33:15 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:33:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:16 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 03:33:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:33:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:33:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:33:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:33:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:33:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:33:16 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 03:33:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:33:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:33:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:33:16 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 03:33:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:33:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:33:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:33:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:33:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:33:16 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:33:16 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:33:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:33:17 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:33:17 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:33:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:17 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 03:33:17 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 03:33:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:33:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:33:18 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 03:33:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:33:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:33:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:33:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:33:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:33:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:33:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:33:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:33:18 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:33:18 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:33:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:33:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:33:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:33:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:18 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 03:33:19 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 03:33:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:33:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:33:19 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 03:33:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:33:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:33:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:33:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:33:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:33:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:33:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:33:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:33:20 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:33:20 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:33:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:33:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:33:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:33:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:20 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 03:33:20 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 03:33:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:33:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:33:21 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 03:33:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:33:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:33:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:33:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:33:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:33:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:33:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:33:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:33:21 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:33:21 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:33:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:33:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:33:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:33:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:33:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:21 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 03:33:22 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-27 03:33:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:33:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:33:22 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-27 03:33:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:33:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:33:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:33:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:33:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:33:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:33:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:23 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:33:23 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:33:23 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:33:23 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:33:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:33:23 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:33:23 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:33:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:23 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-27 03:33:23 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-27 03:33:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:33:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:33:24 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-27 03:33:24 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-27 03:33:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:33:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:33:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:33:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:33:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:33:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:33:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:24 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:33:24 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:33:24 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:33:24 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:33:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:33:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:33:24 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:33:24 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:33:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:25 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-27 03:33:25 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-27 03:33:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:33:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:33:25 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-27 03:33:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:33:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:33:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:33:26 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-27 03:33:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:33:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:33:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:33:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:33:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:33:26 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:33:26 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:33:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:33:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:33:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:33:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:26 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-27 03:33:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:33:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:33:27 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-27 03:33:27 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-27 03:33:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:33:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:33:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:33:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:33:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:33:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:33:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:27 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:33:27 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:33:27 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:33:27 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:33:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:33:27 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:33:27 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:33:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:28 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-27 03:33:28 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-27 03:33:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:33:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:33:29 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-27 03:33:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:33:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:33:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:33:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:33:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:33:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:33:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:29 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:33:29 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:33:29 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:33:29 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:33:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:33:29 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:33:29 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:33:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:29 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2025-04-27 03:33:30 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2025-04-27 03:33:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:33:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:33:30 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2025-04-27 03:33:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:33:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:33:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:33:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:33:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:33:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:33:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:30 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:33:30 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:33:30 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:33:30 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:33:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:33:30 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:33:30 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:33:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:31 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2025-04-27 03:33:31 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2025-04-27 03:33:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:33:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:33:32 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2025-04-27 03:33:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:33:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:33:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:33:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:33:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:33:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:33:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:32 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:33:32 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:33:32 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:33:32 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:33:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:33:32 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:33:32 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:33:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:32 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2025-04-27 03:33:33 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2025-04-27 03:33:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:33:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:33:33 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2025-04-27 03:33:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:33:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:33:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:33:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:33:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:33:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:33:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:33:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:33:33 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:33:33 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:33:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:33:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:33:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:33:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:34 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2025-04-27 03:33:34 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2025-04-27 03:33:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:33:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:33:34 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2025-04-27 03:33:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:33:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:33:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:33:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:33:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:33:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:33:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:35 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:33:35 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:33:35 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:33:35 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:33:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:33:35 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:33:35 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:33:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:35 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2025-04-27 03:33:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:33:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:33:35 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2025-04-27 03:33:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:33:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:36 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:33:36 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:33:36 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:33:36 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:33:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:33:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:36 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:33:36 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:33:36 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:33:36 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:33:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:33:36 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:33:36 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:33:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:36 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2025-04-27 03:33:36 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2025-04-27 03:33:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:33:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:33:37 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2025-04-27 03:33:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:33:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:33:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:33:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:33:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:33:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:33:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:33:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:33:37 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:33:37 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:33:37 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2025-04-27 03:33:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:33:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:33:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:33:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:38 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2025-04-27 03:33:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:33:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:33:38 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2025-04-27 03:33:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:33:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:33:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:33:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:33:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:33:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:33:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:39 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:33:39 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:33:39 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:33:39 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:33:39 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2025-04-27 03:33:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:33:39 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:33:39 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:33:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:39 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2025-04-27 03:33:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:33:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:33:40 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2025-04-27 03:33:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:33:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:33:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:33:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:33:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:33:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:33:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:33:40 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:33:40 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:33:40 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:33:40 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:33:40 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:33:40 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:33:40 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 03:33:40 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=6323 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:33:40 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=6323 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:33:40 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=6323 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:33:40 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=6323 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:33:40 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=6324 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:33:40 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=6324 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:33:40 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=6324 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:33:40 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=6324 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:33:40 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=6324 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:33:40 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=6324 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:33:40 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=6324 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:33:40 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=6324 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:33:45 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:33:45 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:33:45 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:33:45 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:33:45 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:33:45 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:33:45 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:33:45 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:33:45 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:33:45 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:33:45 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 03:33:45 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 03:33:45 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 03:33:45 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:33:45 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:33:45 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:33:45 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 03:33:45 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:33:45 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 03:33:45 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 03:33:45 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 03:33:45 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:33:45 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:33:45 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:33:45 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 03:33:45 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:33:45 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 03:33:45 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 03:33:45 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 03:33:45 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:33:45 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:33:45 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:33:45 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 03:33:45 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:33:45 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 03:33:45 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 03:33:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 03:33:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 03:33:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 03:33:45 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 03:33:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 03:33:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 03:33:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 03:33:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:33:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 03:33:45 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 03:33:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:33:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:33:45 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 03:33:45 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 03:33:45 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 03:33:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:33:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:33:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:33:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 03:33:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:33:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:33:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:33:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:33:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:33:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:33:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:33:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:33:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:33:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:33:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:33:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:33:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:33:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:33:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:33:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:33:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:33:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:33:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:33:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:33:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:33:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:33:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:33:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:33:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:33:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:33:45 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 03:33:46 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 03:33:46 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 03:33:46 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 03:33:46 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 03:33:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:33:46 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:33:46 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:33:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:33:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:46 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:33:46 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:33:46 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:33:46 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:33:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:33:46 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:33:46 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:33:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:46 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 03:33:46 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:33:46 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:33:46 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:33:46 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:33:47 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 03:33:47 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 03:33:47 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:33:47 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:33:47 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:33:47 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:33:48 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 03:33:48 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 03:33:48 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:33:48 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:33:48 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:33:48 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:33:48 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 03:33:49 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 03:33:49 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:33:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:33:49 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:33:49 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:33:49 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 03:33:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:33:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:33:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:33:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:33:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:33:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:33:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:50 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:33:50 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:33:50 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:33:50 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:33:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:33:50 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:33:50 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:33:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:50 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 03:33:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:33:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:33:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:33:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:33:50 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 03:33:51 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 03:33:51 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 03:33:52 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 03:33:52 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 03:33:53 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 03:33:53 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 03:33:54 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 03:33:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:33:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:33:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:33:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:33:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:33:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:33:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:33:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:33:54 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:33:54 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:33:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:33:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:33:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:33:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:54 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 03:33:55 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 03:33:55 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 03:33:56 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 03:33:56 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-27 03:33:57 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-27 03:33:57 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-27 03:33:58 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-27 03:33:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:33:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:33:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:33:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:33:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:33:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:33:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:33:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:33:58 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:33:58 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:33:58 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-27 03:33:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:33:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:33:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:33:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:33:58 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-27 03:33:59 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-27 03:33:59 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-27 03:34:00 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-27 03:34:00 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-27 03:34:01 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-27 03:34:01 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-27 03:34:02 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-27 03:34:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:34:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:34:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:34:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:34:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:34:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:34:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:34:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:34:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:34:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:34:02 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:34:02 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:34:02 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-27 03:34:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:34:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:34:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:34:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:34:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:34:03 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-27 03:34:03 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-27 03:34:04 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2025-04-27 03:34:04 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2025-04-27 03:34:05 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2025-04-27 03:34:05 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2025-04-27 03:34:06 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2025-04-27 03:34:06 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2025-04-27 03:34:07 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2025-04-27 03:34:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:34:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:34:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:34:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:34:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:34:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:34:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:34:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:34:07 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:34:07 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:34:07 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:34:07 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:34:07 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2025-04-27 03:34:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:34:07 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:34:07 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:34:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:34:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:34:07 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2025-04-27 03:34:08 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2025-04-27 03:34:08 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2025-04-27 03:34:09 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2025-04-27 03:34:09 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2025-04-27 03:34:10 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2025-04-27 03:34:10 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2025-04-27 03:34:11 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2025-04-27 03:34:11 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2025-04-27 03:34:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:34:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:34:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:34:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:34:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:34:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:34:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:34:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:34:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:34:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:34:11 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:34:11 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:34:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:34:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:34:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:34:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:34:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:34:12 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2025-04-27 03:34:12 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2025-04-27 03:34:13 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2025-04-27 03:34:13 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2025-04-27 03:34:14 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2025-04-27 03:34:14 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2025-04-27 03:34:15 [DEBUG] clck_gen.py:102 IND CLOCK 6324
2025-04-27 03:34:15 [DEBUG] clck_gen.py:102 IND CLOCK 6426
2025-04-27 03:34:16 [DEBUG] clck_gen.py:102 IND CLOCK 6528
2025-04-27 03:34:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:34:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:34:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:34:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:34:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:34:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:34:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:34:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:34:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:34:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:34:16 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:34:16 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:34:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:34:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:34:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:34:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:34:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:34:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:34:16 [DEBUG] clck_gen.py:102 IND CLOCK 6630
2025-04-27 03:34:16 [DEBUG] clck_gen.py:102 IND CLOCK 6732
2025-04-27 03:34:17 [DEBUG] clck_gen.py:102 IND CLOCK 6834
2025-04-27 03:34:17 [DEBUG] clck_gen.py:102 IND CLOCK 6936
2025-04-27 03:34:18 [DEBUG] clck_gen.py:102 IND CLOCK 7038
2025-04-27 03:34:18 [DEBUG] clck_gen.py:102 IND CLOCK 7140
2025-04-27 03:34:19 [DEBUG] clck_gen.py:102 IND CLOCK 7242
2025-04-27 03:34:19 [DEBUG] clck_gen.py:102 IND CLOCK 7344
2025-04-27 03:34:20 [DEBUG] clck_gen.py:102 IND CLOCK 7446
2025-04-27 03:34:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:34:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:34:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:34:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:34:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:34:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:34:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:34:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:34:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:34:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:34:20 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:34:20 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:34:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:34:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:34:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:34:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:34:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:34:20 [DEBUG] clck_gen.py:102 IND CLOCK 7548
2025-04-27 03:34:21 [DEBUG] clck_gen.py:102 IND CLOCK 7650
2025-04-27 03:34:21 [DEBUG] clck_gen.py:102 IND CLOCK 7752
2025-04-27 03:34:22 [DEBUG] clck_gen.py:102 IND CLOCK 7854
2025-04-27 03:34:22 [DEBUG] clck_gen.py:102 IND CLOCK 7956
2025-04-27 03:34:23 [DEBUG] clck_gen.py:102 IND CLOCK 8058
2025-04-27 03:34:23 [DEBUG] clck_gen.py:102 IND CLOCK 8160
2025-04-27 03:34:24 [DEBUG] clck_gen.py:102 IND CLOCK 8262
2025-04-27 03:34:24 [DEBUG] clck_gen.py:102 IND CLOCK 8364
2025-04-27 03:34:25 [DEBUG] clck_gen.py:102 IND CLOCK 8466
2025-04-27 03:34:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:34:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:34:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:34:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:34:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:34:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:34:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:34:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:34:25 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:34:25 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:34:25 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:34:25 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:34:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:34:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:34:25 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:34:25 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:34:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:34:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:34:25 [DEBUG] clck_gen.py:102 IND CLOCK 8568
2025-04-27 03:34:25 [DEBUG] clck_gen.py:102 IND CLOCK 8670
2025-04-27 03:34:26 [DEBUG] clck_gen.py:102 IND CLOCK 8772
2025-04-27 03:34:26 [DEBUG] clck_gen.py:102 IND CLOCK 8874
2025-04-27 03:34:27 [DEBUG] clck_gen.py:102 IND CLOCK 8976
2025-04-27 03:34:27 [DEBUG] clck_gen.py:102 IND CLOCK 9078
2025-04-27 03:34:28 [DEBUG] clck_gen.py:102 IND CLOCK 9180
2025-04-27 03:34:28 [DEBUG] clck_gen.py:102 IND CLOCK 9282
2025-04-27 03:34:29 [DEBUG] clck_gen.py:102 IND CLOCK 9384
2025-04-27 03:34:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:34:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:34:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:34:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:34:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:34:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:34:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:34:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:34:29 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:34:29 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:34:29 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:34:29 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:34:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:34:29 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:34:29 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:34:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:34:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:34:29 [DEBUG] clck_gen.py:102 IND CLOCK 9486
2025-04-27 03:34:30 [DEBUG] clck_gen.py:102 IND CLOCK 9588
2025-04-27 03:34:30 [DEBUG] clck_gen.py:102 IND CLOCK 9690
2025-04-27 03:34:31 [DEBUG] clck_gen.py:102 IND CLOCK 9792
2025-04-27 03:34:31 [DEBUG] clck_gen.py:102 IND CLOCK 9894
2025-04-27 03:34:32 [DEBUG] clck_gen.py:102 IND CLOCK 9996
2025-04-27 03:34:32 [DEBUG] clck_gen.py:102 IND CLOCK 10098
2025-04-27 03:34:33 [DEBUG] clck_gen.py:102 IND CLOCK 10200
2025-04-27 03:34:33 [DEBUG] clck_gen.py:102 IND CLOCK 10302
2025-04-27 03:34:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:34:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:34:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:34:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:34:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:34:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:34:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:34:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:34:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:34:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:34:33 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:34:33 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:34:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:34:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:34:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:34:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:34:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:34:34 [DEBUG] clck_gen.py:102 IND CLOCK 10404
2025-04-27 03:34:34 [DEBUG] clck_gen.py:102 IND CLOCK 10506
2025-04-27 03:34:35 [DEBUG] clck_gen.py:102 IND CLOCK 10608
2025-04-27 03:34:35 [DEBUG] clck_gen.py:102 IND CLOCK 10710
2025-04-27 03:34:35 [DEBUG] clck_gen.py:102 IND CLOCK 10812
2025-04-27 03:34:36 [DEBUG] clck_gen.py:102 IND CLOCK 10914
2025-04-27 03:34:36 [DEBUG] clck_gen.py:102 IND CLOCK 11016
2025-04-27 03:34:37 [DEBUG] clck_gen.py:102 IND CLOCK 11118
2025-04-27 03:34:37 [DEBUG] clck_gen.py:102 IND CLOCK 11220
2025-04-27 03:34:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:34:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:34:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:34:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:34:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:34:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:34:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:34:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:34:38 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:34:38 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:34:38 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:34:38 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:34:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:34:38 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:34:38 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:34:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:34:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:34:38 [DEBUG] clck_gen.py:102 IND CLOCK 11322
2025-04-27 03:34:38 [DEBUG] clck_gen.py:102 IND CLOCK 11424
2025-04-27 03:34:39 [DEBUG] clck_gen.py:102 IND CLOCK 11526
2025-04-27 03:34:39 [DEBUG] clck_gen.py:102 IND CLOCK 11628
2025-04-27 03:34:40 [DEBUG] clck_gen.py:102 IND CLOCK 11730
2025-04-27 03:34:40 [DEBUG] clck_gen.py:102 IND CLOCK 11832
2025-04-27 03:34:41 [DEBUG] clck_gen.py:102 IND CLOCK 11934
2025-04-27 03:34:41 [DEBUG] clck_gen.py:102 IND CLOCK 12036
2025-04-27 03:34:42 [DEBUG] clck_gen.py:102 IND CLOCK 12138
2025-04-27 03:34:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:34:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:34:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:34:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:34:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:34:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:34:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:34:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:34:42 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:34:42 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:34:42 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:34:42 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:34:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:34:42 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:34:42 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:34:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:34:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:34:42 [DEBUG] clck_gen.py:102 IND CLOCK 12240
2025-04-27 03:34:43 [DEBUG] clck_gen.py:102 IND CLOCK 12342
2025-04-27 03:34:43 [DEBUG] clck_gen.py:102 IND CLOCK 12444
2025-04-27 03:34:44 [DEBUG] clck_gen.py:102 IND CLOCK 12546
2025-04-27 03:34:44 [DEBUG] clck_gen.py:102 IND CLOCK 12648
2025-04-27 03:34:44 [DEBUG] clck_gen.py:102 IND CLOCK 12750
2025-04-27 03:34:45 [DEBUG] clck_gen.py:102 IND CLOCK 12852
2025-04-27 03:34:45 [DEBUG] clck_gen.py:102 IND CLOCK 12954
2025-04-27 03:34:46 [DEBUG] clck_gen.py:102 IND CLOCK 13056
2025-04-27 03:34:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:34:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:34:46 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:34:46 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:34:46 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:34:46 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:34:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:34:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:34:46 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:34:46 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:34:46 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:34:46 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:34:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:34:46 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:34:46 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:34:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:34:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:34:46 [DEBUG] clck_gen.py:102 IND CLOCK 13158
2025-04-27 03:34:47 [DEBUG] clck_gen.py:102 IND CLOCK 13260
2025-04-27 03:34:47 [DEBUG] clck_gen.py:102 IND CLOCK 13362
2025-04-27 03:34:48 [DEBUG] clck_gen.py:102 IND CLOCK 13464
2025-04-27 03:34:48 [DEBUG] clck_gen.py:102 IND CLOCK 13566
2025-04-27 03:34:49 [DEBUG] clck_gen.py:102 IND CLOCK 13668
2025-04-27 03:34:49 [DEBUG] clck_gen.py:102 IND CLOCK 13770
2025-04-27 03:34:50 [DEBUG] clck_gen.py:102 IND CLOCK 13872
2025-04-27 03:34:50 [DEBUG] clck_gen.py:102 IND CLOCK 13974
2025-04-27 03:34:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:34:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:34:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:34:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:34:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:34:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:34:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:34:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:34:50 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:34:50 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:34:50 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:34:50 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:34:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:34:50 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:34:50 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:34:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:34:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:34:51 [DEBUG] clck_gen.py:102 IND CLOCK 14076
2025-04-27 03:34:51 [DEBUG] clck_gen.py:102 IND CLOCK 14178
2025-04-27 03:34:52 [DEBUG] clck_gen.py:102 IND CLOCK 14280
2025-04-27 03:34:52 [DEBUG] clck_gen.py:102 IND CLOCK 14382
2025-04-27 03:34:53 [DEBUG] clck_gen.py:102 IND CLOCK 14484
2025-04-27 03:34:53 [DEBUG] clck_gen.py:102 IND CLOCK 14586
2025-04-27 03:34:53 [DEBUG] clck_gen.py:102 IND CLOCK 14688
2025-04-27 03:34:54 [DEBUG] clck_gen.py:102 IND CLOCK 14790
2025-04-27 03:34:54 [DEBUG] clck_gen.py:102 IND CLOCK 14892
2025-04-27 03:34:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:34:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:34:55 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:34:55 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:34:55 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:34:55 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:34:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:34:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:34:55 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:34:55 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:34:55 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:34:55 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:34:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:34:55 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:34:55 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:34:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:34:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:34:55 [DEBUG] clck_gen.py:102 IND CLOCK 14994
2025-04-27 03:34:55 [DEBUG] clck_gen.py:102 IND CLOCK 15096
2025-04-27 03:34:56 [DEBUG] clck_gen.py:102 IND CLOCK 15198
2025-04-27 03:34:56 [DEBUG] clck_gen.py:102 IND CLOCK 15300
2025-04-27 03:34:57 [DEBUG] clck_gen.py:102 IND CLOCK 15402
2025-04-27 03:34:57 [DEBUG] clck_gen.py:102 IND CLOCK 15504
2025-04-27 03:34:58 [DEBUG] clck_gen.py:102 IND CLOCK 15606
2025-04-27 03:34:58 [DEBUG] clck_gen.py:102 IND CLOCK 15708
2025-04-27 03:34:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:34:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:34:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:34:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:34:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:34:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:34:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:34:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:34:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:34:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:34:59 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:34:59 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:34:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:34:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:34:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:34:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:34:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:34:59 [DEBUG] clck_gen.py:102 IND CLOCK 15810
2025-04-27 03:34:59 [DEBUG] clck_gen.py:102 IND CLOCK 15912
2025-04-27 03:35:00 [DEBUG] clck_gen.py:102 IND CLOCK 16014
2025-04-27 03:35:00 [DEBUG] clck_gen.py:102 IND CLOCK 16116
2025-04-27 03:35:01 [DEBUG] clck_gen.py:102 IND CLOCK 16218
2025-04-27 03:35:01 [DEBUG] clck_gen.py:102 IND CLOCK 16320
2025-04-27 03:35:02 [DEBUG] clck_gen.py:102 IND CLOCK 16422
2025-04-27 03:35:02 [DEBUG] clck_gen.py:102 IND CLOCK 16524
2025-04-27 03:35:02 [DEBUG] clck_gen.py:102 IND CLOCK 16626
2025-04-27 03:35:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:35:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:35:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:35:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:35:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:35:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:35:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:35:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:35:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:35:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:35:03 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:35:03 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:35:03 [DEBUG] clck_gen.py:102 IND CLOCK 16728
2025-04-27 03:35:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:35:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:35:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:35:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:35:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:35:03 [DEBUG] clck_gen.py:102 IND CLOCK 16830
2025-04-27 03:35:04 [DEBUG] clck_gen.py:102 IND CLOCK 16932
2025-04-27 03:35:04 [DEBUG] clck_gen.py:102 IND CLOCK 17034
2025-04-27 03:35:05 [DEBUG] clck_gen.py:102 IND CLOCK 17136
2025-04-27 03:35:05 [DEBUG] clck_gen.py:102 IND CLOCK 17238
2025-04-27 03:35:06 [DEBUG] clck_gen.py:102 IND CLOCK 17340
2025-04-27 03:35:06 [DEBUG] clck_gen.py:102 IND CLOCK 17442
2025-04-27 03:35:07 [DEBUG] clck_gen.py:102 IND CLOCK 17544
2025-04-27 03:35:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:35:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:35:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:35:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:35:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:35:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:35:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:35:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:35:07 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:35:07 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:35:07 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:35:07 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:35:07 [DEBUG] clck_gen.py:102 IND CLOCK 17646
2025-04-27 03:35:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:35:07 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:35:07 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:35:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:35:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:35:08 [DEBUG] clck_gen.py:102 IND CLOCK 17748
2025-04-27 03:35:08 [DEBUG] clck_gen.py:102 IND CLOCK 17850
2025-04-27 03:35:09 [DEBUG] clck_gen.py:102 IND CLOCK 17952
2025-04-27 03:35:09 [DEBUG] clck_gen.py:102 IND CLOCK 18054
2025-04-27 03:35:10 [DEBUG] clck_gen.py:102 IND CLOCK 18156
2025-04-27 03:35:10 [DEBUG] clck_gen.py:102 IND CLOCK 18258
2025-04-27 03:35:11 [DEBUG] clck_gen.py:102 IND CLOCK 18360
2025-04-27 03:35:11 [DEBUG] clck_gen.py:102 IND CLOCK 18462
2025-04-27 03:35:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:35:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:35:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:35:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:35:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:35:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:35:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:35:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:35:11 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:35:11 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:35:11 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:35:11 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:35:11 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:35:11 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 03:35:11 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:35:11 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=18563 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:35:11 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=18563 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:35:11 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=18563 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:35:11 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=18563 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:35:11 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=18563 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:35:11 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=18563 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:35:11 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=18564 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:35:11 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=18564 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:35:11 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=18564 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:35:11 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=18564 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:35:11 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=18564 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:35:11 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=18564 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:35:11 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=18564 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:35:11 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=18564 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:35:16 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:35:16 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:35:16 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:35:16 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:35:16 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:35:16 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:35:16 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:35:16 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:35:16 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:35:16 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:35:16 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 03:35:16 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 03:35:16 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 03:35:16 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:35:16 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:35:16 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:35:16 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 03:35:16 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:35:16 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 03:35:16 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 03:35:16 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 03:35:16 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:35:16 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:35:16 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:35:16 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 03:35:16 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:35:16 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 03:35:16 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 03:35:16 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 03:35:16 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:35:16 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:35:16 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:35:16 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 03:35:16 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:35:16 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 03:35:16 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 03:35:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 03:35:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 03:35:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 03:35:16 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 03:35:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 03:35:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 03:35:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 03:35:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:35:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 03:35:16 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 03:35:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:35:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:35:16 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 03:35:16 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 03:35:16 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 03:35:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:35:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:35:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:35:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 03:35:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:35:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:35:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:35:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:35:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:35:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:35:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:35:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:35:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:35:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:35:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:35:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:35:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:35:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:35:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:35:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:35:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:35:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:35:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:35:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:35:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:35:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:35:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:35:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:35:16 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:35:16 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:35:16 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:35:16 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:35:16 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 03:35:16 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:35:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:35:21 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:35:21 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:35:22 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:35:22 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:35:22 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:35:22 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:35:22 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:35:22 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:35:22 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:35:22 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:35:22 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 03:35:22 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 03:35:22 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 03:35:22 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:35:22 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:35:22 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 03:35:22 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:35:22 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:35:22 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 03:35:22 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 03:35:22 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 03:35:22 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:35:22 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:35:22 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 03:35:22 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:35:22 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:35:22 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 03:35:22 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 03:35:22 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 03:35:22 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:35:22 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:35:22 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 03:35:22 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:35:22 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:35:22 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 03:35:22 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 03:35:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 03:35:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 03:35:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 03:35:22 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 03:35:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 03:35:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 03:35:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 03:35:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:35:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 03:35:22 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 03:35:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:35:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:35:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:35:22 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 03:35:22 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 03:35:22 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 03:35:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:35:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:35:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:35:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 03:35:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:35:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:35:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:35:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:35:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:35:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:35:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:35:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:35:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:35:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:35:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:35:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:35:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:35:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:35:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:35:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:35:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:35:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:35:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:35:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:35:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:35:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:35:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:35:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:35:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:35:22 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 03:35:22 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 03:35:22 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 03:35:22 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 03:35:22 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 03:35:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:35:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:35:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:35:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:35:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:35:22 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:35:22 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:35:22 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:35:22 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:35:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:35:22 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:35:22 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:35:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:35:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:35:22 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 03:35:23 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:35:23 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:35:23 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:35:23 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:35:23 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 03:35:23 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 03:35:24 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:35:24 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:35:24 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:35:24 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:35:24 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 03:35:24 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 03:35:25 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:35:25 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:35:25 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:35:25 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:35:25 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 03:35:25 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 03:35:26 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:35:26 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:35:26 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:35:26 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:35:26 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 03:35:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:35:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:35:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:35:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:35:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:35:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:35:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:35:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:35:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:35:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:35:26 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:35:26 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:35:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:35:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:35:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:35:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:35:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:35:26 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 03:35:27 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:35:27 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:35:27 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:35:27 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:35:27 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 03:35:27 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 03:35:28 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 03:35:28 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 03:35:29 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 03:35:29 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 03:35:30 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 03:35:30 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 03:35:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:35:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:35:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:35:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:35:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:35:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:35:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:35:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:35:30 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:35:30 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:35:30 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:35:30 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:35:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:35:31 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:35:31 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:35:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:35:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:35:31 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 03:35:31 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 03:35:31 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 03:35:32 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 03:35:32 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-27 03:35:33 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-27 03:35:33 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-27 03:35:34 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-27 03:35:34 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-27 03:35:35 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-27 03:35:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:35:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:35:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:35:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:35:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:35:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:35:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:35:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:35:35 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:35:35 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:35:35 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:35:35 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:35:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:35:35 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:35:35 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:35:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:35:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:35:35 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-27 03:35:36 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-27 03:35:36 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-27 03:35:37 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-27 03:35:37 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-27 03:35:38 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-27 03:35:38 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-27 03:35:39 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-27 03:35:39 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-27 03:35:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:35:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:35:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:35:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:35:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:35:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:35:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:35:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:35:39 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:35:39 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:35:39 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:35:39 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:35:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:35:39 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:35:39 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:35:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:35:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:35:40 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-27 03:35:40 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2025-04-27 03:35:40 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2025-04-27 03:35:41 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2025-04-27 03:35:41 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2025-04-27 03:35:42 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2025-04-27 03:35:42 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2025-04-27 03:35:43 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2025-04-27 03:35:43 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2025-04-27 03:35:44 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2025-04-27 03:35:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:35:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:35:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:35:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:35:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:35:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:35:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:35:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:35:44 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:35:44 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:35:44 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:35:44 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:35:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:35:44 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:35:44 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:35:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:35:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:35:44 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2025-04-27 03:35:45 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2025-04-27 03:35:45 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2025-04-27 03:35:46 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2025-04-27 03:35:46 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2025-04-27 03:35:47 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2025-04-27 03:35:47 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2025-04-27 03:35:48 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2025-04-27 03:35:48 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2025-04-27 03:35:48 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2025-04-27 03:35:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:35:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:35:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:35:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:35:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:35:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:35:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:35:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:35:49 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:35:49 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:35:49 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:35:49 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:35:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:35:49 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:35:49 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:35:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:35:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:35:49 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2025-04-27 03:35:49 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2025-04-27 03:35:50 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2025-04-27 03:35:50 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2025-04-27 03:35:51 [DEBUG] clck_gen.py:102 IND CLOCK 6324
2025-04-27 03:35:51 [DEBUG] clck_gen.py:102 IND CLOCK 6426
2025-04-27 03:35:52 [DEBUG] clck_gen.py:102 IND CLOCK 6528
2025-04-27 03:35:52 [DEBUG] clck_gen.py:102 IND CLOCK 6630
2025-04-27 03:35:53 [DEBUG] clck_gen.py:102 IND CLOCK 6732
2025-04-27 03:35:53 [DEBUG] clck_gen.py:102 IND CLOCK 6834
2025-04-27 03:35:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:35:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:35:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:35:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:35:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:35:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:35:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:35:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:35:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:35:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:35:54 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:35:54 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:35:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:35:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:35:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:35:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:35:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:35:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:35:54 [DEBUG] clck_gen.py:102 IND CLOCK 6936
2025-04-27 03:35:54 [DEBUG] clck_gen.py:102 IND CLOCK 7038
2025-04-27 03:35:55 [DEBUG] clck_gen.py:102 IND CLOCK 7140
2025-04-27 03:35:55 [DEBUG] clck_gen.py:102 IND CLOCK 7242
2025-04-27 03:35:56 [DEBUG] clck_gen.py:102 IND CLOCK 7344
2025-04-27 03:35:56 [DEBUG] clck_gen.py:102 IND CLOCK 7446
2025-04-27 03:35:57 [DEBUG] clck_gen.py:102 IND CLOCK 7548
2025-04-27 03:35:57 [DEBUG] clck_gen.py:102 IND CLOCK 7650
2025-04-27 03:35:58 [DEBUG] clck_gen.py:102 IND CLOCK 7752
2025-04-27 03:35:58 [DEBUG] clck_gen.py:102 IND CLOCK 7854
2025-04-27 03:35:58 [DEBUG] clck_gen.py:102 IND CLOCK 7956
2025-04-27 03:35:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:35:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:35:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:35:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:35:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:35:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:35:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:35:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:35:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:35:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:35:59 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:35:59 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:35:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:35:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:35:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:35:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:35:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:35:59 [DEBUG] clck_gen.py:102 IND CLOCK 8058
2025-04-27 03:35:59 [DEBUG] clck_gen.py:102 IND CLOCK 8160
2025-04-27 03:36:00 [DEBUG] clck_gen.py:102 IND CLOCK 8262
2025-04-27 03:36:00 [DEBUG] clck_gen.py:102 IND CLOCK 8364
2025-04-27 03:36:01 [DEBUG] clck_gen.py:102 IND CLOCK 8466
2025-04-27 03:36:01 [DEBUG] clck_gen.py:102 IND CLOCK 8568
2025-04-27 03:36:02 [DEBUG] clck_gen.py:102 IND CLOCK 8670
2025-04-27 03:36:02 [DEBUG] clck_gen.py:102 IND CLOCK 8772
2025-04-27 03:36:03 [DEBUG] clck_gen.py:102 IND CLOCK 8874
2025-04-27 03:36:03 [DEBUG] clck_gen.py:102 IND CLOCK 8976
2025-04-27 03:36:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:36:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:36:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:36:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:36:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:36:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:36:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:36:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:36:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:36:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:36:03 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:36:03 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:36:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:36:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:36:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:36:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:36:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:36:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:36:04 [DEBUG] clck_gen.py:102 IND CLOCK 9078
2025-04-27 03:36:04 [DEBUG] clck_gen.py:102 IND CLOCK 9180
2025-04-27 03:36:05 [DEBUG] clck_gen.py:102 IND CLOCK 9282
2025-04-27 03:36:05 [DEBUG] clck_gen.py:102 IND CLOCK 9384
2025-04-27 03:36:06 [DEBUG] clck_gen.py:102 IND CLOCK 9486
2025-04-27 03:36:06 [DEBUG] clck_gen.py:102 IND CLOCK 9588
2025-04-27 03:36:07 [DEBUG] clck_gen.py:102 IND CLOCK 9690
2025-04-27 03:36:07 [DEBUG] clck_gen.py:102 IND CLOCK 9792
2025-04-27 03:36:07 [DEBUG] clck_gen.py:102 IND CLOCK 9894
2025-04-27 03:36:08 [DEBUG] clck_gen.py:102 IND CLOCK 9996
2025-04-27 03:36:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:36:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:36:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:36:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:36:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:36:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:36:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:36:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:36:08 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:36:08 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:36:08 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:36:08 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:36:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:36:08 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:36:08 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:36:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:36:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:36:08 [DEBUG] clck_gen.py:102 IND CLOCK 10098
2025-04-27 03:36:09 [DEBUG] clck_gen.py:102 IND CLOCK 10200
2025-04-27 03:36:09 [DEBUG] clck_gen.py:102 IND CLOCK 10302
2025-04-27 03:36:10 [DEBUG] clck_gen.py:102 IND CLOCK 10404
2025-04-27 03:36:10 [DEBUG] clck_gen.py:102 IND CLOCK 10506
2025-04-27 03:36:11 [DEBUG] clck_gen.py:102 IND CLOCK 10608
2025-04-27 03:36:11 [DEBUG] clck_gen.py:102 IND CLOCK 10710
2025-04-27 03:36:12 [DEBUG] clck_gen.py:102 IND CLOCK 10812
2025-04-27 03:36:12 [DEBUG] clck_gen.py:102 IND CLOCK 10914
2025-04-27 03:36:13 [DEBUG] clck_gen.py:102 IND CLOCK 11016
2025-04-27 03:36:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:36:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:36:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:36:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:36:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:36:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:36:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:36:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:36:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:36:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:36:13 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:36:13 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:36:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:36:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:36:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:36:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:36:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:36:13 [DEBUG] clck_gen.py:102 IND CLOCK 11118
2025-04-27 03:36:14 [DEBUG] clck_gen.py:102 IND CLOCK 11220
2025-04-27 03:36:14 [DEBUG] clck_gen.py:102 IND CLOCK 11322
2025-04-27 03:36:15 [DEBUG] clck_gen.py:102 IND CLOCK 11424
2025-04-27 03:36:15 [DEBUG] clck_gen.py:102 IND CLOCK 11526
2025-04-27 03:36:16 [DEBUG] clck_gen.py:102 IND CLOCK 11628
2025-04-27 03:36:16 [DEBUG] clck_gen.py:102 IND CLOCK 11730
2025-04-27 03:36:17 [DEBUG] clck_gen.py:102 IND CLOCK 11832
2025-04-27 03:36:17 [DEBUG] clck_gen.py:102 IND CLOCK 11934
2025-04-27 03:36:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:36:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:36:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:36:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:36:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:36:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:36:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:36:17 [DEBUG] clck_gen.py:102 IND CLOCK 12036
2025-04-27 03:36:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:36:17 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:36:17 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:36:17 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:36:17 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:36:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:36:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:36:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:36:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:36:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:36:18 [DEBUG] clck_gen.py:102 IND CLOCK 12138
2025-04-27 03:36:18 [DEBUG] clck_gen.py:102 IND CLOCK 12240
2025-04-27 03:36:19 [DEBUG] clck_gen.py:102 IND CLOCK 12342
2025-04-27 03:36:19 [DEBUG] clck_gen.py:102 IND CLOCK 12444
2025-04-27 03:36:20 [DEBUG] clck_gen.py:102 IND CLOCK 12546
2025-04-27 03:36:20 [DEBUG] clck_gen.py:102 IND CLOCK 12648
2025-04-27 03:36:21 [DEBUG] clck_gen.py:102 IND CLOCK 12750
2025-04-27 03:36:21 [DEBUG] clck_gen.py:102 IND CLOCK 12852
2025-04-27 03:36:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:36:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:36:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:36:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:36:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:36:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:36:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:36:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:36:22 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:36:22 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:36:22 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:36:22 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:36:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:36:22 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:36:22 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:36:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:36:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:36:22 [DEBUG] clck_gen.py:102 IND CLOCK 12954
2025-04-27 03:36:22 [DEBUG] clck_gen.py:102 IND CLOCK 13056
2025-04-27 03:36:23 [DEBUG] clck_gen.py:102 IND CLOCK 13158
2025-04-27 03:36:23 [DEBUG] clck_gen.py:102 IND CLOCK 13260
2025-04-27 03:36:24 [DEBUG] clck_gen.py:102 IND CLOCK 13362
2025-04-27 03:36:24 [DEBUG] clck_gen.py:102 IND CLOCK 13464
2025-04-27 03:36:25 [DEBUG] clck_gen.py:102 IND CLOCK 13566
2025-04-27 03:36:25 [DEBUG] clck_gen.py:102 IND CLOCK 13668
2025-04-27 03:36:26 [DEBUG] clck_gen.py:102 IND CLOCK 13770
2025-04-27 03:36:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:36:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:36:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:36:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:36:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:36:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:36:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:36:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:36:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:36:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:36:26 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:36:26 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:36:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:36:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:36:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:36:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:36:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:36:26 [DEBUG] clck_gen.py:102 IND CLOCK 13872
2025-04-27 03:36:26 [DEBUG] clck_gen.py:102 IND CLOCK 13974
2025-04-27 03:36:27 [DEBUG] clck_gen.py:102 IND CLOCK 14076
2025-04-27 03:36:27 [DEBUG] clck_gen.py:102 IND CLOCK 14178
2025-04-27 03:36:28 [DEBUG] clck_gen.py:102 IND CLOCK 14280
2025-04-27 03:36:28 [DEBUG] clck_gen.py:102 IND CLOCK 14382
2025-04-27 03:36:29 [DEBUG] clck_gen.py:102 IND CLOCK 14484
2025-04-27 03:36:29 [DEBUG] clck_gen.py:102 IND CLOCK 14586
2025-04-27 03:36:30 [DEBUG] clck_gen.py:102 IND CLOCK 14688
2025-04-27 03:36:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:36:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:36:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:36:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:36:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:36:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:36:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:36:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:36:30 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:36:30 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:36:30 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:36:30 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:36:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:36:30 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:36:30 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:36:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:36:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:36:30 [DEBUG] clck_gen.py:102 IND CLOCK 14790
2025-04-27 03:36:31 [DEBUG] clck_gen.py:102 IND CLOCK 14892
2025-04-27 03:36:31 [DEBUG] clck_gen.py:102 IND CLOCK 14994
2025-04-27 03:36:32 [DEBUG] clck_gen.py:102 IND CLOCK 15096
2025-04-27 03:36:32 [DEBUG] clck_gen.py:102 IND CLOCK 15198
2025-04-27 03:36:33 [DEBUG] clck_gen.py:102 IND CLOCK 15300
2025-04-27 03:36:33 [DEBUG] clck_gen.py:102 IND CLOCK 15402
2025-04-27 03:36:34 [DEBUG] clck_gen.py:102 IND CLOCK 15504
2025-04-27 03:36:34 [DEBUG] clck_gen.py:102 IND CLOCK 15606
2025-04-27 03:36:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:36:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:36:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:36:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:36:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:36:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:36:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:36:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:36:34 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:36:34 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:36:34 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:36:34 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:36:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:36:34 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:36:34 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:36:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:36:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:36:35 [DEBUG] clck_gen.py:102 IND CLOCK 15708
2025-04-27 03:36:35 [DEBUG] clck_gen.py:102 IND CLOCK 15810
2025-04-27 03:36:35 [DEBUG] clck_gen.py:102 IND CLOCK 15912
2025-04-27 03:36:36 [DEBUG] clck_gen.py:102 IND CLOCK 16014
2025-04-27 03:36:36 [DEBUG] clck_gen.py:102 IND CLOCK 16116
2025-04-27 03:36:37 [DEBUG] clck_gen.py:102 IND CLOCK 16218
2025-04-27 03:36:37 [DEBUG] clck_gen.py:102 IND CLOCK 16320
2025-04-27 03:36:38 [DEBUG] clck_gen.py:102 IND CLOCK 16422
2025-04-27 03:36:38 [DEBUG] clck_gen.py:102 IND CLOCK 16524
2025-04-27 03:36:39 [DEBUG] clck_gen.py:102 IND CLOCK 16626
2025-04-27 03:36:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:36:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:36:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:36:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:36:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:36:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:36:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:36:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:36:39 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:36:39 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:36:39 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:36:39 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:36:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:36:39 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:36:39 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:36:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:36:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:36:39 [DEBUG] clck_gen.py:102 IND CLOCK 16728
2025-04-27 03:36:40 [DEBUG] clck_gen.py:102 IND CLOCK 16830
2025-04-27 03:36:40 [DEBUG] clck_gen.py:102 IND CLOCK 16932
2025-04-27 03:36:41 [DEBUG] clck_gen.py:102 IND CLOCK 17034
2025-04-27 03:36:41 [DEBUG] clck_gen.py:102 IND CLOCK 17136
2025-04-27 03:36:42 [DEBUG] clck_gen.py:102 IND CLOCK 17238
2025-04-27 03:36:42 [DEBUG] clck_gen.py:102 IND CLOCK 17340
2025-04-27 03:36:43 [DEBUG] clck_gen.py:102 IND CLOCK 17442
2025-04-27 03:36:43 [DEBUG] clck_gen.py:102 IND CLOCK 17544
2025-04-27 03:36:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:36:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:36:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:36:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:36:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:36:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:36:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:36:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:36:43 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:36:43 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:36:43 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:36:43 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:36:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:36:43 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:36:43 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:36:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:36:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:36:43 [DEBUG] clck_gen.py:102 IND CLOCK 17646
2025-04-27 03:36:44 [DEBUG] clck_gen.py:102 IND CLOCK 17748
2025-04-27 03:36:44 [DEBUG] clck_gen.py:102 IND CLOCK 17850
2025-04-27 03:36:45 [DEBUG] clck_gen.py:102 IND CLOCK 17952
2025-04-27 03:36:45 [DEBUG] clck_gen.py:102 IND CLOCK 18054
2025-04-27 03:36:46 [DEBUG] clck_gen.py:102 IND CLOCK 18156
2025-04-27 03:36:46 [DEBUG] clck_gen.py:102 IND CLOCK 18258
2025-04-27 03:36:47 [DEBUG] clck_gen.py:102 IND CLOCK 18360
2025-04-27 03:36:47 [DEBUG] clck_gen.py:102 IND CLOCK 18462
2025-04-27 03:36:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:36:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:36:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:36:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:36:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:36:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:36:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:36:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:36:47 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:36:47 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:36:47 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:36:47 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:36:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:36:47 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:36:47 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:36:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:36:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:36:48 [DEBUG] clck_gen.py:102 IND CLOCK 18564
2025-04-27 03:36:48 [DEBUG] clck_gen.py:102 IND CLOCK 18666
2025-04-27 03:36:49 [DEBUG] clck_gen.py:102 IND CLOCK 18768
2025-04-27 03:36:49 [DEBUG] clck_gen.py:102 IND CLOCK 18870
2025-04-27 03:36:50 [DEBUG] clck_gen.py:102 IND CLOCK 18972
2025-04-27 03:36:50 [DEBUG] clck_gen.py:102 IND CLOCK 19074
2025-04-27 03:36:51 [DEBUG] clck_gen.py:102 IND CLOCK 19176
2025-04-27 03:36:51 [DEBUG] clck_gen.py:102 IND CLOCK 19278
2025-04-27 03:36:52 [DEBUG] clck_gen.py:102 IND CLOCK 19380
2025-04-27 03:36:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:36:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:36:52 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:36:52 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:36:52 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:36:52 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:36:52 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:36:52 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:36:52 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:36:52 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:36:52 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:36:52 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:36:52 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 03:36:52 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:36:52 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:36:52 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=19415 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:36:52 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=19415 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:36:52 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=19415 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:36:52 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=19415 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:36:52 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=19415 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:36:52 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=19415 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:36:57 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:36:57 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:36:57 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:36:57 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:36:57 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:36:57 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:36:57 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:36:57 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:36:57 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:36:57 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:36:57 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 03:36:57 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 03:36:57 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 03:36:57 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:36:57 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:36:57 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:36:57 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 03:36:57 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:36:57 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 03:36:57 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 03:36:57 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 03:36:57 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:36:57 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:36:57 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:36:57 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 03:36:57 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:36:57 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 03:36:57 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 03:36:57 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 03:36:57 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:36:57 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:36:57 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:36:57 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 03:36:57 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:36:57 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 03:36:57 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 03:36:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 03:36:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 03:36:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 03:36:57 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 03:36:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 03:36:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 03:36:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 03:36:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:36:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 03:36:57 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 03:36:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:36:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:36:57 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 03:36:57 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 03:36:57 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 03:36:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:36:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:36:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:36:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 03:36:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:36:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:36:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:36:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:36:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:36:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:36:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:36:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:36:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:36:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:36:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:36:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:36:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:36:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:36:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:36:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:36:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:36:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:36:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:36:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:36:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:36:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:36:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:36:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:36:57 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:36:57 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:36:57 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:36:57 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:36:57 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 03:36:57 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:36:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:37:02 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:37:02 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:37:02 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:37:02 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:37:02 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:37:02 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:37:02 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:37:02 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:37:02 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:37:02 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:37:02 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 03:37:02 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 03:37:02 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 03:37:02 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:37:02 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:37:02 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:37:02 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 03:37:02 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:37:02 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 03:37:02 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 03:37:02 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 03:37:02 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:37:02 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:37:02 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:37:02 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 03:37:02 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:37:02 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 03:37:02 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 03:37:02 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 03:37:02 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:37:02 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:37:02 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:37:02 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 03:37:02 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:37:02 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 03:37:02 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 03:37:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 03:37:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 03:37:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 03:37:02 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 03:37:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 03:37:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 03:37:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 03:37:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:37:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 03:37:02 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 03:37:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:37:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:37:02 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 03:37:02 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 03:37:02 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 03:37:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:37:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:37:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:37:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 03:37:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:37:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:37:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:37:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:37:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:37:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:37:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:37:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:37:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:37:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:37:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:37:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:37:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:37:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:37:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:37:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:37:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:37:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:37:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:37:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:37:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:37:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:37:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:37:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:37:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:37:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:37:02 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 03:37:02 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 03:37:02 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 03:37:02 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 03:37:02 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 03:37:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:37:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:37:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:37:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:37:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:37:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:37:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:37:02 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:37:02 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:37:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:37:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:37:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:37:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:37:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:37:03 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 03:37:03 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:37:03 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:37:03 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:37:03 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:37:03 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 03:37:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:37:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:37:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:37:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:37:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:37:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:37:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:37:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:37:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:37:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:37:03 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:37:03 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:37:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:37:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:37:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:37:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:37:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:37:04 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 03:37:04 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:37:04 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:37:04 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:37:04 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:37:04 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 03:37:05 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 03:37:05 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:37:05 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:37:05 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:37:05 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:37:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:37:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:37:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:37:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:37:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:37:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:37:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:37:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:37:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:37:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:37:05 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:37:05 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:37:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:37:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:37:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:37:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:37:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:37:05 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 03:37:06 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 03:37:06 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:37:06 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:37:06 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:37:06 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:37:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:37:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:37:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:37:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:37:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:37:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:37:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:37:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:37:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:37:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:37:06 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:37:06 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:37:06 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 03:37:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:37:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:37:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:37:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:37:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:37:07 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 03:37:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:37:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:37:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:37:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:37:07 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 03:37:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:37:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:37:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:37:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:37:07 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 03:37:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:37:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:37:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:37:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:37:07 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:37:07 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:37:07 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:37:07 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:37:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:37:08 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:37:08 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:37:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:37:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:37:08 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 03:37:08 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 03:37:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:37:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:37:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:37:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:37:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:37:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:37:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:37:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:37:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:37:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:37:09 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:37:09 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:37:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:37:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:37:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:37:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:37:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:37:09 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 03:37:09 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 03:37:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:37:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:37:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:37:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:37:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:37:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:37:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:37:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:37:10 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:37:10 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:37:10 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:37:10 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:37:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:37:10 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:37:10 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:37:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:37:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:37:10 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 03:37:10 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 03:37:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:37:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:37:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:37:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:37:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:37:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:37:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:37:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:37:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:37:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:37:11 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:37:11 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:37:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:37:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:37:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:37:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:37:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:37:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:37:11 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 03:37:11 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 03:37:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:37:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:37:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:37:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:37:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:37:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:37:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:37:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:37:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:37:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:37:12 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:37:12 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:37:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:37:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:37:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:37:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:37:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:37:12 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 03:37:12 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 03:37:13 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-27 03:37:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:37:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:37:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:37:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:37:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:37:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:37:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:37:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:37:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:37:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:37:13 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:37:13 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:37:13 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-27 03:37:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:37:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:37:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:37:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:37:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:37:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:37:14 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-27 03:37:14 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-27 03:37:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:37:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:37:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:37:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:37:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:37:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:37:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:37:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:37:15 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:37:15 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:37:15 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:37:15 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:37:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:37:15 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-27 03:37:15 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:37:15 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:37:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:37:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:37:15 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-27 03:37:16 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-27 03:37:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:37:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:37:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:37:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:37:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:37:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:37:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:37:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:37:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:37:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:37:16 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:37:16 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:37:16 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-27 03:37:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:37:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:37:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:37:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:37:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:37:16 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-27 03:37:17 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-27 03:37:17 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-27 03:37:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:37:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:37:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:37:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:37:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:37:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:37:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:37:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:37:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:37:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:37:18 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:37:18 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:37:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:37:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:37:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:37:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:37:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:37:18 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-27 03:37:18 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-27 03:37:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:37:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:37:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:37:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:37:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:37:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:37:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:37:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:37:19 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:37:19 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:37:19 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:37:19 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:37:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:37:19 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:37:19 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:37:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:37:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:37:19 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-27 03:37:19 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-27 03:37:20 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-27 03:37:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:37:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:37:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:37:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:37:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:37:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:37:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:37:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:37:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:37:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:37:20 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:37:20 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:37:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:37:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:37:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:37:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:37:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:37:20 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2025-04-27 03:37:21 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2025-04-27 03:37:21 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2025-04-27 03:37:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:37:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:37:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:37:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:37:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:37:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:37:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:37:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:37:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:37:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:37:21 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:37:21 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:37:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:37:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:37:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:37:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:37:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:37:22 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2025-04-27 03:37:22 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2025-04-27 03:37:23 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2025-04-27 03:37:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:37:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:37:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:37:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:37:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:37:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:37:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:37:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:37:23 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:37:23 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:37:23 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:37:23 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:37:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:37:23 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:37:23 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:37:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:37:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:37:23 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2025-04-27 03:37:24 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2025-04-27 03:37:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:37:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:37:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:37:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:37:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:37:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:37:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:37:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:37:24 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:37:24 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:37:24 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:37:24 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:37:24 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2025-04-27 03:37:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:37:24 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:37:24 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:37:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:37:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:37:25 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2025-04-27 03:37:25 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2025-04-27 03:37:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:37:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:37:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:37:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:37:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:37:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:37:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:37:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:37:25 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:37:25 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:37:25 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:37:25 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:37:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:37:25 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2025-04-27 03:37:25 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:37:25 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:37:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:37:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:37:26 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2025-04-27 03:37:26 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2025-04-27 03:37:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:37:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:37:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:37:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:37:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:37:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:37:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:37:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:37:27 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:37:27 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:37:27 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:37:27 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:37:27 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2025-04-27 03:37:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:37:27 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:37:27 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:37:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:37:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:37:27 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2025-04-27 03:37:28 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2025-04-27 03:37:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:37:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:37:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:37:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:37:28 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:37:28 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:37:28 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:37:28 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:37:28 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:37:28 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:37:28 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:37:28 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:37:28 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:37:28 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:37:28 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 03:37:28 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=5712 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:37:28 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=5712 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:37:28 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=5712 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:37:28 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=5712 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:37:28 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=5712 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:37:28 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=5712 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:37:28 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=5712 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:37:33 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:37:33 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:37:33 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:37:33 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:37:33 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:37:33 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:37:33 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:37:33 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:37:33 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:37:33 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:37:33 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 03:37:33 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 03:37:33 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 03:37:33 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:37:33 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:37:33 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:37:33 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 03:37:33 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:37:33 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 03:37:33 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 03:37:33 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 03:37:33 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:37:33 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:37:33 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:37:33 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 03:37:33 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:37:33 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 03:37:33 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 03:37:33 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 03:37:33 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:37:33 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:37:33 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 03:37:33 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:37:33 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:37:33 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 03:37:33 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 03:37:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 03:37:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 03:37:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 03:37:33 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 03:37:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 03:37:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 03:37:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 03:37:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:37:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 03:37:33 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 03:37:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:37:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:37:33 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 03:37:33 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 03:37:33 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 03:37:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:37:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:37:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:37:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 03:37:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:37:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:37:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:37:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:37:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:37:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:37:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:37:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:37:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:37:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:37:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:37:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:37:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:37:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:37:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:37:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:37:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:37:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:37:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:37:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:37:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:37:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:37:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:37:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:37:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:37:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:37:33 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 03:37:34 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 03:37:34 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 03:37:34 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 03:37:34 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 03:37:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:37:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:37:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:37:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:37:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:37:34 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:37:34 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:37:34 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:37:34 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:37:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD HANDOVER
2025-04-27 03:37:34 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:37:34 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:37:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:37:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:37:34 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 03:37:34 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:37:34 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:37:34 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:37:34 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:37:35 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 03:37:35 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 03:37:35 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:37:35 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:37:35 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:37:35 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:37:36 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 03:37:36 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 03:37:36 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:37:36 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:37:36 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:37:36 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:37:37 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 03:37:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:37:37 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 03:37:37 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:37:37 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:37:37 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:37:37 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:37:38 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 03:37:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:37:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:37:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:37:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:37:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:37:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:37:38 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:37:38 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:37:38 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:37:38 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:37:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD HANDOVER
2025-04-27 03:37:38 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:37:38 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:37:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:37:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:37:38 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 03:37:38 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:37:38 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:37:38 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:37:38 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:37:39 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 03:37:39 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 03:37:40 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 03:37:40 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 03:37:40 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 03:37:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:37:41 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 03:37:41 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 03:37:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:37:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:37:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:37:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:37:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:37:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:37:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:37:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:37:42 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:37:42 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:37:42 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:37:42 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:37:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD HANDOVER
2025-04-27 03:37:42 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:37:42 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:37:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:37:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:37:42 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 03:37:42 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 03:37:43 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 03:37:43 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 03:37:44 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 03:37:44 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-27 03:37:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:37:45 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-27 03:37:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:37:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:37:45 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:37:45 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:37:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:37:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:37:45 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:37:45 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:37:45 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:37:45 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:37:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD HANDOVER
2025-04-27 03:37:45 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:37:45 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:37:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:37:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:37:45 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-27 03:37:46 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-27 03:37:46 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-27 03:37:47 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-27 03:37:47 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-27 03:37:48 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-27 03:37:48 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-27 03:37:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:37:49 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-27 03:37:49 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-27 03:37:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:37:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:37:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:37:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:37:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:37:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:37:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:37:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:37:49 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:37:49 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:37:49 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:37:49 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:37:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD HANDOVER
2025-04-27 03:37:49 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:37:49 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:37:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:37:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:37:49 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-27 03:37:50 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-27 03:37:50 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-27 03:37:51 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-27 03:37:51 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-27 03:37:52 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2025-04-27 03:37:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:37:52 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2025-04-27 03:37:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:37:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:37:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:37:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:37:53 [WARNING] transceiver.py:250 (MS@172.18.127.22:6700) RX TRXD message (fn=4177 tn=2 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:37:53 [WARNING] transceiver.py:250 (MS@172.18.127.22:6700) RX TRXD message (fn=4177 tn=3 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:37:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:37:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:37:53 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:37:53 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:37:53 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:37:53 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:37:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD HANDOVER
2025-04-27 03:37:53 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2025-04-27 03:37:53 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:37:53 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:37:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:37:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:37:53 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2025-04-27 03:37:54 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2025-04-27 03:37:54 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2025-04-27 03:37:55 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2025-04-27 03:37:55 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2025-04-27 03:37:56 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2025-04-27 03:37:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:37:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:37:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:37:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:37:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:37:56 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2025-04-27 03:37:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:37:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:37:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:37:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:37:56 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:37:56 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:37:56 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:37:56 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:37:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD HANDOVER
2025-04-27 03:37:56 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:37:56 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:37:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:37:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:37:57 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2025-04-27 03:37:57 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2025-04-27 03:37:58 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2025-04-27 03:37:58 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2025-04-27 03:37:58 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2025-04-27 03:37:59 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2025-04-27 03:37:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:37:59 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2025-04-27 03:38:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:38:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:38:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:38:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:38:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:38:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:38:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:38:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:38:00 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:38:00 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:38:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD HANDOVER
2025-04-27 03:38:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:38:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:38:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:38:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:38:00 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2025-04-27 03:38:00 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2025-04-27 03:38:01 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2025-04-27 03:38:01 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2025-04-27 03:38:02 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2025-04-27 03:38:02 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2025-04-27 03:38:03 [DEBUG] clck_gen.py:102 IND CLOCK 6324
2025-04-27 03:38:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:38:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:38:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:38:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:38:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:38:03 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:38:03 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:38:03 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:38:03 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:38:03 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:38:03 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:38:03 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:38:03 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:38:03 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:38:03 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:38:03 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 03:38:03 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=6414 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:38:03 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=6414 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:38:03 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=6414 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:38:03 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=6414 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:38:03 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=6414 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:38:03 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=6414 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:38:03 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=6415 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:38:03 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=6415 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:38:03 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=6415 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:38:03 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=6415 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:38:03 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=6415 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:38:03 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=6415 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:38:03 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=6415 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:38:03 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=6415 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:38:08 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:38:08 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:38:08 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:38:08 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:38:08 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:38:08 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:38:08 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:38:08 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:38:08 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:38:08 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:38:08 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 03:38:08 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 03:38:08 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 03:38:08 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:38:08 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:38:08 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:38:08 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 03:38:08 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:38:08 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 03:38:08 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 03:38:08 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 03:38:08 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:38:08 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:38:08 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:38:08 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 03:38:08 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:38:08 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 03:38:08 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 03:38:08 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 03:38:08 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:38:08 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:38:08 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:38:08 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 03:38:08 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:38:08 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 03:38:08 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 03:38:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 03:38:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 03:38:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 03:38:08 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 03:38:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 03:38:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 03:38:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 03:38:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:38:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 03:38:08 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 03:38:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:38:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:38:08 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 03:38:08 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 03:38:08 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 03:38:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:38:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:38:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:38:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 03:38:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:38:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:38:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:38:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:38:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:38:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:38:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:38:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:38:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:38:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:38:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:38:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:38:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:38:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:38:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:38:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:38:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:38:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:38:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:38:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:38:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:38:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:38:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:38:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:38:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:38:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:38:08 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 03:38:09 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 03:38:09 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 03:38:09 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 03:38:09 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 03:38:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:38:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:38:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:38:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:38:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:38:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:38:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:38:09 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:38:09 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:38:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD HANDOVER
2025-04-27 03:38:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:38:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:38:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:38:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:38:09 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 03:38:09 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:38:09 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:38:09 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:38:09 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:38:10 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 03:38:10 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 03:38:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:38:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:38:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:38:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:38:11 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 03:38:11 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 03:38:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:38:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:38:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:38:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:38:12 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 03:38:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:38:12 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 03:38:12 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:38:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:38:12 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:38:12 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:38:12 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 03:38:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:38:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:38:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:38:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:38:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:38:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:38:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:38:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:38:13 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:38:13 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:38:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD HANDOVER
2025-04-27 03:38:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:38:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:38:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:38:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:38:13 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 03:38:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:38:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:38:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:38:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:38:13 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 03:38:14 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 03:38:14 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 03:38:15 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 03:38:15 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 03:38:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:38:16 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 03:38:16 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 03:38:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:38:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:38:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:38:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:38:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:38:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:38:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:38:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:38:16 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:38:16 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:38:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD HANDOVER
2025-04-27 03:38:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:38:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:38:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:38:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:38:17 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 03:38:17 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 03:38:18 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 03:38:18 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 03:38:19 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 03:38:19 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-27 03:38:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:38:20 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-27 03:38:20 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-27 03:38:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:38:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:38:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:38:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:38:20 [WARNING] transceiver.py:250 (MS@172.18.127.22:6700) RX TRXD message (fn=2600 tn=5 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:38:20 [WARNING] transceiver.py:250 (MS@172.18.127.22:6700) RX TRXD message (fn=2600 tn=6 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:38:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:38:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:38:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:38:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:38:20 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:38:20 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:38:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD HANDOVER
2025-04-27 03:38:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:38:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:38:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:38:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:38:21 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-27 03:38:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:38:21 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-27 03:38:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:38:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:38:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:38:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:38:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:38:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:38:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:38:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:38:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:38:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:38:21 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:38:21 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:38:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD HANDOVER
2025-04-27 03:38:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:38:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:38:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:38:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:38:21 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-27 03:38:22 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-27 03:38:22 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-27 03:38:23 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-27 03:38:23 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-27 03:38:24 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-27 03:38:24 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-27 03:38:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:38:25 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-27 03:38:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:38:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:38:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:38:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:38:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:38:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:38:25 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:38:25 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:38:25 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:38:25 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:38:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD HANDOVER
2025-04-27 03:38:25 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:38:25 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:38:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:38:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:38:25 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-27 03:38:26 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-27 03:38:26 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-27 03:38:27 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2025-04-27 03:38:27 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2025-04-27 03:38:28 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2025-04-27 03:38:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:38:28 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2025-04-27 03:38:29 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2025-04-27 03:38:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:38:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:38:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:38:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:38:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:38:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:38:29 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:38:29 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:38:29 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:38:29 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:38:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD HANDOVER
2025-04-27 03:38:29 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:38:29 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:38:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:38:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:38:29 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2025-04-27 03:38:30 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2025-04-27 03:38:30 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2025-04-27 03:38:30 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2025-04-27 03:38:31 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2025-04-27 03:38:31 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2025-04-27 03:38:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:38:32 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2025-04-27 03:38:32 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2025-04-27 03:38:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:38:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:38:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:38:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:38:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:38:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:38:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:38:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:38:33 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:38:33 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:38:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD HANDOVER
2025-04-27 03:38:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:38:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:38:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:38:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:38:33 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2025-04-27 03:38:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:38:33 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2025-04-27 03:38:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:38:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:38:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:38:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:38:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:38:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:38:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:38:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:38:34 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:38:34 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:38:34 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:38:34 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:38:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD HANDOVER
2025-04-27 03:38:34 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:38:34 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:38:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:38:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:38:34 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2025-04-27 03:38:34 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2025-04-27 03:38:35 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2025-04-27 03:38:35 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2025-04-27 03:38:36 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2025-04-27 03:38:36 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2025-04-27 03:38:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:38:37 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2025-04-27 03:38:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:38:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:38:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:38:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:38:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:38:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:38:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:38:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:38:37 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:38:37 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:38:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD HANDOVER
2025-04-27 03:38:37 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2025-04-27 03:38:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:38:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:38:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:38:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:38:38 [DEBUG] clck_gen.py:102 IND CLOCK 6324
2025-04-27 03:38:38 [DEBUG] clck_gen.py:102 IND CLOCK 6426
2025-04-27 03:38:39 [DEBUG] clck_gen.py:102 IND CLOCK 6528
2025-04-27 03:38:39 [DEBUG] clck_gen.py:102 IND CLOCK 6630
2025-04-27 03:38:39 [DEBUG] clck_gen.py:102 IND CLOCK 6732
2025-04-27 03:38:40 [DEBUG] clck_gen.py:102 IND CLOCK 6834
2025-04-27 03:38:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:38:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:38:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:38:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:38:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:38:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:38:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:38:40 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:38:40 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:38:40 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:38:40 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:38:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD HANDOVER
2025-04-27 03:38:40 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:38:40 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:38:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:38:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:38:40 [DEBUG] clck_gen.py:102 IND CLOCK 6936
2025-04-27 03:38:41 [DEBUG] clck_gen.py:102 IND CLOCK 7038
2025-04-27 03:38:41 [DEBUG] clck_gen.py:102 IND CLOCK 7140
2025-04-27 03:38:42 [DEBUG] clck_gen.py:102 IND CLOCK 7242
2025-04-27 03:38:42 [DEBUG] clck_gen.py:102 IND CLOCK 7344
2025-04-27 03:38:43 [DEBUG] clck_gen.py:102 IND CLOCK 7446
2025-04-27 03:38:43 [DEBUG] clck_gen.py:102 IND CLOCK 7548
2025-04-27 03:38:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:38:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:38:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:38:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:38:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:38:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:38:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:38:44 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:38:44 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:38:44 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:38:44 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:38:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD HANDOVER
2025-04-27 03:38:44 [DEBUG] clck_gen.py:102 IND CLOCK 7650
2025-04-27 03:38:44 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:38:44 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:38:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:38:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:38:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:38:44 [DEBUG] clck_gen.py:102 IND CLOCK 7752
2025-04-27 03:38:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:38:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:38:45 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:38:45 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:38:45 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:38:45 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:38:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:38:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:38:45 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:38:45 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:38:45 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:38:45 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:38:45 [DEBUG] clck_gen.py:102 IND CLOCK 7854
2025-04-27 03:38:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD HANDOVER
2025-04-27 03:38:45 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:38:45 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:38:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:38:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:38:45 [DEBUG] clck_gen.py:102 IND CLOCK 7956
2025-04-27 03:38:46 [DEBUG] clck_gen.py:102 IND CLOCK 8058
2025-04-27 03:38:46 [DEBUG] clck_gen.py:102 IND CLOCK 8160
2025-04-27 03:38:47 [DEBUG] clck_gen.py:102 IND CLOCK 8262
2025-04-27 03:38:47 [DEBUG] clck_gen.py:102 IND CLOCK 8364
2025-04-27 03:38:48 [DEBUG] clck_gen.py:102 IND CLOCK 8466
2025-04-27 03:38:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:38:48 [DEBUG] clck_gen.py:102 IND CLOCK 8568
2025-04-27 03:38:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:38:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:38:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:38:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:38:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:38:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:38:48 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:38:48 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:38:48 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:38:48 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:38:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD HANDOVER
2025-04-27 03:38:48 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:38:48 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:38:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:38:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:38:49 [DEBUG] clck_gen.py:102 IND CLOCK 8670
2025-04-27 03:38:49 [DEBUG] clck_gen.py:102 IND CLOCK 8772
2025-04-27 03:38:49 [DEBUG] clck_gen.py:102 IND CLOCK 8874
2025-04-27 03:38:50 [DEBUG] clck_gen.py:102 IND CLOCK 8976
2025-04-27 03:38:50 [DEBUG] clck_gen.py:102 IND CLOCK 9078
2025-04-27 03:38:51 [DEBUG] clck_gen.py:102 IND CLOCK 9180
2025-04-27 03:38:51 [DEBUG] clck_gen.py:102 IND CLOCK 9282
2025-04-27 03:38:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:38:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:38:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:38:52 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:38:52 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:38:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:38:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:38:52 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:38:52 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:38:52 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:38:52 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:38:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD HANDOVER
2025-04-27 03:38:52 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:38:52 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:38:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:38:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:38:52 [DEBUG] clck_gen.py:102 IND CLOCK 9384
2025-04-27 03:38:52 [DEBUG] clck_gen.py:102 IND CLOCK 9486
2025-04-27 03:38:53 [DEBUG] clck_gen.py:102 IND CLOCK 9588
2025-04-27 03:38:53 [DEBUG] clck_gen.py:102 IND CLOCK 9690
2025-04-27 03:38:54 [DEBUG] clck_gen.py:102 IND CLOCK 9792
2025-04-27 03:38:54 [DEBUG] clck_gen.py:102 IND CLOCK 9894
2025-04-27 03:38:55 [DEBUG] clck_gen.py:102 IND CLOCK 9996
2025-04-27 03:38:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:38:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:38:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:38:55 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:38:55 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:38:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:38:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:38:55 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:38:55 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:38:55 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:38:55 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:38:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD HANDOVER
2025-04-27 03:38:55 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:38:55 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:38:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:38:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:38:55 [DEBUG] clck_gen.py:102 IND CLOCK 10098
2025-04-27 03:38:56 [DEBUG] clck_gen.py:102 IND CLOCK 10200
2025-04-27 03:38:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:38:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:38:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:38:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:38:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:38:56 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:38:56 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:38:56 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:38:56 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:38:56 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:38:56 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:38:56 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:38:56 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:38:56 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 03:38:56 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=10290 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:38:56 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:38:56 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:38:56 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=10290 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:38:56 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=10290 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:38:56 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=10290 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:38:56 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=10290 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:38:56 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=10290 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:38:56 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=10290 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:38:56 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=10290 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:39:01 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:39:01 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:39:01 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:39:01 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:39:01 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:39:01 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:39:01 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:39:01 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:39:01 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:39:01 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:39:01 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 03:39:01 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 03:39:01 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 03:39:01 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:39:01 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:39:01 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 03:39:01 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:39:01 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:39:01 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 03:39:01 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 03:39:01 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 03:39:01 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:39:01 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:39:01 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 03:39:01 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:39:01 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:39:01 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 03:39:01 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 03:39:01 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 03:39:01 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:39:01 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:39:01 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 03:39:01 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:39:01 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:39:01 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 03:39:01 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 03:39:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 03:39:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 03:39:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 03:39:01 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 03:39:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 03:39:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 03:39:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 03:39:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 03:39:01 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 03:39:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:39:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:39:01 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 03:39:01 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 03:39:01 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 03:39:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:39:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:39:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:39:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 03:39:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:39:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:39:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:39:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:39:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:39:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:39:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:39:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:39:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:39:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:39:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:39:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:39:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:39:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:39:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:39:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:39:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:39:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:39:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:39:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:39:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:39:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:39:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:39:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:39:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:39:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:39:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:39:01 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 03:39:02 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 03:39:02 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 03:39:02 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 03:39:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:39:02 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 03:39:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:39:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:39:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:39:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:39:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:39:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:39:02 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:39:02 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:39:02 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 03:39:02 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:39:02 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:39:02 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:39:02 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:39:02 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 03:39:03 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 03:39:03 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:39:03 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:39:03 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:39:03 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:39:03 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 03:39:04 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 03:39:04 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:39:04 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:39:04 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:39:04 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:39:04 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 03:39:05 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 03:39:05 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:39:05 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:39:05 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:39:05 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:39:05 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 03:39:06 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 03:39:06 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:39:06 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:39:06 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:39:06 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:39:06 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 03:39:07 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 03:39:07 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 03:39:08 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 03:39:08 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 03:39:09 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 03:39:09 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 03:39:10 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 03:39:10 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 03:39:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:39:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:39:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:39:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:39:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:39:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:39:10 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:39:10 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:39:10 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:39:10 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:39:10 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:39:10 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:39:10 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 03:39:10 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2008 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:39:10 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2008 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:39:10 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2008 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:39:10 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2009 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:39:10 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2009 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:39:10 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2009 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:39:10 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2009 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:39:10 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2009 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:39:10 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2009 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:39:10 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2009 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:39:10 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2009 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:39:15 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:39:15 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:39:15 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:39:15 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:39:15 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:39:15 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:39:15 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:39:15 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:39:15 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:39:15 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:39:15 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 03:39:15 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 03:39:15 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 03:39:15 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:39:15 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:39:15 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:39:15 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 03:39:15 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:39:15 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 03:39:15 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 03:39:15 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 03:39:15 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:39:15 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:39:15 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:39:15 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 03:39:15 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:39:15 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 03:39:15 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 03:39:15 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 03:39:15 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:39:15 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:39:15 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:39:15 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 03:39:15 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:39:15 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 03:39:15 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 03:39:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 03:39:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 03:39:15 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 03:39:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 03:39:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 03:39:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 03:39:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 03:39:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 03:39:15 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 03:39:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:39:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:39:15 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 03:39:15 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 03:39:15 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 03:39:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:39:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:39:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:39:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 03:39:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:39:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:39:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:39:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:39:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:39:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:39:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:39:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:39:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:39:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:39:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:39:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:39:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:39:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:39:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:39:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:39:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:39:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:39:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:39:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:39:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:39:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:39:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:39:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:39:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:39:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:39:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:39:15 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 03:39:16 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 03:39:16 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 03:39:16 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 03:39:16 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 03:39:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:39:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:39:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:39:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:39:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:39:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:39:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:39:16 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:39:16 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:39:16 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 03:39:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:39:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:39:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:39:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:39:17 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 03:39:17 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 03:39:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:39:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:39:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:39:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:39:18 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 03:39:18 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 03:39:18 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:39:18 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:39:18 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:39:18 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:39:19 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 03:39:19 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 03:39:19 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:39:19 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:39:19 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:39:19 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:39:20 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 03:39:20 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 03:39:20 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:39:20 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:39:20 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:39:20 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:39:21 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 03:39:21 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 03:39:22 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 03:39:22 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 03:39:23 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 03:39:23 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 03:39:23 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 03:39:24 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 03:39:24 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 03:39:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:39:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:39:25 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:39:25 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:39:25 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:39:25 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:39:25 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:39:25 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:39:25 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:39:25 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:39:25 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:39:25 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 03:39:25 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2008 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:39:25 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:39:25 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2008 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:39:25 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2008 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:39:25 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2008 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:39:25 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2008 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:39:25 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2008 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:39:25 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2009 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:39:25 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2009 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:39:25 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2009 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:39:25 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2009 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:39:25 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2009 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:39:25 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2009 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:39:25 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2009 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:39:25 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2009 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:39:25 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2010 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:39:25 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2010 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:39:25 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2010 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:39:25 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2010 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:39:25 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2010 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:39:25 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2010 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:39:25 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2010 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:39:25 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2010 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:39:30 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:39:30 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:39:30 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:39:30 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:39:30 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:39:30 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:39:30 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:39:30 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:39:30 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:39:30 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:39:30 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 03:39:30 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 03:39:30 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 03:39:30 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:39:30 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:39:30 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:39:30 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 03:39:30 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:39:30 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 03:39:30 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 03:39:30 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 03:39:30 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:39:30 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:39:30 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:39:30 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 03:39:30 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:39:30 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 03:39:30 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 03:39:30 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 03:39:30 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:39:30 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:39:30 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:39:30 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 03:39:30 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:39:30 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 03:39:30 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 03:39:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 03:39:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 03:39:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 03:39:30 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 03:39:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 03:39:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 03:39:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 03:39:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:39:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 03:39:30 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 03:39:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:39:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:39:30 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 03:39:30 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 03:39:30 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 03:39:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:39:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:39:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:39:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 03:39:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:39:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:39:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:39:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:39:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:39:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:39:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:39:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:39:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:39:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:39:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:39:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:39:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:39:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:39:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:39:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:39:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:39:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:39:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:39:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:39:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:39:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:39:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:39:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:39:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:39:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:39:30 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 03:39:30 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 03:39:30 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 03:39:30 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 03:39:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:39:30 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 03:39:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:39:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:39:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:39:31 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 03:39:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:39:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:39:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:39:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:39:31 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 03:39:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:39:31 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:39:31 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:39:31 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:39:31 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:39:32 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 03:39:32 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:39:32 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:39:32 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:39:32 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:39:32 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 03:39:33 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 03:39:33 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:39:33 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:39:33 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:39:33 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:39:33 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 03:39:34 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 03:39:34 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:39:34 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:39:34 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:39:34 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:39:34 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 03:39:35 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 03:39:35 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:39:35 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:39:35 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:39:35 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:39:35 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 03:39:35 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 03:39:36 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 03:39:36 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 03:39:37 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 03:39:37 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 03:39:38 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 03:39:38 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 03:39:39 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 03:39:39 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 03:39:40 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 03:39:40 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 03:39:41 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-27 03:39:41 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-27 03:39:42 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-27 03:39:42 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-27 03:39:43 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-27 03:39:43 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-27 03:39:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:39:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:39:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:39:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:39:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:39:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:39:43 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:39:43 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:39:43 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:39:43 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:39:43 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 03:39:43 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:39:43 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:39:43 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2883 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:39:43 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2883 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:39:43 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2883 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:39:43 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2883 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:39:43 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2883 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:39:43 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2883 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:39:43 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2883 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:39:48 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:39:48 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:39:48 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:39:48 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:39:48 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:39:48 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:39:48 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:39:48 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:39:48 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:39:48 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:39:48 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 03:39:48 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 03:39:48 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 03:39:48 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:39:48 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:39:48 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:39:48 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 03:39:48 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:39:48 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 03:39:48 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 03:39:48 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 03:39:48 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:39:48 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:39:48 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:39:48 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 03:39:48 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:39:48 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 03:39:48 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 03:39:48 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 03:39:48 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:39:48 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:39:48 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:39:48 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 03:39:48 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:39:48 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 03:39:48 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 03:39:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 03:39:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 03:39:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 03:39:48 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 03:39:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 03:39:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 03:39:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 03:39:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 03:39:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:39:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:39:48 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 03:39:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:39:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:39:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:39:48 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 03:39:48 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 03:39:48 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 03:39:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:39:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:39:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:39:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 03:39:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:39:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:39:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:39:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:39:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:39:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:39:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:39:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:39:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:39:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:39:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:39:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:39:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:39:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:39:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:39:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:39:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:39:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:39:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:39:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:39:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:39:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:39:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:39:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:39:48 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 03:39:49 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 03:39:49 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 03:39:49 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 03:39:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:39:49 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 03:39:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:39:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:39:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:39:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:39:49 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:39:49 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:39:49 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:39:49 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:39:49 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 03:39:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:39:49 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:39:49 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:39:49 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:39:50 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 03:39:50 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 03:39:50 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 03:39:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:39:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:39:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:39:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:39:50 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 03:39:51 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 03:39:51 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 03:39:51 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 03:39:51 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:39:51 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:39:51 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:39:51 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:39:51 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 03:39:52 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 03:39:52 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:39:52 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:39:52 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:39:52 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:39:52 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 03:39:53 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 03:39:53 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 03:39:53 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:39:53 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:39:53 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:39:53 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:39:53 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 03:39:53 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 03:39:54 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 03:39:54 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 03:39:54 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 03:39:54 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 03:39:55 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 03:39:55 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 03:39:56 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 03:39:56 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 03:39:56 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 03:39:57 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 03:39:57 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 03:39:58 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 03:39:58 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 03:39:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:39:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:39:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:39:58 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:39:58 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:39:58 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:39:58 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:39:58 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:39:58 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:39:58 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:39:58 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 03:39:58 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:39:58 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:40:03 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:40:03 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:40:03 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:40:03 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:40:03 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:40:03 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:40:03 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:40:03 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:40:03 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:40:03 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:40:03 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 03:40:03 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 03:40:03 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 03:40:03 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:40:03 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:40:03 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:40:03 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 03:40:03 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:40:03 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 03:40:03 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 03:40:03 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 03:40:03 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:40:03 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:40:03 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:40:03 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 03:40:03 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:40:03 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 03:40:03 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 03:40:03 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 03:40:03 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:40:03 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:40:03 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:40:03 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 03:40:03 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:40:03 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 03:40:03 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 03:40:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 03:40:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 03:40:03 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 03:40:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 03:40:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 03:40:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 03:40:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 03:40:03 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 03:40:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:40:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 03:40:03 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 03:40:03 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 03:40:03 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 03:40:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:40:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:40:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:40:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 03:40:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:40:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:40:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:40:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:40:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:40:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:40:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:40:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:40:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:40:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:40:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:40:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:40:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:40:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:40:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:40:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:40:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:40:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:40:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:40:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:40:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:40:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:40:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:40:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:40:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:40:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:40:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:40:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:40:03 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 03:40:04 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 03:40:04 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 03:40:04 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 03:40:04 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 03:40:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:40:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:40:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:40:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:40:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:40:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:40:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:40:04 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:40:04 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:40:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD HANDOVER
2025-04-27 03:40:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:40:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:40:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:40:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:40:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:40:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:40:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:40:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:40:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:40:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:40:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:40:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:40:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:40:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:40:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:40:04 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:40:04 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:40:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD HANDOVER
2025-04-27 03:40:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:40:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:40:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:40:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:40:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:40:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:40:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:40:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:40:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:40:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:40:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:40:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:40:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:40:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:40:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:40:04 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:40:04 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:40:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD HANDOVER
2025-04-27 03:40:04 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 03:40:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:40:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:40:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:40:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:40:04 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:40:04 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:40:04 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:40:04 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:40:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:40:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:40:05 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD HANDOVER
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:40:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:40:05 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:40:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:40:05 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD HANDOVER
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:40:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:40:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:40:05 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD HANDOVER
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:40:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:40:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:40:05 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD HANDOVER
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:40:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:40:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:40:05 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD HANDOVER
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:40:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:40:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:40:05 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD HANDOVER
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:40:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:40:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:40:05 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD HANDOVER
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:40:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:40:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:40:05 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD HANDOVER
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:40:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:40:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:40:05 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD HANDOVER
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:40:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:40:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:40:05 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD HANDOVER
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:40:05 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:40:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:40:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:40:05 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD HANDOVER
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:40:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:40:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:40:05 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD HANDOVER
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:40:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:40:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:40:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:40:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:40:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:40:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:40:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:40:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:40:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:40:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:40:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:40:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:40:06 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:40:06 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:40:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD HANDOVER
2025-04-27 03:40:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:40:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:40:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:40:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:40:06 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 03:40:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:40:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:40:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:40:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:40:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:40:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:40:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:40:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:40:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:40:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:40:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:40:06 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:40:06 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:40:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD HANDOVER
2025-04-27 03:40:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:40:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:40:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:40:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:40:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:40:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:40:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:40:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:40:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:40:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:40:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:40:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:40:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:40:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:40:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:40:06 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:40:06 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:40:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD HANDOVER
2025-04-27 03:40:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:40:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:40:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:40:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:40:06 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 03:40:06 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:40:06 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:40:06 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:40:06 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:40:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:40:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:40:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:40:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:40:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:40:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:40:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:40:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:40:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:40:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:40:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:40:06 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:40:06 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:40:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD HANDOVER
2025-04-27 03:40:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:40:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:40:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:40:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:40:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:40:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:40:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:40:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:40:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:40:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:40:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:40:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:40:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:40:07 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:40:07 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:40:07 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:40:07 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:40:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD HANDOVER
2025-04-27 03:40:07 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 03:40:07 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:40:07 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:40:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:40:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:40:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:40:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:40:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:40:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:40:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:40:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:40:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:40:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:40:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:40:07 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:40:07 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:40:07 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:40:07 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:40:07 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:40:07 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 03:40:07 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:40:12 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:40:12 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:40:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:40:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:40:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:40:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:40:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:40:12 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:40:12 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:40:12 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:40:12 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 03:40:12 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 03:40:12 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 03:40:12 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:40:12 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:40:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:40:12 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 03:40:12 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:40:12 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 03:40:12 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 03:40:12 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 03:40:12 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:40:12 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:40:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:40:12 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 03:40:12 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:40:12 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 03:40:12 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 03:40:12 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 03:40:12 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:40:12 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:40:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:40:12 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 03:40:12 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:40:12 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 03:40:12 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 03:40:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 03:40:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 03:40:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 03:40:12 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 03:40:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 03:40:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 03:40:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 03:40:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:40:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 03:40:12 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 03:40:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:40:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:40:12 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 03:40:12 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 03:40:12 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 03:40:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:40:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:40:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:40:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 03:40:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:40:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:40:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:40:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:40:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:40:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:40:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:40:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:40:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:40:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:40:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:40:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:40:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:40:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:40:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:40:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:40:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:40:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:40:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:40:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:40:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:40:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:40:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:40:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:40:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:40:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:40:12 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 03:40:12 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 03:40:12 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 03:40:12 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 03:40:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:40:12 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 03:40:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:40:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:40:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:40:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:40:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:40:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:40:12 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:40:12 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:40:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD HANDOVER
2025-04-27 03:40:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:40:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:40:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:40:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:40:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:40:13 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 03:40:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:40:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:40:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:40:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:40:13 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 03:40:14 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 03:40:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:40:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:40:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:40:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:40:14 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 03:40:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:40:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:40:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:40:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:40:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:40:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:40:15 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:40:15 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:40:15 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:40:15 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:40:15 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:40:15 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:40:15 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 03:40:15 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=572 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:40:15 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=572 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:40:15 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=572 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:40:15 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=572 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:40:15 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=572 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:40:15 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=572 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:40:20 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:40:20 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:40:20 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:40:20 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:40:20 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:40:20 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:40:20 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:40:20 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:40:20 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:40:20 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:40:20 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 03:40:20 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 03:40:20 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 03:40:20 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:40:20 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:40:20 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:40:20 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 03:40:20 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:40:20 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 03:40:20 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 03:40:20 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 03:40:20 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:40:20 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:40:20 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:40:20 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 03:40:20 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:40:20 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 03:40:20 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 03:40:20 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 03:40:20 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:40:20 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:40:20 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:40:20 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 03:40:20 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:40:20 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 03:40:20 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 03:40:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 03:40:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 03:40:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 03:40:20 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 03:40:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 03:40:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 03:40:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 03:40:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:40:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 03:40:20 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 03:40:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:40:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:40:20 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 03:40:20 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 03:40:20 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 03:40:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:40:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:40:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:40:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 03:40:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:40:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:40:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:40:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:40:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:40:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:40:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:40:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:40:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:40:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:40:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:40:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:40:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:40:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:40:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:40:20 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:40:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:40:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:40:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:40:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:40:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:40:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:40:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:40:20 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:40:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:40:20 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:40:20 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:40:20 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 03:40:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:40:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:40:25 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:40:25 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:40:25 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:40:25 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:40:25 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:40:25 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:40:25 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:40:25 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:40:25 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:40:25 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:40:25 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 03:40:25 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 03:40:25 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 03:40:25 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:40:25 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:40:25 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:40:25 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 03:40:25 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:40:25 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 03:40:25 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 03:40:25 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 03:40:25 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:40:25 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:40:25 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:40:25 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 03:40:25 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:40:25 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 03:40:25 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 03:40:25 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 03:40:25 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:40:25 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:40:25 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:40:25 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 03:40:25 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:40:25 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 03:40:25 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 03:40:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 03:40:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 03:40:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 03:40:25 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 03:40:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 03:40:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 03:40:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 03:40:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 03:40:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:40:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:40:25 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 03:40:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:40:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:40:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:40:25 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 03:40:25 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 03:40:25 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 03:40:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:40:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:40:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:40:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 03:40:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:40:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:40:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:40:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:40:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:40:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:40:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:40:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:40:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:40:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:40:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:40:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:40:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:40:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:40:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:40:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:40:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:40:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:40:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:40:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:40:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:40:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:40:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:40:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:40:25 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 03:40:25 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 03:40:25 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 03:40:25 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 03:40:25 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 03:40:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:40:26 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 03:40:26 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:40:26 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:40:26 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:40:26 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:40:26 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 03:40:27 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 03:40:27 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:40:27 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:40:27 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:40:27 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:40:27 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 03:40:28 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 03:40:28 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:40:28 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:40:28 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:40:28 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:40:28 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 03:40:28 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 03:40:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:40:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:40:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:40:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:40:29 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 03:40:29 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 03:40:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:40:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:40:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:40:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:40:30 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 03:40:30 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 03:40:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:40:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:40:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:40:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:40:31 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:40:31 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:40:31 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:40:31 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:40:31 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 03:40:31 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:40:31 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:40:36 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:40:36 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:40:36 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:40:36 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:40:36 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:40:36 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:40:36 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:40:36 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:40:36 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:40:36 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:40:36 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 03:40:36 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 03:40:36 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 03:40:36 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:40:36 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:40:36 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:40:36 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 03:40:36 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:40:36 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 03:40:36 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 03:40:36 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 03:40:36 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:40:36 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:40:36 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:40:36 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 03:40:36 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:40:36 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 03:40:36 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 03:40:36 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 03:40:36 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:40:36 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:40:36 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:40:36 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 03:40:36 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:40:36 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 03:40:36 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 03:40:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 03:40:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 03:40:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 03:40:36 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 03:40:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 03:40:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 03:40:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 03:40:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 03:40:36 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 03:40:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:40:36 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 03:40:36 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 03:40:36 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 03:40:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:40:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:40:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:40:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 03:40:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:40:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:40:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:40:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:40:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:40:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:40:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:40:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:40:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:40:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:40:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:40:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:40:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:40:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:40:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:40:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:40:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:40:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:40:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:40:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:40:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:40:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:40:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:40:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:40:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:40:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:40:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:40:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:40:36 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 03:40:36 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 03:40:36 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 03:40:36 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 03:40:36 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 03:40:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:40:37 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 03:40:37 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:40:37 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:40:37 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:40:37 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:40:37 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 03:40:38 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 03:40:38 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:40:38 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:40:38 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:40:38 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:40:38 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 03:40:39 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 03:40:39 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:40:39 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:40:39 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:40:39 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:40:39 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 03:40:40 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 03:40:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:40:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:40:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:40:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:40:40 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 03:40:40 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 03:40:41 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:40:41 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:40:41 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:40:41 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:40:41 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 03:40:41 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:40:41 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:40:41 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:40:41 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:40:41 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:40:41 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:40:41 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:40:41 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 03:40:41 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1184 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:40:41 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:40:41 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:40:41 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:40:41 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1184 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:40:41 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1184 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:40:41 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1184 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:40:41 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1184 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:40:41 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1184 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:40:46 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:40:46 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:40:46 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:40:46 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:40:46 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:40:46 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:40:46 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:40:46 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:40:46 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:40:46 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:40:46 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 03:40:46 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 03:40:46 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 03:40:46 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:40:46 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:40:46 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:40:46 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 03:40:46 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:40:46 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 03:40:46 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 03:40:46 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 03:40:46 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:40:46 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:40:46 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:40:46 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 03:40:46 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:40:46 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 03:40:46 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 03:40:46 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 03:40:46 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:40:46 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:40:46 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:40:46 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 03:40:46 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:40:46 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 03:40:46 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 03:40:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 03:40:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 03:40:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 03:40:46 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 03:40:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 03:40:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 03:40:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 03:40:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 03:40:46 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 03:40:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:40:46 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 03:40:46 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 03:40:46 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 03:40:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:40:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:40:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:40:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 03:40:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:40:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:40:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:40:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:40:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:40:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:40:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:40:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:40:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:40:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:40:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:40:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:40:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:40:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:40:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:40:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:40:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:40:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:40:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:40:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:40:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:40:46 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:40:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:40:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:40:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:40:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:40:46 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:40:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:40:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:40:46 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:40:46 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:40:46 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 03:40:46 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:40:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:40:51 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:40:51 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:40:51 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:40:51 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:40:51 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:40:51 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:40:51 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:40:51 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:40:51 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:40:51 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:40:51 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 03:40:51 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 03:40:51 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 03:40:51 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:40:51 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:40:51 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:40:51 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 03:40:51 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:40:51 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 03:40:51 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 03:40:51 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 03:40:51 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:40:51 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:40:51 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:40:51 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 03:40:51 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:40:51 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 03:40:51 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 03:40:51 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 03:40:51 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:40:51 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:40:51 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:40:51 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 03:40:51 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:40:51 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 03:40:51 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 03:40:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 03:40:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 03:40:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 03:40:51 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 03:40:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 03:40:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 03:40:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 03:40:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:40:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 03:40:51 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 03:40:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:40:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:40:51 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 03:40:51 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 03:40:51 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 03:40:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:40:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:40:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:40:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 03:40:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:40:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:40:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:40:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:40:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:40:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:40:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:40:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:40:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:40:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:40:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:40:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:40:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:40:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:40:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:40:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:40:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:40:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:40:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:40:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:40:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:40:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:40:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:40:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:40:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:40:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:40:51 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 03:40:52 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 03:40:52 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 03:40:52 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 03:40:52 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 03:40:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:40:52 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:40:52 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:40:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:40:52 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 03:40:52 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:40:52 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:40:52 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:40:52 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:40:53 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 03:40:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:40:53 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:40:53 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:40:53 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:40:53 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:40:53 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 03:40:53 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:40:53 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:40:53 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:40:53 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:40:54 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 03:40:54 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 03:40:54 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:40:54 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:40:54 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:40:54 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:40:55 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 03:40:55 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 03:40:55 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:40:55 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:40:55 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:40:55 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:40:56 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 03:40:56 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 03:40:56 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:40:56 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:40:56 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:40:56 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:40:57 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 03:40:57 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 03:40:58 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 03:40:58 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 03:40:58 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 03:40:59 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 03:40:59 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 03:41:00 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 03:41:00 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 03:41:01 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 03:41:01 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 03:41:02 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 03:41:02 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-27 03:41:03 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-27 03:41:03 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-27 03:41:04 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-27 03:41:04 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-27 03:41:05 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-27 03:41:05 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-27 03:41:06 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-27 03:41:06 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-27 03:41:06 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-27 03:41:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:41:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:41:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:41:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:41:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:41:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:41:07 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:41:07 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:41:07 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:41:07 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:41:07 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:41:07 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:41:07 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 03:41:07 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3315 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:41:07 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3315 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:41:07 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3315 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:41:07 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3315 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:41:07 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3315 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:41:07 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3315 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:41:07 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3315 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:41:12 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:41:12 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:41:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:41:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:41:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:41:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:41:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:41:12 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:41:12 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:41:12 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:41:12 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 03:41:12 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 03:41:12 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 03:41:12 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:41:12 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:41:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:41:12 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 03:41:12 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:41:12 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 03:41:12 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 03:41:12 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 03:41:12 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:41:12 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:41:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:41:12 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 03:41:12 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:41:12 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 03:41:12 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 03:41:12 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 03:41:12 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:41:12 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:41:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:41:12 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 03:41:12 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:41:12 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 03:41:12 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 03:41:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 03:41:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 03:41:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 03:41:12 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 03:41:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 03:41:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 03:41:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 03:41:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:41:12 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 03:41:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:41:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 03:41:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:41:12 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 03:41:12 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 03:41:12 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 03:41:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:41:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:41:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:41:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 03:41:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:41:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:41:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:41:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:41:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:41:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:41:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:41:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:41:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:41:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:41:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:41:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:41:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:41:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:41:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:41:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:41:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:41:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:41:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:41:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:41:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:41:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:41:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:41:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:41:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:41:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:41:12 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 03:41:12 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 03:41:12 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 03:41:12 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 03:41:12 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 03:41:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:41:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:41:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:41:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:41:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:41:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:41:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:41:12 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:41:12 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:41:12 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 03:41:12 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 03:41:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:41:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:41:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:41:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:41:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:41:13 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 03:41:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:41:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:41:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:41:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:41:13 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 03:41:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:41:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:41:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:41:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:41:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:41:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:41:13 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:41:13 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:41:13 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:41:13 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:41:13 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:41:13 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:41:13 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 03:41:13 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=314 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:41:13 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=314 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:41:13 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=314 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:41:13 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=314 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:41:13 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=314 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:41:13 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=314 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:41:18 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:41:18 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:41:18 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:41:18 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:41:18 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:41:18 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:41:18 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:41:18 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:41:18 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:41:18 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:41:18 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 03:41:18 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 03:41:18 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 03:41:18 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:41:18 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:41:18 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:41:18 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 03:41:18 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:41:18 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 03:41:18 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 03:41:18 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 03:41:18 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:41:18 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:41:18 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:41:18 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 03:41:18 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:41:18 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 03:41:18 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 03:41:18 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 03:41:18 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:41:18 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:41:18 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:41:18 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 03:41:18 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:41:18 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 03:41:18 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 03:41:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 03:41:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 03:41:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 03:41:18 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 03:41:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 03:41:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 03:41:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 03:41:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:41:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 03:41:18 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 03:41:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:41:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:41:18 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 03:41:18 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 03:41:18 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 03:41:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:41:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:41:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:41:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 03:41:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:41:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:41:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:41:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:41:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:41:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:41:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:41:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:41:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:41:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:41:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:41:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:41:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:41:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:41:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:41:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:41:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:41:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:41:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:41:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:41:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:41:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:41:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:41:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:41:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:41:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:41:18 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 03:41:19 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 03:41:19 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 03:41:19 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 03:41:19 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 03:41:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:41:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:41:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:41:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:41:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:41:19 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:41:19 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:41:19 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:41:19 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:41:19 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 03:41:19 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 03:41:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:41:19 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:41:19 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:41:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:41:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:41:19 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 03:41:19 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:41:19 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:41:19 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:41:19 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:41:20 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 03:41:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:41:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:41:20 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:41:20 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:41:20 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:41:20 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:41:20 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:41:20 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:41:20 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:41:20 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:41:20 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:41:20 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:41:20 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 03:41:25 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:41:25 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:41:25 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:41:25 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:41:25 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:41:25 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:41:25 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:41:25 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:41:25 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:41:25 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:41:25 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 03:41:25 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 03:41:25 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 03:41:25 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:41:25 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:41:25 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:41:25 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 03:41:25 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:41:25 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 03:41:25 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 03:41:25 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 03:41:25 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:41:25 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:41:25 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:41:25 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 03:41:25 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:41:25 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 03:41:25 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 03:41:25 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 03:41:25 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:41:25 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:41:25 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:41:25 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 03:41:25 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:41:25 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 03:41:25 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 03:41:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 03:41:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 03:41:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 03:41:25 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 03:41:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 03:41:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 03:41:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 03:41:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:41:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 03:41:25 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 03:41:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:41:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:41:25 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 03:41:25 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 03:41:25 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 03:41:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:41:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:41:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:41:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 03:41:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:41:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:41:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:41:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:41:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:41:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:41:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:41:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:41:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:41:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:41:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:41:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:41:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:41:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:41:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:41:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:41:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:41:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:41:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:41:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:41:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:41:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:41:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:41:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:41:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:41:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:41:25 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 03:41:25 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 03:41:25 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 03:41:25 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 03:41:25 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 03:41:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:41:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:41:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:41:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:41:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:41:25 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:41:25 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:41:25 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:41:25 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:41:25 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 03:41:25 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 03:41:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:41:25 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:41:25 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:41:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:41:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:41:26 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 03:41:26 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:41:26 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:41:26 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:41:26 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:41:26 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 03:41:27 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 03:41:27 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:41:27 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:41:27 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:41:27 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:41:27 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 03:41:28 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 03:41:28 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:41:28 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:41:28 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:41:28 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:41:28 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 03:41:29 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 03:41:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:41:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:41:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:41:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:41:29 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 03:41:29 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 03:41:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:41:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:41:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:41:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:41:30 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 03:41:30 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 03:41:31 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 03:41:31 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 03:41:32 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 03:41:32 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 03:41:33 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 03:41:33 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 03:41:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:41:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:41:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:41:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:41:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:41:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:41:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:41:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:41:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:41:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:41:33 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:41:33 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:41:33 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 03:41:33 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 03:41:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:41:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:41:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:41:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:41:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:41:34 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 03:41:34 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 03:41:35 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 03:41:35 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 03:41:36 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-27 03:41:36 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-27 03:41:37 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-27 03:41:37 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-27 03:41:38 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-27 03:41:38 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-27 03:41:39 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-27 03:41:39 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-27 03:41:39 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-27 03:41:40 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-27 03:41:40 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-27 03:41:41 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-27 03:41:41 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-27 03:41:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:41:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:41:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:41:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:41:41 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:41:41 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:41:41 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:41:41 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:41:41 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:41:41 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:41:41 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:41:41 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:41:41 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:41:41 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:41:41 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 03:41:41 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3583 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:41:41 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3583 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:41:41 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3583 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:41:41 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3583 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:41:41 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3583 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:41:41 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3583 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:41:41 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3584 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:41:41 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3584 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:41:41 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3584 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:41:41 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3584 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:41:41 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3584 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:41:41 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3584 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:41:41 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3584 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:41:41 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3584 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:41:41 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3585 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:41:41 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3585 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:41:41 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3585 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:41:41 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3585 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:41:41 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3585 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:41:41 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3585 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:41:41 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3585 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:41:41 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3585 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:41:46 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:41:46 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:41:46 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:41:46 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:41:46 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:41:46 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:41:46 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:41:46 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:41:46 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:41:46 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:41:46 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 03:41:46 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 03:41:46 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 03:41:46 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:41:46 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:41:46 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:41:46 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 03:41:46 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:41:46 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 03:41:46 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 03:41:46 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 03:41:46 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:41:46 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:41:46 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:41:46 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 03:41:46 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:41:46 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 03:41:46 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 03:41:46 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 03:41:46 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:41:46 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:41:46 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:41:46 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 03:41:46 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:41:46 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 03:41:47 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 03:41:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 03:41:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 03:41:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 03:41:47 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 03:41:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 03:41:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 03:41:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 03:41:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:41:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 03:41:47 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 03:41:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:41:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:41:47 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 03:41:47 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 03:41:47 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 03:41:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:41:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:41:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:41:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 03:41:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:41:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:41:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:41:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:41:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:41:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:41:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:41:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:41:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:41:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:41:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:41:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:41:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:41:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:41:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:41:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:41:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:41:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:41:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:41:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:41:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:41:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:41:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:41:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:41:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:41:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:41:47 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 03:41:47 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 03:41:47 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 03:41:47 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 03:41:47 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 03:41:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:41:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:41:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:41:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:41:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:41:47 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:41:47 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:41:47 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:41:47 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:41:47 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 03:41:47 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 03:41:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:41:47 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:41:47 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:41:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:41:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:41:47 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 03:41:48 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:41:48 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:41:48 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:41:48 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:41:48 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 03:41:48 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 03:41:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:41:49 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:41:49 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:41:49 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:41:49 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 03:41:49 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 03:41:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:41:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:41:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:41:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:41:50 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 03:41:50 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 03:41:51 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:41:51 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:41:51 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:41:51 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:41:51 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 03:41:51 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 03:41:52 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:41:52 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:41:52 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:41:52 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:41:52 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 03:41:52 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 03:41:53 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 03:41:53 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 03:41:54 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 03:41:54 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 03:41:55 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 03:41:55 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 03:41:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:41:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:41:55 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:41:55 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:41:55 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:41:55 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:41:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:41:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:41:55 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:41:55 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:41:55 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:41:55 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:41:55 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 03:41:55 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 03:41:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:41:55 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:41:55 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:41:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:41:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:41:56 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 03:41:56 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 03:41:56 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 03:41:57 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 03:41:57 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-27 03:41:58 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-27 03:41:58 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-27 03:41:59 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-27 03:41:59 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-27 03:42:00 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-27 03:42:00 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-27 03:42:01 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-27 03:42:01 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-27 03:42:02 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-27 03:42:02 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-27 03:42:03 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-27 03:42:03 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-27 03:42:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:42:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:42:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:42:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:42:03 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:42:03 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:42:03 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:42:03 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:42:03 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:42:03 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:42:03 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:42:03 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:42:03 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 03:42:03 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3577 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:42:03 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:42:03 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:42:03 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3577 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:42:03 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3577 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:42:03 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3578 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:42:03 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3578 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:42:03 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3578 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:42:03 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3578 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:42:03 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3578 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:42:03 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3578 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:42:03 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3578 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:42:03 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3578 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:42:08 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:42:08 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:42:08 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:42:08 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:42:08 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:42:08 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:42:08 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:42:08 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:42:08 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:42:08 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:42:08 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 03:42:08 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 03:42:08 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 03:42:08 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:42:08 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:42:08 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:42:08 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 03:42:08 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:42:08 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 03:42:08 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 03:42:08 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 03:42:08 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:42:08 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:42:08 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:42:08 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 03:42:08 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:42:08 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 03:42:08 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 03:42:08 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 03:42:08 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:42:08 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:42:08 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:42:08 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 03:42:08 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:42:08 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 03:42:08 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 03:42:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 03:42:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 03:42:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 03:42:08 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 03:42:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 03:42:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 03:42:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 03:42:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:42:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 03:42:08 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 03:42:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:42:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:42:08 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 03:42:08 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 03:42:08 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 03:42:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:42:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:42:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:42:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 03:42:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:42:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:42:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:42:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:42:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:42:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:42:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:42:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:42:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:42:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:42:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:42:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:42:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:42:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:42:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:42:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:42:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:42:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:42:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:42:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:42:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:42:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:42:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:42:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:42:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:42:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:42:08 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 03:42:09 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 03:42:09 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 03:42:09 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 03:42:09 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 03:42:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:42:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:42:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:42:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:42:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:42:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:42:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:42:09 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:42:09 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:42:09 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 03:42:09 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 03:42:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:42:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:42:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:42:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:42:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:42:09 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 03:42:09 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:42:09 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:42:09 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:42:09 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:42:10 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 03:42:10 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 03:42:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:42:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:42:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:42:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:42:11 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 03:42:11 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 03:42:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:42:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:42:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:42:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:42:12 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 03:42:12 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 03:42:12 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:42:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:42:12 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:42:12 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:42:13 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 03:42:13 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 03:42:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:42:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:42:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:42:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:42:13 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 03:42:14 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 03:42:14 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 03:42:15 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 03:42:15 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 03:42:16 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 03:42:16 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 03:42:17 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 03:42:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:42:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:42:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:42:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:42:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:42:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:42:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:42:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:42:17 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:42:17 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:42:17 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:42:17 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:42:17 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 03:42:17 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 03:42:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:42:17 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:42:17 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:42:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:42:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:42:17 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 03:42:18 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 03:42:18 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 03:42:19 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 03:42:19 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-27 03:42:20 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-27 03:42:20 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-27 03:42:21 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-27 03:42:21 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-27 03:42:22 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-27 03:42:22 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-27 03:42:23 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-27 03:42:23 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-27 03:42:23 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-27 03:42:24 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-27 03:42:24 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-27 03:42:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:42:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:42:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:42:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:42:25 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:42:25 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:42:25 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:42:25 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:42:25 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:42:25 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:42:25 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:42:25 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:42:25 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:42:25 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:42:25 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 03:42:25 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3563 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:42:25 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3563 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:42:25 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3563 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:42:25 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3563 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:42:25 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3563 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:42:25 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3563 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:42:25 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3564 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:42:25 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3564 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:42:25 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3564 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:42:25 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3564 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:42:25 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3564 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:42:25 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3564 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:42:25 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3564 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:42:25 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3564 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:42:30 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:42:30 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:42:30 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:42:30 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:42:30 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:42:30 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:42:30 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:42:30 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:42:30 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:42:30 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:42:30 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 03:42:30 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 03:42:30 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 03:42:30 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:42:30 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:42:30 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:42:30 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 03:42:30 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:42:30 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 03:42:30 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 03:42:30 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 03:42:30 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:42:30 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:42:30 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:42:30 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 03:42:30 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:42:30 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 03:42:30 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 03:42:30 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 03:42:30 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:42:30 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:42:30 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:42:30 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 03:42:30 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:42:30 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 03:42:30 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 03:42:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 03:42:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 03:42:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 03:42:30 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 03:42:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 03:42:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 03:42:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 03:42:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 03:42:30 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 03:42:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:42:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:42:30 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 03:42:30 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 03:42:30 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 03:42:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:42:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:42:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:42:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 03:42:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:42:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:42:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:42:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:42:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:42:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:42:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:42:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:42:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:42:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:42:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:42:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:42:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:42:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:42:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:42:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:42:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:42:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:42:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:42:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:42:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:42:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:42:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:42:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:42:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:42:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:42:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:42:30 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 03:42:30 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 03:42:30 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 03:42:30 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 03:42:30 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 03:42:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:42:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:42:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:42:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:42:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:42:30 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:42:30 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:42:30 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:42:30 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:42:31 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 03:42:31 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 03:42:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:42:31 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:42:31 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:42:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:42:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:42:31 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 03:42:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:42:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:42:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:42:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:42:31 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 03:42:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:42:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:42:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:42:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:42:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:42:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:42:31 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:42:31 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:42:31 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:42:31 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:42:31 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:42:31 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:42:31 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 03:42:36 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:42:36 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:42:36 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:42:36 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:42:36 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:42:36 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:42:36 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:42:36 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:42:36 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:42:36 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:42:36 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 03:42:36 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 03:42:36 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 03:42:36 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:42:36 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:42:36 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:42:36 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 03:42:36 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:42:36 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 03:42:36 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 03:42:36 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 03:42:36 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:42:36 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:42:36 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:42:36 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 03:42:36 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:42:36 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 03:42:36 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 03:42:36 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 03:42:36 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:42:36 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:42:36 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:42:36 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 03:42:36 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:42:36 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 03:42:36 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 03:42:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 03:42:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 03:42:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 03:42:36 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 03:42:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 03:42:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 03:42:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 03:42:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:42:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 03:42:36 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 03:42:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:42:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:42:36 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 03:42:36 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 03:42:36 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 03:42:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:42:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:42:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:42:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 03:42:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:42:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:42:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:42:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:42:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:42:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:42:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:42:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:42:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:42:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:42:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:42:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:42:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:42:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:42:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:42:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:42:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:42:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:42:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:42:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:42:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:42:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:42:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:42:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:42:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:42:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:42:36 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 03:42:37 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 03:42:37 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 03:42:37 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 03:42:37 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 03:42:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:42:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:42:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:42:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:42:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:42:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:42:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:42:37 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:42:37 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:42:37 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 03:42:37 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 03:42:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:42:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:42:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:42:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:42:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:42:37 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 03:42:37 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:42:37 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:42:37 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:42:37 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:42:38 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 03:42:38 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 03:42:38 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:42:38 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:42:38 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:42:38 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:42:39 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 03:42:39 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 03:42:39 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:42:39 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:42:39 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:42:39 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:42:40 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 03:42:40 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 03:42:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:42:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:42:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:42:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:42:41 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 03:42:41 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 03:42:41 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:42:41 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:42:41 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:42:41 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:42:42 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 03:42:42 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 03:42:43 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 03:42:43 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 03:42:44 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 03:42:44 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 03:42:45 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 03:42:45 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 03:42:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:42:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:42:45 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:42:45 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:42:45 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:42:45 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:42:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:42:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:42:45 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:42:45 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:42:45 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:42:45 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:42:45 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 03:42:45 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 03:42:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:42:45 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:42:45 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:42:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:42:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:42:45 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 03:42:46 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 03:42:46 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 03:42:47 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 03:42:47 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-27 03:42:48 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-27 03:42:48 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-27 03:42:49 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-27 03:42:49 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-27 03:42:50 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-27 03:42:50 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-27 03:42:51 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-27 03:42:51 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-27 03:42:52 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-27 03:42:52 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-27 03:42:53 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-27 03:42:53 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-27 03:42:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:42:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:42:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:42:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:42:53 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:42:53 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:42:53 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:42:53 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:42:53 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:42:53 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:42:53 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:42:53 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 03:42:53 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3576 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:42:53 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:42:53 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:42:53 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:42:53 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3576 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:42:53 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3576 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:42:58 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:42:58 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:42:58 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:42:58 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:42:58 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:42:58 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:42:58 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:42:58 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:42:58 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:42:58 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:42:58 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 03:42:58 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 03:42:58 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 03:42:58 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:42:58 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:42:58 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:42:58 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 03:42:58 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:42:58 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 03:42:58 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 03:42:58 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 03:42:58 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:42:58 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:42:58 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:42:58 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 03:42:58 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:42:58 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 03:42:58 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 03:42:58 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 03:42:58 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:42:58 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:42:58 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:42:58 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 03:42:58 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:42:58 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 03:42:58 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 03:42:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 03:42:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 03:42:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 03:42:58 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 03:42:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 03:42:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 03:42:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 03:42:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 03:42:58 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 03:42:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:42:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:42:58 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 03:42:58 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 03:42:58 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 03:42:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:42:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:42:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:42:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 03:42:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:42:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:42:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:42:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:42:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:42:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:42:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:42:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:42:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:42:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:42:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:42:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:42:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:42:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:42:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:42:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:42:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:42:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:42:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:42:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:42:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:42:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:42:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:42:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:42:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:42:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:42:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:42:58 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 03:42:59 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 03:42:59 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 03:42:59 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 03:42:59 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 03:42:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:42:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:42:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:42:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:42:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:42:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:42:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:42:59 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:42:59 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:42:59 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 03:42:59 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 03:42:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:42:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:42:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:42:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:42:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:42:59 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 03:42:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:42:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:42:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:42:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:43:00 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 03:43:00 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 03:43:00 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:43:00 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:43:00 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:43:00 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:43:01 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 03:43:01 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 03:43:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:43:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:43:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:43:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:43:01 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 03:43:02 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 03:43:02 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:43:02 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:43:02 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:43:02 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:43:02 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 03:43:03 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 03:43:03 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:43:03 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:43:03 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:43:03 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:43:03 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 03:43:04 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 03:43:04 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 03:43:05 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 03:43:05 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 03:43:06 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 03:43:06 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 03:43:07 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 03:43:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:43:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:43:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:43:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:43:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:43:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:43:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:43:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:43:07 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:43:07 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:43:07 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:43:07 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:43:07 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 03:43:07 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 03:43:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:43:07 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:43:07 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:43:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:43:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:43:07 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 03:43:08 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 03:43:08 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 03:43:09 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 03:43:09 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-27 03:43:10 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-27 03:43:10 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-27 03:43:11 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-27 03:43:11 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-27 03:43:11 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-27 03:43:12 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-27 03:43:12 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-27 03:43:13 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-27 03:43:13 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-27 03:43:14 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-27 03:43:14 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-27 03:43:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:43:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:43:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:43:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:43:15 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-27 03:43:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:43:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:43:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:43:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:43:15 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:43:15 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:43:15 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:43:15 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:43:15 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 03:43:15 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 03:43:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:43:15 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:43:15 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:43:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:43:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:43:15 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-27 03:43:16 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-27 03:43:16 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-27 03:43:17 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2025-04-27 03:43:17 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2025-04-27 03:43:18 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2025-04-27 03:43:18 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2025-04-27 03:43:19 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2025-04-27 03:43:19 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2025-04-27 03:43:20 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2025-04-27 03:43:20 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2025-04-27 03:43:21 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2025-04-27 03:43:21 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2025-04-27 03:43:21 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2025-04-27 03:43:22 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2025-04-27 03:43:22 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2025-04-27 03:43:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:43:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:43:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:43:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:43:23 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2025-04-27 03:43:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:43:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:43:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:43:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:43:23 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:43:23 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:43:23 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:43:23 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:43:23 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 03:43:23 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 03:43:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:43:23 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:43:23 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:43:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:43:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:43:23 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2025-04-27 03:43:24 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2025-04-27 03:43:24 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2025-04-27 03:43:25 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2025-04-27 03:43:25 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2025-04-27 03:43:26 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2025-04-27 03:43:26 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2025-04-27 03:43:27 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2025-04-27 03:43:27 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2025-04-27 03:43:28 [DEBUG] clck_gen.py:102 IND CLOCK 6324
2025-04-27 03:43:28 [DEBUG] clck_gen.py:102 IND CLOCK 6426
2025-04-27 03:43:29 [DEBUG] clck_gen.py:102 IND CLOCK 6528
2025-04-27 03:43:29 [DEBUG] clck_gen.py:102 IND CLOCK 6630
2025-04-27 03:43:30 [DEBUG] clck_gen.py:102 IND CLOCK 6732
2025-04-27 03:43:30 [DEBUG] clck_gen.py:102 IND CLOCK 6834
2025-04-27 03:43:30 [DEBUG] clck_gen.py:102 IND CLOCK 6936
2025-04-27 03:43:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:43:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:43:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:43:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:43:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:43:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:43:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:43:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:43:31 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:43:31 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:43:31 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:43:31 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 03:43:31 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=7037 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:43:31 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:43:31 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:43:31 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:43:31 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=7037 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:43:31 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=7037 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:43:31 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=7037 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:43:31 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=7037 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:43:31 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=7037 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:43:36 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:43:36 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:43:36 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:43:36 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:43:36 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:43:36 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:43:36 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:43:36 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:43:36 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:43:36 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:43:36 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 03:43:36 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 03:43:36 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 03:43:36 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:43:36 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:43:36 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:43:36 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 03:43:36 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:43:36 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 03:43:36 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 03:43:36 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 03:43:36 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:43:36 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:43:36 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:43:36 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 03:43:36 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:43:36 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 03:43:36 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 03:43:36 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 03:43:36 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:43:36 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:43:36 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:43:36 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 03:43:36 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:43:36 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 03:43:36 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 03:43:36 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 03:43:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 03:43:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 03:43:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 03:43:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 03:43:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 03:43:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 03:43:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 03:43:36 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 03:43:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:43:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:43:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:43:36 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 03:43:36 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 03:43:36 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 03:43:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:43:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:43:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:43:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 03:43:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:43:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:43:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:43:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:43:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:43:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:43:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:43:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:43:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:43:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:43:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:43:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:43:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:43:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:43:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:43:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:43:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:43:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:43:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:43:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:43:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:43:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:43:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:43:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:43:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:43:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:43:36 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 03:43:36 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 03:43:37 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 03:43:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:43:37 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 03:43:37 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 03:43:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:43:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:43:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:43:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:43:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:43:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:43:37 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:43:37 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:43:37 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 03:43:37 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 03:43:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:43:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:43:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:43:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:43:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:43:37 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 03:43:37 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:43:37 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:43:37 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:43:37 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:43:37 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 03:43:38 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 03:43:38 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:43:38 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:43:38 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:43:38 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:43:38 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 03:43:39 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 03:43:39 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:43:39 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:43:39 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:43:39 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:43:39 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 03:43:40 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 03:43:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:43:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:43:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:43:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:43:40 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 03:43:41 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 03:43:41 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:43:41 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:43:41 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:43:41 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:43:41 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 03:43:42 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 03:43:42 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 03:43:43 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 03:43:43 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 03:43:44 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 03:43:44 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 03:43:45 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 03:43:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:43:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:43:45 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:43:45 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:43:45 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:43:45 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:43:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:43:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:43:45 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:43:45 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:43:45 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:43:45 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:43:45 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 03:43:45 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 03:43:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:43:45 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:43:45 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:43:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:43:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:43:45 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 03:43:45 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 03:43:46 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 03:43:46 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 03:43:47 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-27 03:43:47 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-27 03:43:48 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-27 03:43:48 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-27 03:43:49 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-27 03:43:49 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-27 03:43:50 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-27 03:43:50 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-27 03:43:51 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-27 03:43:51 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-27 03:43:52 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-27 03:43:52 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-27 03:43:53 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-27 03:43:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:43:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:43:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:43:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:43:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:43:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:43:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:43:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:43:53 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:43:53 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:43:53 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:43:53 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:43:53 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 03:43:53 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 03:43:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:43:53 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:43:53 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:43:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:43:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:43:53 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-27 03:43:54 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-27 03:43:54 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-27 03:43:54 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2025-04-27 03:43:55 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2025-04-27 03:43:55 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2025-04-27 03:43:56 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2025-04-27 03:43:56 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2025-04-27 03:43:57 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2025-04-27 03:43:57 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2025-04-27 03:43:58 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2025-04-27 03:43:58 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2025-04-27 03:43:59 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2025-04-27 03:43:59 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2025-04-27 03:44:00 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2025-04-27 03:44:00 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2025-04-27 03:44:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:44:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:44:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:44:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:44:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:44:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:44:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:44:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:44:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:44:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:44:01 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:44:01 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:44:01 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 03:44:01 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 03:44:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:44:01 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2025-04-27 03:44:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:44:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:44:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:44:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:44:01 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2025-04-27 03:44:02 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2025-04-27 03:44:02 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2025-04-27 03:44:03 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2025-04-27 03:44:03 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2025-04-27 03:44:04 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2025-04-27 03:44:04 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2025-04-27 03:44:05 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2025-04-27 03:44:05 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2025-04-27 03:44:05 [DEBUG] clck_gen.py:102 IND CLOCK 6324
2025-04-27 03:44:06 [DEBUG] clck_gen.py:102 IND CLOCK 6426
2025-04-27 03:44:06 [DEBUG] clck_gen.py:102 IND CLOCK 6528
2025-04-27 03:44:07 [DEBUG] clck_gen.py:102 IND CLOCK 6630
2025-04-27 03:44:07 [DEBUG] clck_gen.py:102 IND CLOCK 6732
2025-04-27 03:44:08 [DEBUG] clck_gen.py:102 IND CLOCK 6834
2025-04-27 03:44:08 [DEBUG] clck_gen.py:102 IND CLOCK 6936
2025-04-27 03:44:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:44:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:44:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:44:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:44:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:44:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:44:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:44:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:44:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:44:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:44:09 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:44:09 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:44:09 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 03:44:09 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 03:44:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:44:09 [DEBUG] clck_gen.py:102 IND CLOCK 7038
2025-04-27 03:44:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:44:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:44:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:44:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:44:09 [DEBUG] clck_gen.py:102 IND CLOCK 7140
2025-04-27 03:44:10 [DEBUG] clck_gen.py:102 IND CLOCK 7242
2025-04-27 03:44:10 [DEBUG] clck_gen.py:102 IND CLOCK 7344
2025-04-27 03:44:11 [DEBUG] clck_gen.py:102 IND CLOCK 7446
2025-04-27 03:44:11 [DEBUG] clck_gen.py:102 IND CLOCK 7548
2025-04-27 03:44:12 [DEBUG] clck_gen.py:102 IND CLOCK 7650
2025-04-27 03:44:12 [DEBUG] clck_gen.py:102 IND CLOCK 7752
2025-04-27 03:44:13 [DEBUG] clck_gen.py:102 IND CLOCK 7854
2025-04-27 03:44:13 [DEBUG] clck_gen.py:102 IND CLOCK 7956
2025-04-27 03:44:13 [DEBUG] clck_gen.py:102 IND CLOCK 8058
2025-04-27 03:44:14 [DEBUG] clck_gen.py:102 IND CLOCK 8160
2025-04-27 03:44:14 [DEBUG] clck_gen.py:102 IND CLOCK 8262
2025-04-27 03:44:15 [DEBUG] clck_gen.py:102 IND CLOCK 8364
2025-04-27 03:44:15 [DEBUG] clck_gen.py:102 IND CLOCK 8466
2025-04-27 03:44:16 [DEBUG] clck_gen.py:102 IND CLOCK 8568
2025-04-27 03:44:16 [DEBUG] clck_gen.py:102 IND CLOCK 8670
2025-04-27 03:44:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:44:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:44:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:44:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:44:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:44:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:44:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:44:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:44:17 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:44:17 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:44:17 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:44:17 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:44:17 [DEBUG] clck_gen.py:102 IND CLOCK 8772
2025-04-27 03:44:17 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 03:44:17 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 03:44:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:44:17 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:44:17 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:44:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:44:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:44:17 [DEBUG] clck_gen.py:102 IND CLOCK 8874
2025-04-27 03:44:18 [DEBUG] clck_gen.py:102 IND CLOCK 8976
2025-04-27 03:44:18 [DEBUG] clck_gen.py:102 IND CLOCK 9078
2025-04-27 03:44:19 [DEBUG] clck_gen.py:102 IND CLOCK 9180
2025-04-27 03:44:19 [DEBUG] clck_gen.py:102 IND CLOCK 9282
2025-04-27 03:44:20 [DEBUG] clck_gen.py:102 IND CLOCK 9384
2025-04-27 03:44:20 [DEBUG] clck_gen.py:102 IND CLOCK 9486
2025-04-27 03:44:21 [DEBUG] clck_gen.py:102 IND CLOCK 9588
2025-04-27 03:44:21 [DEBUG] clck_gen.py:102 IND CLOCK 9690
2025-04-27 03:44:22 [DEBUG] clck_gen.py:102 IND CLOCK 9792
2025-04-27 03:44:22 [DEBUG] clck_gen.py:102 IND CLOCK 9894
2025-04-27 03:44:22 [DEBUG] clck_gen.py:102 IND CLOCK 9996
2025-04-27 03:44:23 [DEBUG] clck_gen.py:102 IND CLOCK 10098
2025-04-27 03:44:23 [DEBUG] clck_gen.py:102 IND CLOCK 10200
2025-04-27 03:44:24 [DEBUG] clck_gen.py:102 IND CLOCK 10302
2025-04-27 03:44:24 [DEBUG] clck_gen.py:102 IND CLOCK 10404
2025-04-27 03:44:25 [DEBUG] clck_gen.py:102 IND CLOCK 10506
2025-04-27 03:44:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:44:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:44:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:44:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:44:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:44:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:44:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:44:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:44:25 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:44:25 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:44:25 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:44:25 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:44:25 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 03:44:25 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 03:44:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:44:25 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:44:25 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:44:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:44:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:44:25 [DEBUG] clck_gen.py:102 IND CLOCK 10608
2025-04-27 03:44:26 [DEBUG] clck_gen.py:102 IND CLOCK 10710
2025-04-27 03:44:26 [DEBUG] clck_gen.py:102 IND CLOCK 10812
2025-04-27 03:44:27 [DEBUG] clck_gen.py:102 IND CLOCK 10914
2025-04-27 03:44:27 [DEBUG] clck_gen.py:102 IND CLOCK 11016
2025-04-27 03:44:28 [DEBUG] clck_gen.py:102 IND CLOCK 11118
2025-04-27 03:44:28 [DEBUG] clck_gen.py:102 IND CLOCK 11220
2025-04-27 03:44:29 [DEBUG] clck_gen.py:102 IND CLOCK 11322
2025-04-27 03:44:29 [DEBUG] clck_gen.py:102 IND CLOCK 11424
2025-04-27 03:44:30 [DEBUG] clck_gen.py:102 IND CLOCK 11526
2025-04-27 03:44:30 [DEBUG] clck_gen.py:102 IND CLOCK 11628
2025-04-27 03:44:30 [DEBUG] clck_gen.py:102 IND CLOCK 11730
2025-04-27 03:44:31 [DEBUG] clck_gen.py:102 IND CLOCK 11832
2025-04-27 03:44:31 [DEBUG] clck_gen.py:102 IND CLOCK 11934
2025-04-27 03:44:32 [DEBUG] clck_gen.py:102 IND CLOCK 12036
2025-04-27 03:44:32 [DEBUG] clck_gen.py:102 IND CLOCK 12138
2025-04-27 03:44:33 [DEBUG] clck_gen.py:102 IND CLOCK 12240
2025-04-27 03:44:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:44:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:44:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:44:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:44:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:44:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:44:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:44:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:44:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:44:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:44:33 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:44:33 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:44:33 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 03:44:33 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 03:44:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:44:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:44:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:44:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:44:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:44:33 [DEBUG] clck_gen.py:102 IND CLOCK 12342
2025-04-27 03:44:34 [DEBUG] clck_gen.py:102 IND CLOCK 12444
2025-04-27 03:44:34 [DEBUG] clck_gen.py:102 IND CLOCK 12546
2025-04-27 03:44:35 [DEBUG] clck_gen.py:102 IND CLOCK 12648
2025-04-27 03:44:35 [DEBUG] clck_gen.py:102 IND CLOCK 12750
2025-04-27 03:44:36 [DEBUG] clck_gen.py:102 IND CLOCK 12852
2025-04-27 03:44:36 [DEBUG] clck_gen.py:102 IND CLOCK 12954
2025-04-27 03:44:37 [DEBUG] clck_gen.py:102 IND CLOCK 13056
2025-04-27 03:44:37 [DEBUG] clck_gen.py:102 IND CLOCK 13158
2025-04-27 03:44:38 [DEBUG] clck_gen.py:102 IND CLOCK 13260
2025-04-27 03:44:38 [DEBUG] clck_gen.py:102 IND CLOCK 13362
2025-04-27 03:44:38 [DEBUG] clck_gen.py:102 IND CLOCK 13464
2025-04-27 03:44:39 [DEBUG] clck_gen.py:102 IND CLOCK 13566
2025-04-27 03:44:39 [DEBUG] clck_gen.py:102 IND CLOCK 13668
2025-04-27 03:44:40 [DEBUG] clck_gen.py:102 IND CLOCK 13770
2025-04-27 03:44:40 [DEBUG] clck_gen.py:102 IND CLOCK 13872
2025-04-27 03:44:41 [DEBUG] clck_gen.py:102 IND CLOCK 13974
2025-04-27 03:44:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:44:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:44:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:44:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:44:41 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:44:41 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:44:41 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:44:41 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:44:41 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:44:41 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:44:41 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:44:41 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:44:41 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:44:41 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:44:41 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 03:44:41 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=14001 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:44:41 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=14001 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:44:41 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=14001 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:44:41 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=14001 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:44:41 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=14001 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:44:41 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=14001 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:44:41 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=14002 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:44:41 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=14002 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:44:41 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=14002 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:44:41 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=14002 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:44:41 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=14002 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:44:41 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=14002 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:44:41 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=14002 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:44:41 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=14002 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:44:41 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=14003 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:44:41 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=14003 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:44:41 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=14003 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:44:41 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=14003 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:44:41 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=14003 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:44:41 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=14003 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:44:41 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=14003 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:44:41 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=14003 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:44:46 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:44:46 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:44:46 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:44:46 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:44:46 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:44:46 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:44:46 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:44:46 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:44:46 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:44:46 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 03:44:46 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 03:44:46 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:44:46 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 03:44:46 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 03:44:46 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 03:44:46 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:44:46 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:44:46 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:44:46 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:44:46 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:44:46 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:44:46 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 03:44:46 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 03:44:46 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:44:46 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 03:44:46 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:44:46 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 03:44:46 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 03:44:46 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 03:44:46 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:44:46 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:44:46 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:44:46 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 03:44:46 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:44:46 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 03:44:46 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 03:44:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 03:44:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 03:44:46 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 03:44:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 03:44:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 03:44:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 03:44:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 03:44:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 03:44:46 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 03:44:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:44:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:44:46 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 03:44:46 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 03:44:46 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 03:44:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:44:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:44:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:44:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 03:44:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:44:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:44:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:44:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:44:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:44:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:44:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:44:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:44:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:44:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:44:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:44:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:44:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:44:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:44:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:44:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:44:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:44:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:44:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:44:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:44:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:44:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:44:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:44:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:44:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:44:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:44:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:44:46 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 03:44:46 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 03:44:46 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 03:44:46 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 03:44:46 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 03:44:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:44:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:44:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:44:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:44:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:44:47 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:44:47 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:44:47 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:44:47 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:44:47 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 03:44:47 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 03:44:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:44:47 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:44:47 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:44:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:44:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:44:47 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 03:44:47 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:44:47 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:44:47 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:44:47 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:44:47 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 03:44:48 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 03:44:48 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:44:48 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:44:48 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:44:48 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:44:48 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 03:44:49 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 03:44:49 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:44:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:44:49 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:44:49 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:44:49 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 03:44:50 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 03:44:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:44:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:44:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:44:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:44:50 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 03:44:51 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 03:44:51 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:44:51 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:44:51 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:44:51 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:44:51 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 03:44:52 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 03:44:52 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 03:44:53 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 03:44:53 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 03:44:54 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 03:44:54 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 03:44:55 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 03:44:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:44:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:44:55 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:44:55 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:44:55 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:44:55 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:44:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:44:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:44:55 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:44:55 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:44:55 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:44:55 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:44:55 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 03:44:55 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 03:44:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:44:55 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:44:55 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:44:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:44:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:44:55 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 03:44:56 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 03:44:56 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 03:44:56 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 03:44:57 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-27 03:44:57 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-27 03:44:58 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-27 03:44:58 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-27 03:44:59 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-27 03:44:59 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-27 03:45:00 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-27 03:45:00 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-27 03:45:01 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-27 03:45:01 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-27 03:45:02 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-27 03:45:02 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-27 03:45:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:45:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:45:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:45:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:45:03 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:45:03 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:45:03 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:45:03 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:45:03 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:45:03 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:45:03 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:45:03 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:45:03 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 03:45:03 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:45:03 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:45:03 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3568 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:45:03 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3568 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:45:03 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3568 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:45:03 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3568 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:45:03 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3568 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:45:03 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3568 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:45:03 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3568 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:45:08 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:45:08 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:45:08 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:45:08 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:45:08 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:45:08 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:45:08 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:45:08 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:45:08 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:45:08 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:45:08 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 03:45:08 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 03:45:08 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 03:45:08 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:45:08 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:45:08 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 03:45:08 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:45:08 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:45:08 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 03:45:08 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 03:45:08 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 03:45:08 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:45:08 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:45:08 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:45:08 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 03:45:08 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:45:08 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 03:45:08 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 03:45:08 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 03:45:08 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:45:08 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:45:08 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:45:08 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 03:45:08 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:45:08 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 03:45:08 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 03:45:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 03:45:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 03:45:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 03:45:08 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 03:45:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 03:45:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 03:45:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 03:45:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:45:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 03:45:08 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 03:45:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:45:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:45:08 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 03:45:08 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 03:45:08 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 03:45:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:45:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:45:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:45:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 03:45:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:45:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:45:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:45:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:45:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:45:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:45:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:45:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:45:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:45:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:45:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:45:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:45:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:45:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:45:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:45:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:45:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:45:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:45:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:45:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:45:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:45:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:45:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:45:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:45:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:45:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:45:08 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 03:45:08 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 03:45:08 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 03:45:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:45:08 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 03:45:08 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 03:45:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:45:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:45:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:45:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:45:08 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:45:08 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:45:08 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:45:08 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:45:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:45:08 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:45:08 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:45:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:45:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:45:09 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 03:45:09 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:45:09 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:45:09 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:45:09 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:45:09 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 03:45:10 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 03:45:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:45:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:45:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:45:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:45:10 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 03:45:11 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 03:45:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:45:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:45:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:45:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:45:11 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 03:45:11 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 03:45:12 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:45:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:45:12 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:45:12 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:45:12 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 03:45:12 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 03:45:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:45:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:45:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:45:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:45:13 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 03:45:13 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 03:45:14 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 03:45:14 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 03:45:15 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 03:45:15 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 03:45:16 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 03:45:16 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 03:45:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:45:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:45:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:45:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:45:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:45:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:45:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:45:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:45:16 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:45:16 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:45:16 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:45:16 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:45:16 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:45:16 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:45:16 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 03:45:16 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1851 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:45:16 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1851 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:45:16 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1851 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:45:16 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1851 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:45:16 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1851 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:45:16 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1851 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:45:16 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1852 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:45:16 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1852 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:45:16 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1852 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:45:16 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1852 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:45:16 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1852 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:45:16 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1852 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:45:16 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1852 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:45:16 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1852 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:45:21 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:45:21 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:45:21 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:45:21 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:45:21 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:45:21 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:45:21 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:45:21 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:45:21 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:45:21 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:45:21 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 03:45:21 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 03:45:21 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 03:45:21 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:45:21 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:45:21 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:45:21 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 03:45:21 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:45:21 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 03:45:21 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 03:45:21 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 03:45:21 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:45:21 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:45:21 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:45:21 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 03:45:21 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:45:21 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 03:45:21 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 03:45:21 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 03:45:21 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:45:21 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:45:21 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:45:21 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 03:45:21 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:45:21 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 03:45:21 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 03:45:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 03:45:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 03:45:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 03:45:21 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 03:45:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 03:45:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 03:45:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 03:45:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:45:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 03:45:21 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 03:45:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:45:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:45:21 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 03:45:21 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 03:45:21 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 03:45:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:45:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:45:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:45:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 03:45:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:45:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:45:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:45:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:45:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:45:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:45:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:45:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:45:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:45:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:45:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:45:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:45:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:45:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:45:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:45:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:45:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:45:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:45:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:45:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:45:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:45:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:45:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:45:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:45:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:45:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:45:21 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 03:45:22 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 03:45:22 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 03:45:22 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 03:45:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:45:22 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 03:45:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:45:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:45:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:45:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:45:22 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:45:22 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:45:22 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:45:22 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:45:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:45:22 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:45:22 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:45:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:45:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:45:22 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 03:45:22 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:45:22 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:45:22 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:45:22 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:45:23 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 03:45:23 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 03:45:23 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:45:23 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:45:23 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:45:23 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:45:24 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 03:45:24 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 03:45:24 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:45:24 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:45:24 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:45:24 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:45:25 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 03:45:25 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 03:45:25 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:45:25 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:45:25 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:45:25 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:45:26 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 03:45:26 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 03:45:26 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:45:26 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:45:26 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:45:26 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:45:27 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 03:45:27 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 03:45:27 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 03:45:28 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 03:45:28 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 03:45:29 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 03:45:29 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 03:45:30 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 03:45:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:45:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:45:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:45:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:45:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:45:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:45:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:45:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:45:30 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:45:30 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:45:30 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:45:30 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:45:30 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:45:30 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 03:45:30 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:45:30 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1851 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:45:30 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1851 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:45:30 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1851 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:45:30 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1851 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:45:30 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1851 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:45:30 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1851 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:45:30 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1852 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:45:30 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1852 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:45:30 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1852 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:45:30 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1852 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:45:30 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1852 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:45:30 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1852 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:45:30 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1852 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:45:30 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1852 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:45:35 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:45:35 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:45:35 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:45:35 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:45:35 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:45:35 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:45:35 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:45:35 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:45:35 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:45:35 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:45:35 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 03:45:35 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 03:45:35 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 03:45:35 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:45:35 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:45:35 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:45:35 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 03:45:35 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:45:35 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 03:45:35 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 03:45:35 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 03:45:35 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:45:35 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:45:35 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:45:35 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 03:45:35 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:45:35 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 03:45:35 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 03:45:35 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 03:45:35 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:45:35 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:45:35 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:45:35 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 03:45:35 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:45:35 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 03:45:35 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 03:45:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 03:45:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 03:45:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 03:45:35 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 03:45:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 03:45:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 03:45:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 03:45:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 03:45:35 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 03:45:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:45:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:45:35 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 03:45:35 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 03:45:35 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 03:45:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:45:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:45:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:45:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 03:45:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:45:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:45:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:45:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:45:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:45:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:45:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:45:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:45:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:45:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:45:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:45:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:45:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:45:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:45:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:45:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:45:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:45:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:45:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:45:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:45:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:45:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:45:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:45:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:45:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:45:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:45:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:45:35 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 03:45:35 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 03:45:35 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 03:45:35 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 03:45:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:45:35 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 03:45:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:45:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:45:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:45:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:45:35 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:45:35 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:45:35 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:45:35 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:45:36 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 03:45:36 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:45:36 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:45:36 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:45:36 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:45:36 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 03:45:37 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 03:45:37 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:45:37 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:45:37 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:45:37 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:45:37 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 03:45:38 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 03:45:38 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:45:38 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:45:38 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:45:38 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:45:38 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 03:45:39 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 03:45:39 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:45:39 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:45:39 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:45:39 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:45:39 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 03:45:40 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 03:45:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:45:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:45:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:45:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:45:40 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 03:45:41 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 03:45:41 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 03:45:42 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 03:45:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:45:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:45:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:45:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:45:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:45:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:45:42 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:45:42 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:45:42 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:45:42 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:45:42 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:45:42 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:45:42 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 03:45:47 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:45:47 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:45:47 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:45:47 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:45:47 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:45:47 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:45:47 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:45:47 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:45:47 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:45:47 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:45:47 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 03:45:47 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 03:45:47 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 03:45:47 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:45:47 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:45:47 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:45:47 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 03:45:47 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:45:47 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 03:45:47 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 03:45:47 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 03:45:47 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:45:47 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:45:47 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:45:47 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 03:45:47 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:45:47 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 03:45:47 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 03:45:47 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 03:45:47 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:45:47 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:45:47 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:45:47 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 03:45:47 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:45:47 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 03:45:47 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 03:45:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 03:45:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 03:45:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 03:45:47 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 03:45:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 03:45:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 03:45:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 03:45:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:45:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 03:45:47 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 03:45:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:45:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:45:47 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 03:45:47 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 03:45:47 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 03:45:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:45:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:45:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:45:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 03:45:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:45:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:45:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:45:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:45:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:45:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:45:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:45:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:45:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:45:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:45:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:45:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:45:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:45:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:45:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:45:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:45:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:45:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:45:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:45:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:45:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:45:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:45:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:45:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:45:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:45:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:45:47 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 03:45:48 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 03:45:48 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 03:45:48 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 03:45:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:45:48 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 03:45:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:45:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:45:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:45:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:45:48 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:45:48 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:45:48 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:45:48 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:45:48 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 03:45:48 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:45:48 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:45:48 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:45:48 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:45:48 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 03:45:49 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 03:45:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:45:49 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:45:49 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:45:49 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:45:49 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 03:45:50 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 03:45:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:45:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:45:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:45:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:45:50 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 03:45:51 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 03:45:51 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:45:51 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:45:51 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:45:51 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:45:51 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 03:45:52 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 03:45:52 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:45:52 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:45:52 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:45:52 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:45:52 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:45:52 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:45:52 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:45:52 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:45:52 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:45:52 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:45:52 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:45:52 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:45:52 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:45:52 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:45:52 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 03:45:53 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 03:45:53 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 03:45:54 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 03:45:54 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 03:45:55 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 03:45:55 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 03:45:56 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 03:45:56 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 03:45:57 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 03:45:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:45:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:45:57 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 03:45:57 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:45:57 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:45:57 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:45:57 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:45:57 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:45:57 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:45:57 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:45:57 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:45:57 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:45:57 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:45:57 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 03:45:57 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 03:45:57 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 03:45:57 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:45:57 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:45:57 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:45:57 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 03:45:57 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:45:57 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 03:45:57 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 03:45:57 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 03:45:57 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:45:57 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:45:57 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:45:57 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 03:45:57 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:45:57 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 03:45:57 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 03:45:57 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 03:45:57 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:45:57 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:45:57 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:45:57 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 03:45:57 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:45:57 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 03:45:57 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 03:45:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 03:45:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 03:45:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 03:45:57 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 03:45:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 03:45:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 03:45:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 03:45:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 03:45:57 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 03:45:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:45:57 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 03:45:57 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 03:45:57 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 03:45:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:45:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:45:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:45:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 03:45:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:45:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:45:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:45:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:45:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:45:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:45:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:45:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:45:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:45:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:45:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:45:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:45:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:45:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:45:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:45:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:45:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:45:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:45:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:45:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:45:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:45:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:45:57 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:45:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:45:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:45:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:45:57 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:45:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:45:57 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:45:57 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:45:57 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 03:45:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:45:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:46:02 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:46:02 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:46:02 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:46:02 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:46:02 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:46:02 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:46:02 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:46:02 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:46:02 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:46:02 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:46:02 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 03:46:02 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 03:46:02 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 03:46:02 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:46:02 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:46:02 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:46:02 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 03:46:02 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:46:02 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 03:46:02 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 03:46:02 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 03:46:02 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:46:02 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:46:02 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:46:02 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 03:46:02 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:46:02 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 03:46:02 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 03:46:02 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 03:46:02 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:46:02 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:46:02 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:46:02 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 03:46:02 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:46:02 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 03:46:02 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 03:46:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 03:46:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 03:46:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 03:46:02 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 03:46:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 03:46:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 03:46:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 03:46:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 03:46:02 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 03:46:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:46:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:46:02 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 03:46:02 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 03:46:02 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 03:46:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:46:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:46:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:46:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 03:46:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:46:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:46:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:46:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:46:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:46:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:46:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:46:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:46:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:46:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:46:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:46:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:46:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:46:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:46:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:46:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:46:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:46:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:46:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:46:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:46:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:46:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:46:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:46:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:46:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:46:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:46:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:46:02 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 03:46:03 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 03:46:03 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 03:46:03 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 03:46:03 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 03:46:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:46:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:46:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:46:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:46:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:46:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:46:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:46:03 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:46:03 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:46:03 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 03:46:03 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:46:03 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:46:03 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:46:03 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:46:04 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 03:46:04 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 03:46:04 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:46:04 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:46:04 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:46:04 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:46:05 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 03:46:05 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 03:46:05 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:46:05 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:46:05 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:46:05 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:46:06 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 03:46:06 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 03:46:06 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:46:06 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:46:06 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:46:06 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:46:06 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 03:46:07 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 03:46:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:46:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:46:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:46:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:46:07 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 03:46:08 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 03:46:08 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:46:08 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 03:46:09 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 03:46:09 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:46:09 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 03:46:10 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 03:46:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:46:10 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 03:46:11 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 03:46:11 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 03:46:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:46:12 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 03:46:12 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 03:46:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:46:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:46:13 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 03:46:13 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-27 03:46:14 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-27 03:46:14 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-27 03:46:15 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-27 03:46:15 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-27 03:46:15 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:46:16 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-27 03:46:16 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-27 03:46:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:46:16 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-27 03:46:17 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-27 03:46:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:46:17 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-27 03:46:18 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-27 03:46:18 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:46:18 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-27 03:46:19 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-27 03:46:19 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:46:19 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-27 03:46:20 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-27 03:46:20 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:46:20 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-27 03:46:21 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2025-04-27 03:46:21 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2025-04-27 03:46:22 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2025-04-27 03:46:22 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2025-04-27 03:46:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:46:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:46:22 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:46:22 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:46:22 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:46:22 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:46:22 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:46:22 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:46:22 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:46:22 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:46:22 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 03:46:22 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:46:22 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:46:22 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4315 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:46:22 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4315 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:46:22 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4315 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:46:22 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4315 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:46:22 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4315 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:46:22 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4315 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:46:27 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:46:27 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:46:27 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:46:27 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:46:27 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:46:27 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:46:27 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:46:27 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:46:27 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:46:27 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:46:27 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 03:46:27 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 03:46:27 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 03:46:27 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:46:27 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:46:27 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:46:27 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 03:46:27 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:46:27 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 03:46:27 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 03:46:27 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 03:46:27 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:46:27 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:46:27 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:46:27 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 03:46:27 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:46:27 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 03:46:27 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 03:46:27 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 03:46:27 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:46:27 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:46:27 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:46:27 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 03:46:27 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:46:27 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 03:46:27 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 03:46:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 03:46:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 03:46:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 03:46:27 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 03:46:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 03:46:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 03:46:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 03:46:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:46:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 03:46:27 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 03:46:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:46:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:46:27 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 03:46:27 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 03:46:27 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 03:46:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:46:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:46:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:46:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 03:46:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:46:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:46:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:46:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:46:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:46:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:46:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:46:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:46:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:46:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:46:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:46:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:46:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:46:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:46:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:46:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:46:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:46:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:46:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:46:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:46:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:46:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:46:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:46:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:46:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:46:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:46:27 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 03:46:28 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 03:46:28 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 03:46:28 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 03:46:28 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 03:46:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:46:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:46:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:46:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:46:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:46:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:46:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:46:28 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:46:28 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:46:28 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 03:46:28 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 03:46:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD NOHANDOVER
2025-04-27 03:46:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:46:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:46:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:46:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:46:28 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=130 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:28 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=131 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:28 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=132 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:28 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=133 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:28 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=134 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:28 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=135 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:28 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=136 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:28 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=137 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:28 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=138 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:28 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=139 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:28 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=140 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:28 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=141 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:28 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=143 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:28 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=144 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:28 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=145 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:28 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=146 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:28 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=147 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:28 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=148 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:28 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=149 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:28 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=150 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:28 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=151 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:28 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=152 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:28 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=153 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:28 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=154 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:28 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=156 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:28 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=157 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:28 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=158 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:28 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=159 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:28 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=160 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:28 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=161 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:28 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=162 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:28 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=163 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:28 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=164 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:28 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=165 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:28 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=166 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:28 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=167 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:28 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=169 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:28 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=170 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:28 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=171 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:28 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=172 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:28 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=173 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:28 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=174 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:28 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=175 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:28 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=176 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:28 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=177 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:28 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=178 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:28 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=179 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:28 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=180 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:28 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=182 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:28 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=183 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:28 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=184 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:28 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=185 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:28 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=186 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:28 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=187 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:28 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=188 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:28 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=189 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:28 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=190 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:28 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=191 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:28 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=192 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:28 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=193 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:28 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=195 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:28 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=196 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:28 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=197 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:28 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=198 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:28 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=199 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:28 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=200 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:28 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=201 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:28 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=202 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:28 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=203 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:28 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=204 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:28 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=205 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:28 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=206 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:28 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 03:46:28 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=208 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:28 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=209 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:28 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=210 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:28 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=211 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:28 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:46:28 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:46:28 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:46:28 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:46:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD NOHANDOVER
2025-04-27 03:46:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:46:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:46:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:46:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:46:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:46:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:46:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:46:29 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:46:29 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:46:29 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:46:29 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:46:29 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:46:29 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:46:29 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 03:46:34 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:46:34 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:46:34 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:46:34 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:46:34 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:46:34 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:46:34 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:46:34 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:46:34 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:46:34 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:46:34 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 03:46:34 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 03:46:34 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 03:46:34 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:46:34 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:46:34 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:46:34 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 03:46:34 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:46:34 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 03:46:34 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 03:46:34 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 03:46:34 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:46:34 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:46:34 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:46:34 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 03:46:34 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:46:34 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 03:46:34 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 03:46:34 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 03:46:34 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:46:34 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:46:34 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 03:46:34 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:46:34 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:46:34 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 03:46:34 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 03:46:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 03:46:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 03:46:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 03:46:34 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 03:46:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 03:46:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 03:46:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 03:46:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 03:46:34 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 03:46:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:46:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:46:34 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 03:46:34 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 03:46:34 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 03:46:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:46:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:46:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:46:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 03:46:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:46:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:46:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:46:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:46:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:46:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:46:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:46:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:46:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:46:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:46:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:46:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:46:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:46:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:46:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:46:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:46:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:46:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:46:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:46:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:46:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:46:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:46:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:46:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:46:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:46:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:46:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:46:34 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 03:46:34 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 03:46:34 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 03:46:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:46:34 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 03:46:34 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 03:46:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:46:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:46:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:46:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:46:34 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:46:34 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:46:34 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:46:34 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:46:34 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 03:46:34 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 03:46:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD NOHANDOVER
2025-04-27 03:46:34 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:46:34 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:46:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:46:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:46:34 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=130 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:34 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=131 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:34 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=132 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:34 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=133 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:34 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=134 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:34 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=135 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:34 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=136 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:34 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=137 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:34 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=138 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:34 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=139 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:34 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=140 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:34 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=141 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:35 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=143 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:35 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=144 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:35 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=145 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:35 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=146 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:35 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=147 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:35 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=148 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:35 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=149 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:35 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=150 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:35 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=151 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:35 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=152 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:35 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=153 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:35 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=154 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:35 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=156 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:35 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=157 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:35 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=158 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:35 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=159 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:35 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=160 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:35 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=161 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:35 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=162 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:35 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=163 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:35 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=164 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:35 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=165 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:35 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=166 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:35 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=167 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:35 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=169 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:35 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=170 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:35 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=171 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:35 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=172 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:35 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=173 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:35 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=174 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:35 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=175 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:35 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=176 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:35 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=177 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:35 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=178 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:35 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=179 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:35 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=180 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:35 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=182 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:35 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=183 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:35 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=184 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:35 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=185 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:35 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=186 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:35 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=187 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:35 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=188 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:35 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=189 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:35 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=190 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:35 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=191 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:35 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=192 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:35 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=193 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:35 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=195 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:35 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=196 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:35 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=197 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:35 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=198 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:35 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=199 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:35 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=200 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:35 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=201 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:35 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=202 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:35 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=203 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:35 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=204 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:35 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=205 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:35 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=206 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:35 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 03:46:35 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=208 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:35 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=209 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:35 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=210 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:35 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=211 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:35 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=212 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:35 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=213 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:35 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=214 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:35 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=215 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 03:46:35 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:46:35 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:46:35 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:46:35 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:46:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD NOHANDOVER
2025-04-27 03:46:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:46:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:46:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:46:35 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:46:35 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:46:35 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:46:35 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:46:35 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:46:35 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:46:35 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:46:35 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:46:35 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 03:46:35 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=302 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:46:35 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:46:35 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:46:35 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=302 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:46:35 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=302 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:46:35 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=302 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:46:35 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=302 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:46:40 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:46:40 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:46:40 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:46:40 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:46:40 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:46:40 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:46:40 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:46:40 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:46:40 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:46:40 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:46:40 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 03:46:40 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 03:46:40 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 03:46:40 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:46:40 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:46:40 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:46:40 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 03:46:40 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:46:40 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 03:46:40 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 03:46:40 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 03:46:40 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:46:40 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:46:40 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:46:40 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 03:46:40 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:46:40 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 03:46:40 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 03:46:40 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 03:46:40 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:46:40 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:46:40 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:46:40 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 03:46:40 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:46:40 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 03:46:40 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 03:46:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 03:46:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 03:46:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 03:46:40 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 03:46:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 03:46:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 03:46:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 03:46:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 03:46:40 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 03:46:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:46:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:46:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:46:40 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 03:46:40 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 03:46:40 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 03:46:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:46:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:46:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:46:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 03:46:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:46:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:46:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:46:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:46:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:46:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:46:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:46:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:46:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:46:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:46:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:46:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:46:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:46:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:46:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:46:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:46:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:46:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:46:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:46:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:46:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:46:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:46:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:46:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:46:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:46:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:46:40 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 03:46:41 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 03:46:41 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 03:46:41 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 03:46:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:46:41 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 03:46:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:46:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:46:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:46:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:46:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:46:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:46:41 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:46:41 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:46:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:46:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:46:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:46:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:46:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:46:41 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 03:46:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:46:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:46:41 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:46:41 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:46:41 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:46:41 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:46:41 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:46:41 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:46:41 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:46:41 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:46:41 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:46:41 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:46:41 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 03:46:41 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=209 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:46:46 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:46:46 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:46:46 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:46:46 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:46:46 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:46:46 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:46:46 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:46:46 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:46:46 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:46:46 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:46:46 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 03:46:46 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 03:46:46 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 03:46:46 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:46:46 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:46:46 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:46:46 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 03:46:46 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:46:46 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 03:46:46 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 03:46:46 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 03:46:46 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:46:46 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:46:46 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:46:46 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 03:46:46 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:46:46 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 03:46:46 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 03:46:46 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 03:46:46 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:46:46 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:46:46 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:46:46 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 03:46:46 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:46:46 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 03:46:46 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 03:46:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 03:46:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 03:46:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 03:46:46 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 03:46:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 03:46:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 03:46:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 03:46:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:46:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 03:46:46 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 03:46:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:46:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:46:46 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 03:46:46 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 03:46:46 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 03:46:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:46:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:46:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:46:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 03:46:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:46:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:46:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:46:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:46:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:46:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:46:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:46:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:46:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:46:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:46:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:46:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:46:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:46:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:46:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:46:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:46:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:46:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:46:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:46:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:46:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:46:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:46:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:46:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:46:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:46:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:46:46 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 03:46:47 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 03:46:47 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 03:46:47 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 03:46:47 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 03:46:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:46:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:46:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:46:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:46:47 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 03:46:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:46:47 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:46:47 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:46:47 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:46:47 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:46:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:46:47 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:46:47 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:46:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:46:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:46:47 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 03:46:47 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:46:47 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:46:47 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:46:47 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:46:48 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 03:46:48 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 03:46:48 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:46:48 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:46:48 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:46:48 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:46:49 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 03:46:49 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 03:46:49 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:46:49 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:46:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:46:49 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:46:50 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 03:46:50 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 03:46:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:46:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:46:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:46:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:46:51 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 03:46:51 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 03:46:51 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:46:51 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:46:51 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:46:51 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:46:52 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 03:46:52 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 03:46:53 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 03:46:53 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 03:46:53 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 03:46:54 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 03:46:54 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 03:46:55 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 03:46:55 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 03:46:56 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 03:46:56 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 03:46:57 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 03:46:57 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-27 03:46:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:46:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:46:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:46:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:46:57 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:46:57 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:46:57 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:46:57 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:46:57 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:46:57 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:46:57 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:46:57 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:46:57 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:46:57 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:46:57 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 03:47:02 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:47:02 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:47:02 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:47:02 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:47:02 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:47:02 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:47:02 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:47:02 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:47:02 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:47:02 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:47:02 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 03:47:02 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 03:47:02 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 03:47:02 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:47:02 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:47:02 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:47:02 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 03:47:02 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:47:02 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 03:47:02 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 03:47:02 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 03:47:02 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:47:02 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:47:02 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:47:02 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 03:47:02 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:47:02 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 03:47:02 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 03:47:02 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 03:47:02 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:47:02 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:47:02 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:47:02 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 03:47:02 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:47:02 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 03:47:02 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 03:47:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 03:47:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 03:47:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 03:47:02 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 03:47:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 03:47:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 03:47:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 03:47:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 03:47:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:47:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:47:02 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 03:47:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:47:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:47:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:47:02 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 03:47:02 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 03:47:02 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 03:47:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:47:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:47:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:47:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 03:47:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:47:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:47:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:47:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:47:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:47:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:47:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:47:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:47:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:47:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:47:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:47:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:47:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:47:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:47:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:47:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:47:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:47:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:47:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:47:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:47:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:47:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:47:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:47:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:47:02 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 03:47:03 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 03:47:03 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 03:47:03 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 03:47:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:47:03 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 03:47:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:47:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:47:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:47:03 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 03:47:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:47:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:47:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:47:03 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:47:03 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:47:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:47:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:47:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:47:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:47:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:47:03 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 03:47:03 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:47:03 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:47:03 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:47:03 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:47:04 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 03:47:04 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 03:47:04 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:47:04 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:47:04 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:47:04 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:47:05 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 03:47:05 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 03:47:05 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:47:05 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:47:05 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:47:05 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:47:06 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 03:47:06 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 03:47:06 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:47:06 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:47:06 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:47:06 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:47:07 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 03:47:07 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 03:47:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:47:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:47:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:47:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:47:08 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 03:47:08 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 03:47:09 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 03:47:09 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 03:47:09 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 03:47:10 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 03:47:10 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 03:47:11 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 03:47:11 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 03:47:12 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 03:47:12 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 03:47:13 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 03:47:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:47:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:47:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:47:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:47:13 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-27 03:47:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:47:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:47:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:47:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:47:13 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:47:13 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:47:13 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:47:13 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:47:13 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:47:13 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:47:13 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 03:47:13 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2350 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:47:13 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2350 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:47:13 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2350 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:47:13 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2350 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:47:13 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2350 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:47:13 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2350 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:47:18 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:47:18 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:47:18 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:47:18 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:47:18 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:47:18 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:47:18 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:47:18 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:47:18 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:47:18 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:47:18 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 03:47:18 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 03:47:18 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 03:47:18 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:47:18 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:47:18 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:47:18 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 03:47:18 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:47:18 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 03:47:18 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 03:47:18 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 03:47:18 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:47:18 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:47:18 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:47:18 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 03:47:18 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:47:18 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 03:47:18 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 03:47:18 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 03:47:18 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:47:18 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:47:18 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:47:18 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 03:47:18 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:47:18 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 03:47:18 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 03:47:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 03:47:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 03:47:18 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 03:47:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 03:47:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 03:47:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 03:47:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 03:47:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 03:47:18 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 03:47:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:47:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:47:18 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 03:47:18 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 03:47:18 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 03:47:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:47:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:47:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:47:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 03:47:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:47:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:47:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:47:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:47:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:47:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:47:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:47:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:47:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:47:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:47:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:47:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:47:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:47:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:47:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:47:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:47:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:47:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:47:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:47:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:47:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:47:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:47:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:47:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:47:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:47:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:47:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:47:18 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 03:47:19 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 03:47:19 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 03:47:19 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 03:47:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:47:19 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 03:47:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:47:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:47:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:47:19 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 03:47:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:47:19 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:47:19 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:47:19 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:47:19 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:47:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:47:19 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:47:19 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:47:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:47:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:47:19 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 03:47:19 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:47:19 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:47:19 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:47:19 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:47:20 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 03:47:20 [DEBUG] fake_trx.py:263 (MS@172.18.127.22:6700) Recv SETTA cmd
2025-04-27 03:47:20 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 03:47:20 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:47:20 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:47:20 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:47:20 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:47:21 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 03:47:21 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 03:47:21 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:47:21 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:47:21 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:47:21 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:47:22 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 03:47:22 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 03:47:22 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:47:22 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:47:22 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:47:22 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:47:23 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 03:47:23 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 03:47:23 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:47:23 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:47:23 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:47:23 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:47:24 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 03:47:24 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 03:47:25 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 03:47:25 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 03:47:26 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 03:47:26 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 03:47:26 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 03:47:27 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 03:47:27 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 03:47:28 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 03:47:28 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 03:47:29 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 03:47:29 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-27 03:47:30 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-27 03:47:30 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-27 03:47:31 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-27 03:47:31 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-27 03:47:32 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-27 03:47:32 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-27 03:47:33 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-27 03:47:33 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-27 03:47:34 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-27 03:47:34 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-27 03:47:35 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-27 03:47:35 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-27 03:47:35 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-27 03:47:36 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-27 03:47:36 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-27 03:47:37 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2025-04-27 03:47:37 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2025-04-27 03:47:38 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2025-04-27 03:47:38 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2025-04-27 03:47:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:47:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:47:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:47:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:47:39 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:47:39 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:47:39 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:47:39 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:47:39 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:47:39 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:47:39 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:47:39 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:47:39 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:47:39 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:47:39 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 03:47:39 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4345 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:47:39 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4345 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:47:39 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4345 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:47:39 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4345 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:47:39 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4345 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:47:39 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4345 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:47:39 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4345 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:47:39 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4346 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:47:39 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4346 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:47:39 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4346 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:47:39 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4346 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:47:39 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4346 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:47:39 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4346 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:47:39 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4346 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:47:39 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4346 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:47:44 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:47:44 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:47:44 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:47:44 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:47:44 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:47:44 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:47:44 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:47:44 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:47:44 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:47:44 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:47:44 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 03:47:44 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 03:47:44 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 03:47:44 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:47:44 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:47:44 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:47:44 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 03:47:44 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:47:44 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 03:47:44 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 03:47:44 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 03:47:44 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:47:44 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:47:44 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:47:44 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 03:47:44 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:47:44 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 03:47:44 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 03:47:44 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 03:47:44 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:47:44 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:47:44 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:47:44 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 03:47:44 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:47:44 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 03:47:44 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 03:47:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 03:47:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 03:47:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 03:47:44 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 03:47:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 03:47:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 03:47:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 03:47:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 03:47:44 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 03:47:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:47:44 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 03:47:44 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 03:47:44 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 03:47:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:47:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:47:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:47:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 03:47:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:47:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:47:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:47:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:47:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:47:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:47:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:47:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:47:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:47:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:47:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:47:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:47:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:47:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:47:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:47:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:47:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:47:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:47:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:47:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:47:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:47:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:47:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:47:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:47:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:47:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:47:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:47:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:47:44 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 03:47:44 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 03:47:44 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 03:47:44 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 03:47:44 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 03:47:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:47:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:47:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:47:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:47:44 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 03:47:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:47:44 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:47:44 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:47:44 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:47:44 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:47:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:47:44 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:47:44 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:47:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:47:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:47:45 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 03:47:45 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:47:45 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:47:45 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:47:45 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:47:45 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 03:47:46 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 03:47:46 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:47:46 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:47:46 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:47:46 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:47:46 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 03:47:46 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 03:47:47 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:47:47 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:47:47 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:47:47 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:47:47 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 03:47:47 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 03:47:48 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:47:48 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:47:48 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:47:48 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:47:48 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 03:47:48 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 03:47:49 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:47:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:47:49 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:47:49 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:47:49 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 03:47:49 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 03:47:50 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 03:47:50 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 03:47:51 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 03:47:51 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 03:47:52 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 03:47:52 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 03:47:53 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 03:47:53 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 03:47:54 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 03:47:54 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 03:47:55 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-27 03:47:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:47:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:47:55 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:47:55 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:47:55 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:47:55 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:47:55 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:47:55 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:47:55 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:47:55 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:47:55 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:47:55 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:47:55 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:47:55 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:47:55 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 03:47:55 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2355 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:47:55 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2355 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:47:55 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2355 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:47:55 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2355 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:47:55 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2355 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:47:55 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2355 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:47:55 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2355 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:48:00 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:48:00 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:48:00 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:48:00 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:48:00 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:48:00 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:48:00 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:48:00 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:48:00 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:48:00 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:48:00 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 03:48:00 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 03:48:00 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 03:48:00 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:48:00 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:48:00 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:48:00 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 03:48:00 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:48:00 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 03:48:00 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 03:48:00 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 03:48:00 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:48:00 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:48:00 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:48:00 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 03:48:00 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:48:00 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 03:48:00 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 03:48:00 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 03:48:00 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:48:00 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:48:00 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:48:00 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 03:48:00 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:48:00 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 03:48:00 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 03:48:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 03:48:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 03:48:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 03:48:00 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 03:48:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 03:48:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 03:48:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 03:48:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:48:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 03:48:00 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 03:48:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:48:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:48:00 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 03:48:00 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 03:48:00 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 03:48:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:48:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:48:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:48:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 03:48:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:48:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:48:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:48:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:48:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:48:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:48:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:48:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:48:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:48:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:48:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:48:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:48:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:48:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:48:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:48:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:48:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:48:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:48:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:48:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:48:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:48:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:48:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:48:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:48:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:48:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:48:00 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 03:48:00 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 03:48:00 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 03:48:00 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 03:48:00 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 03:48:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:48:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:48:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:48:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:48:00 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 03:48:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:48:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:48:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:48:00 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:48:00 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:48:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:48:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:48:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:48:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:48:00 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 03:48:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:48:01 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 03:48:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:48:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:48:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:48:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:48:01 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 03:48:01 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 03:48:02 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 03:48:02 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:48:02 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:48:02 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:48:02 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:48:02 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 03:48:02 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 03:48:03 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:48:03 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:48:03 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:48:03 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:48:03 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 03:48:03 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 03:48:04 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:48:04 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:48:04 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:48:04 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:48:04 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 03:48:04 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 03:48:05 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:48:05 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:48:05 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:48:05 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:48:05 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 03:48:05 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 03:48:06 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 03:48:06 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 03:48:07 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 03:48:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:48:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:48:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:48:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:48:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:48:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:48:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:48:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:48:07 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:48:07 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:48:07 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:48:07 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:48:07 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:48:07 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:48:07 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 03:48:07 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1561 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:48:07 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1561 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:48:07 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1561 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:48:07 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1561 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:48:07 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1561 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:48:07 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1561 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:48:12 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:48:12 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:48:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:48:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:48:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:48:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:48:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:48:12 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:48:12 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:48:12 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:48:12 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 03:48:12 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 03:48:12 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 03:48:12 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:48:12 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:48:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:48:12 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 03:48:12 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:48:12 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 03:48:12 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 03:48:12 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 03:48:12 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:48:12 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:48:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:48:12 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 03:48:12 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:48:12 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 03:48:12 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 03:48:12 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 03:48:12 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:48:12 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:48:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:48:12 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 03:48:12 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:48:12 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 03:48:12 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 03:48:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 03:48:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 03:48:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 03:48:12 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 03:48:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 03:48:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 03:48:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 03:48:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:48:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 03:48:12 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 03:48:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:48:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:48:12 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 03:48:12 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 03:48:12 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 03:48:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:48:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:48:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:48:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 03:48:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:48:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:48:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:48:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:48:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:48:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:48:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:48:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:48:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:48:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:48:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:48:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:48:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:48:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:48:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:48:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:48:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:48:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:48:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:48:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:48:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:48:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:48:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:48:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:48:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:48:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:48:12 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 03:48:12 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 03:48:12 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 03:48:12 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 03:48:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:48:12 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 03:48:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:48:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:48:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:48:12 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 03:48:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:48:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:48:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:48:12 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:48:12 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:48:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:48:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:48:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:48:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:48:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:48:13 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 03:48:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:48:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:48:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:48:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:48:13 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 03:48:14 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 03:48:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:48:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:48:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:48:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:48:14 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 03:48:15 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 03:48:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:48:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:48:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:48:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:48:15 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 03:48:16 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 03:48:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:48:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:48:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:48:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:48:16 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 03:48:17 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 03:48:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:48:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:48:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:48:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:48:17 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 03:48:18 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 03:48:18 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 03:48:19 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 03:48:19 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 03:48:20 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 03:48:20 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 03:48:20 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 03:48:21 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 03:48:21 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 03:48:22 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 03:48:22 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 03:48:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:48:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:48:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:48:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:48:23 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:48:23 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:48:23 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:48:23 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:48:23 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:48:23 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:48:23 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:48:23 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:48:23 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:48:23 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 03:48:23 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:48:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2276 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:48:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2276 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:48:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2276 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:48:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2276 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:48:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2276 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:48:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2276 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:48:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2277 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:48:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2277 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:48:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2277 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:48:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2277 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:48:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2277 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:48:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2277 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:48:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2277 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:48:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2277 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:48:28 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:48:28 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:48:28 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:48:28 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:48:28 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:48:28 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:48:28 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:48:28 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:48:28 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:48:28 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:48:28 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 03:48:28 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 03:48:28 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 03:48:28 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:48:28 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:48:28 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:48:28 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 03:48:28 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:48:28 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 03:48:28 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 03:48:28 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 03:48:28 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:48:28 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:48:28 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:48:28 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 03:48:28 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:48:28 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 03:48:28 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 03:48:28 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 03:48:28 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:48:28 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:48:28 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:48:28 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 03:48:28 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:48:28 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 03:48:28 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 03:48:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 03:48:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 03:48:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 03:48:28 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 03:48:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 03:48:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 03:48:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 03:48:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 03:48:28 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 03:48:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:48:28 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 03:48:28 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 03:48:28 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 03:48:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:48:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:48:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:48:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 03:48:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:48:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:48:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:48:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:48:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:48:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:48:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:48:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:48:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:48:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:48:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:48:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:48:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:48:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:48:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:48:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:48:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:48:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:48:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:48:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:48:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:48:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:48:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:48:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:48:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:48:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:48:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:48:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:48:28 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 03:48:28 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 03:48:28 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 03:48:28 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 03:48:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:48:28 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 03:48:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:48:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:48:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:48:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:48:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:48:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:48:28 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:48:28 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:48:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:48:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:48:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:48:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:48:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:48:29 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 03:48:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:48:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:48:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:48:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:48:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:48:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:48:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:48:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:48:29 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:48:29 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:48:29 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:48:29 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:48:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:48:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:48:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:48:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:48:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:48:29 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:48:29 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:48:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:48:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:48:29 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 03:48:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:48:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:48:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:48:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:48:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:48:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:48:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:48:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:48:29 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:48:29 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:48:29 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:48:29 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:48:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:48:29 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:48:29 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:48:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:48:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:48:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:48:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:48:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:48:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:48:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:48:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:48:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:48:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:48:29 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:48:29 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:48:29 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:48:29 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:48:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:48:29 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:48:29 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:48:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:48:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:48:29 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 03:48:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:48:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:48:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:48:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:48:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:48:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:48:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:48:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:48:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:48:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:48:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:48:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:48:30 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:48:30 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:48:30 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:48:30 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:48:30 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:48:30 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:48:30 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 03:48:30 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=497 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:48:30 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=497 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:48:30 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=497 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:48:30 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=497 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:48:30 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=497 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:48:30 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=497 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:48:30 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=497 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:48:35 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:48:35 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:48:35 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:48:35 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:48:35 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:48:35 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:48:35 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:48:35 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:48:35 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:48:35 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:48:35 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 03:48:35 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 03:48:35 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 03:48:35 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:48:35 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:48:35 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:48:35 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 03:48:35 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:48:35 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 03:48:35 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 03:48:35 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 03:48:35 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:48:35 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:48:35 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:48:35 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 03:48:35 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:48:35 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 03:48:35 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 03:48:35 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 03:48:35 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:48:35 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:48:35 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:48:35 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 03:48:35 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:48:35 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 03:48:35 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 03:48:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 03:48:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 03:48:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 03:48:35 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 03:48:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 03:48:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 03:48:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 03:48:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:48:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 03:48:35 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 03:48:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:48:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:48:35 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 03:48:35 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 03:48:35 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 03:48:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:48:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:48:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:48:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 03:48:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:48:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:48:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:48:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:48:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:48:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:48:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:48:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:48:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:48:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:48:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:48:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:48:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:48:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:48:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:48:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:48:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:48:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:48:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:48:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:48:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:48:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:48:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:48:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:48:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:48:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:48:35 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 03:48:35 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 03:48:35 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 03:48:35 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 03:48:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:48:35 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 03:48:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:48:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:48:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:48:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:48:35 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:48:35 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:48:35 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:48:35 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:48:35 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 03:48:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:48:35 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:48:35 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:48:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:48:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:48:36 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 03:48:36 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:48:36 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:48:36 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:48:36 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:48:36 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 03:48:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:48:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:48:36 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:48:36 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:48:36 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:48:36 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:48:36 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:48:36 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:48:36 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:48:36 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:48:36 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:48:36 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:48:36 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 03:48:36 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=315 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:48:36 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:48:36 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:48:41 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:48:41 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:48:41 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:48:41 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:48:41 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:48:41 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:48:41 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:48:41 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:48:41 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:48:41 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:48:41 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 03:48:41 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 03:48:41 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 03:48:41 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:48:41 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:48:41 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:48:41 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 03:48:41 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:48:41 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 03:48:41 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 03:48:41 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 03:48:41 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:48:41 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:48:41 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:48:41 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 03:48:41 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:48:41 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 03:48:41 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 03:48:41 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 03:48:41 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:48:41 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:48:41 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:48:41 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 03:48:41 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:48:41 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 03:48:41 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 03:48:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 03:48:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 03:48:41 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 03:48:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 03:48:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 03:48:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 03:48:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 03:48:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 03:48:41 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 03:48:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:48:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:48:41 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 03:48:41 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 03:48:41 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 03:48:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:48:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:48:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:48:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 03:48:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:48:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:48:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:48:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:48:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:48:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:48:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:48:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:48:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:48:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:48:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:48:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:48:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:48:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:48:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:48:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:48:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:48:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:48:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:48:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:48:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:48:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:48:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:48:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:48:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:48:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:48:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:48:41 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 03:48:42 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 03:48:42 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 03:48:42 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 03:48:42 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 03:48:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:48:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:48:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:48:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:48:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:48:42 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:48:42 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:48:42 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:48:42 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:48:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:48:42 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:48:42 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:48:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:48:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:48:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:48:42 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 03:48:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:48:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:48:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:48:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:48:43 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 03:48:43 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 03:48:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:48:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:48:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:48:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:48:44 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 03:48:44 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 03:48:44 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:48:44 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:48:44 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:48:44 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:48:45 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 03:48:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:48:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:48:45 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:48:45 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:48:45 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:48:45 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:48:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:48:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:48:45 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:48:45 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:48:45 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:48:45 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:48:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:48:45 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:48:45 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:48:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:48:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:48:45 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 03:48:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:48:45 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:48:45 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:48:45 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:48:45 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:48:46 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 03:48:46 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 03:48:46 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:48:46 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:48:46 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:48:46 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:48:47 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 03:48:47 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 03:48:48 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 03:48:48 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 03:48:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:48:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:48:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:48:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:48:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:48:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:48:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:48:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:48:48 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:48:48 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:48:48 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:48:48 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:48:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:48:48 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:48:48 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:48:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:48:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:48:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:48:49 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 03:48:49 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 03:48:49 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 03:48:50 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 03:48:50 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 03:48:51 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 03:48:51 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 03:48:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:48:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:48:52 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:48:52 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:48:52 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:48:52 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:48:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:48:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:48:52 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:48:52 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:48:52 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:48:52 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:48:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:48:52 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:48:52 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:48:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:48:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:48:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:48:52 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 03:48:52 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-27 03:48:53 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-27 03:48:53 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-27 03:48:54 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-27 03:48:54 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-27 03:48:55 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-27 03:48:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:48:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:48:55 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:48:55 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:48:55 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:48:55 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:48:55 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:48:55 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:48:55 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:48:55 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:48:55 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:48:55 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:48:55 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 03:48:55 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:48:55 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:48:55 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2873 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:48:55 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2873 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:48:55 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2873 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:48:55 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2873 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:48:55 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2873 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:48:55 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2873 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:48:55 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2873 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:49:00 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:49:00 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:49:00 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:49:00 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:49:00 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:49:00 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:49:00 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:49:00 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:49:00 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:49:00 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:49:00 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 03:49:00 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 03:49:00 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 03:49:00 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:49:00 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:49:00 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:49:00 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 03:49:00 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:49:00 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 03:49:00 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 03:49:00 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 03:49:00 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:49:00 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:49:00 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:49:00 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 03:49:00 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:49:00 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 03:49:00 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 03:49:00 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 03:49:00 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:49:00 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:49:00 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:49:00 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 03:49:00 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:49:00 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 03:49:00 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 03:49:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 03:49:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 03:49:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 03:49:00 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 03:49:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 03:49:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 03:49:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 03:49:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 03:49:00 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 03:49:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:49:00 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 03:49:00 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 03:49:00 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 03:49:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:49:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:49:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:49:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 03:49:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:49:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:49:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:49:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:49:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:49:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:49:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:49:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:49:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:49:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:49:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:49:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:49:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:49:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:49:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:49:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:49:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:49:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:49:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:49:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:49:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:49:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:49:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:49:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:49:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:49:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:49:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:49:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:49:00 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 03:49:00 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 03:49:00 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 03:49:00 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 03:49:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:49:00 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 03:49:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:49:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:49:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:49:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:49:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:49:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:49:00 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:49:00 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:49:01 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 03:49:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:49:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:49:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:49:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:49:01 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 03:49:02 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 03:49:02 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:49:02 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:49:02 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:49:02 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:49:02 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 03:49:03 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 03:49:03 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:49:03 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:49:03 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:49:03 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:49:03 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 03:49:04 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 03:49:04 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:49:04 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:49:04 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:49:04 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:49:04 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 03:49:05 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 03:49:05 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:49:05 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:49:05 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:49:05 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:49:05 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 03:49:06 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 03:49:06 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 03:49:07 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 03:49:07 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 03:49:07 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 03:49:08 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 03:49:08 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 03:49:09 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 03:49:09 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 03:49:10 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 03:49:10 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 03:49:11 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-27 03:49:11 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-27 03:49:12 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-27 03:49:12 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-27 03:49:13 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-27 03:49:13 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-27 03:49:14 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-27 03:49:14 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-27 03:49:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:49:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:49:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:49:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:49:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:49:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:49:14 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:49:14 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:49:14 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:49:14 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:49:14 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:49:14 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:49:14 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 03:49:14 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3130 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:49:14 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3130 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:49:14 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3130 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:49:14 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3130 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:49:14 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3130 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:49:14 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3130 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:49:15 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3130 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:49:19 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:49:20 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:49:20 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:49:20 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:49:20 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:49:20 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:49:20 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:49:20 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:49:20 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:49:20 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:49:20 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 03:49:20 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 03:49:20 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 03:49:20 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:49:20 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:49:20 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:49:20 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 03:49:20 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:49:20 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 03:49:20 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 03:49:20 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 03:49:20 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:49:20 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:49:20 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:49:20 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 03:49:20 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:49:20 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 03:49:20 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 03:49:20 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 03:49:20 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:49:20 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:49:20 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:49:20 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 03:49:20 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:49:20 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 03:49:20 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 03:49:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 03:49:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 03:49:20 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 03:49:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 03:49:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 03:49:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 03:49:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 03:49:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 03:49:20 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 03:49:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:49:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:49:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:49:20 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 03:49:20 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 03:49:20 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 03:49:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:49:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:49:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:49:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 03:49:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:49:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:49:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:49:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:49:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:49:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:49:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:49:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:49:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:49:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:49:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:49:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:49:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:49:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:49:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:49:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:49:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:49:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:49:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:49:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:49:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:49:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:49:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:49:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:49:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:49:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:49:20 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 03:49:20 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 03:49:20 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 03:49:20 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 03:49:20 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 03:49:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:49:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:49:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:49:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:49:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:49:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:49:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:49:20 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:49:20 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:49:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:49:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:49:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:49:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:49:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:49:21 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 03:49:21 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:49:21 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:49:21 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:49:21 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:49:21 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 03:49:21 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 03:49:22 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:49:22 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:49:22 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:49:22 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:49:22 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 03:49:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:49:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:49:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:49:22 [WARNING] transceiver.py:250 (MS@172.18.127.22:6700) RX TRXD message (fn=547 tn=6 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:49:22 [WARNING] transceiver.py:250 (MS@172.18.127.22:6700) RX TRXD message (fn=547 tn=7 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:49:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:49:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:49:22 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:49:22 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:49:22 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:49:22 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:49:22 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 03:49:23 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:49:23 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:49:23 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:49:23 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:49:23 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 03:49:23 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 03:49:24 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:49:24 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:49:24 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:49:24 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:49:24 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 03:49:24 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 03:49:25 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:49:25 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:49:25 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:49:25 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:49:25 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 03:49:25 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 03:49:26 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 03:49:26 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 03:49:27 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 03:49:27 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 03:49:28 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 03:49:28 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 03:49:29 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 03:49:29 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 03:49:30 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 03:49:30 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 03:49:31 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-27 03:49:31 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-27 03:49:32 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-27 03:49:32 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-27 03:49:32 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-27 03:49:33 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-27 03:49:33 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-27 03:49:34 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-27 03:49:34 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-27 03:49:35 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-27 03:49:35 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-27 03:49:36 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-27 03:49:36 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-27 03:49:37 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-27 03:49:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:49:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:49:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:49:37 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:49:37 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:49:37 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:49:37 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:49:37 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:49:37 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:49:37 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:49:37 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:49:37 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:49:37 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:49:37 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 03:49:42 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:49:42 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:49:42 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:49:42 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:49:42 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:49:42 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:49:42 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:49:42 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:49:42 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:49:42 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:49:42 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 03:49:42 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 03:49:42 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 03:49:42 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:49:42 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:49:42 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:49:42 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 03:49:42 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:49:42 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 03:49:42 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 03:49:42 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 03:49:42 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:49:42 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:49:42 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:49:42 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 03:49:42 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:49:42 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 03:49:42 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 03:49:42 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 03:49:42 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:49:42 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:49:42 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:49:42 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 03:49:42 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:49:42 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 03:49:42 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 03:49:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 03:49:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 03:49:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 03:49:42 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 03:49:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 03:49:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 03:49:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 03:49:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:49:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 03:49:42 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 03:49:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:49:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:49:42 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 03:49:42 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 03:49:42 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 03:49:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:49:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:49:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:49:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 03:49:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:49:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:49:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:49:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:49:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:49:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:49:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:49:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:49:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:49:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:49:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:49:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:49:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:49:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:49:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:49:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:49:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:49:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:49:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:49:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:49:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:49:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:49:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:49:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:49:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:49:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:49:42 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 03:49:43 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 03:49:43 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 03:49:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:49:43 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 03:49:43 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 03:49:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:49:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:49:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:49:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:49:43 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:49:43 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:49:43 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:49:43 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:49:43 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 03:49:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:49:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:49:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:49:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:49:44 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 03:49:44 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 03:49:44 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:49:44 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:49:44 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:49:44 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:49:44 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 03:49:45 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 03:49:45 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:49:45 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:49:45 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:49:45 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:49:45 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 03:49:46 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 03:49:46 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:49:46 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:49:46 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:49:46 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:49:46 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 03:49:47 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 03:49:47 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:49:47 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:49:47 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:49:47 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:49:47 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 03:49:48 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 03:49:48 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 03:49:49 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 03:49:49 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 03:49:50 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 03:49:50 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 03:49:51 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 03:49:51 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 03:49:52 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 03:49:52 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 03:49:53 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 03:49:53 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-27 03:49:53 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-27 03:49:54 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-27 03:49:54 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-27 03:49:55 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-27 03:49:55 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-27 03:49:56 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-27 03:49:56 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-27 03:49:57 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-27 03:49:57 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-27 03:49:58 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-27 03:49:58 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-27 03:49:59 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-27 03:49:59 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-27 03:50:00 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-27 03:50:00 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-27 03:50:01 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2025-04-27 03:50:01 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2025-04-27 03:50:02 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2025-04-27 03:50:02 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2025-04-27 03:50:03 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2025-04-27 03:50:03 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2025-04-27 03:50:04 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2025-04-27 03:50:04 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2025-04-27 03:50:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:50:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:50:04 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:50:04 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:50:04 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:50:04 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:50:04 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:50:04 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:50:04 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:50:04 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:50:04 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 03:50:04 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:50:04 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:50:04 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4718 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:50:04 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4718 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:50:04 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4718 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:50:04 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4718 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:50:04 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4718 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:50:04 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4718 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:50:09 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:50:09 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:50:09 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:50:09 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:50:09 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:50:09 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:50:09 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:50:09 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:50:09 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:50:09 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:50:09 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 03:50:09 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 03:50:09 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 03:50:09 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:50:09 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:50:09 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:50:09 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 03:50:09 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:50:09 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 03:50:09 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 03:50:09 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 03:50:09 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:50:09 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:50:09 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:50:09 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 03:50:09 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:50:09 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 03:50:09 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 03:50:09 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 03:50:09 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:50:09 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:50:09 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:50:09 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 03:50:09 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:50:09 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 03:50:09 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 03:50:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 03:50:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 03:50:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 03:50:09 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 03:50:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 03:50:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 03:50:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 03:50:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 03:50:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:50:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:50:09 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 03:50:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:50:09 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 03:50:09 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 03:50:09 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 03:50:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:50:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:50:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:50:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 03:50:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:50:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:50:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:50:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:50:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:50:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:50:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:50:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:50:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:50:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:50:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:50:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:50:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:50:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:50:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:50:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:50:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:50:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:50:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:50:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:50:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:50:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:50:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:50:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:50:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:50:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:50:09 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 03:50:10 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 03:50:10 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 03:50:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:50:10 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 03:50:10 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 03:50:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:50:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:50:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:50:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:50:10 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:50:10 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:50:10 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:50:10 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:50:10 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 03:50:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:50:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:50:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:50:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:50:11 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 03:50:11 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 03:50:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:50:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:50:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:50:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:50:12 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 03:50:12 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 03:50:12 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:50:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:50:12 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:50:12 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:50:12 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 03:50:13 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 03:50:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:50:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:50:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:50:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:50:13 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 03:50:14 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 03:50:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:50:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:50:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:50:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:50:14 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 03:50:15 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 03:50:15 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 03:50:16 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 03:50:16 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 03:50:17 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 03:50:17 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 03:50:18 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 03:50:18 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 03:50:19 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 03:50:19 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 03:50:20 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 03:50:20 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-27 03:50:21 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-27 03:50:21 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-27 03:50:22 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-27 03:50:22 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-27 03:50:22 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-27 03:50:23 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-27 03:50:23 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-27 03:50:24 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-27 03:50:24 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-27 03:50:25 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-27 03:50:25 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-27 03:50:26 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-27 03:50:26 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-27 03:50:27 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-27 03:50:27 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-27 03:50:28 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2025-04-27 03:50:28 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2025-04-27 03:50:29 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2025-04-27 03:50:29 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2025-04-27 03:50:30 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2025-04-27 03:50:30 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2025-04-27 03:50:31 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2025-04-27 03:50:31 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2025-04-27 03:50:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:50:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:50:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:50:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:50:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:50:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:50:31 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:50:31 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:50:31 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:50:31 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:50:31 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:50:31 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:50:31 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 03:50:36 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:50:36 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:50:36 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:50:36 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:50:36 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:50:36 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:50:36 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:50:36 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:50:36 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:50:36 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:50:36 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 03:50:36 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 03:50:36 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 03:50:36 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:50:36 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:50:36 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:50:36 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 03:50:36 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:50:36 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 03:50:36 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 03:50:36 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 03:50:36 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:50:36 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:50:36 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:50:36 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 03:50:36 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:50:36 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 03:50:36 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 03:50:36 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 03:50:36 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:50:36 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:50:36 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:50:36 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 03:50:36 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:50:36 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 03:50:36 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 03:50:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 03:50:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 03:50:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 03:50:36 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 03:50:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 03:50:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 03:50:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 03:50:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:50:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 03:50:36 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 03:50:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:50:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:50:36 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 03:50:36 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 03:50:36 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 03:50:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:50:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:50:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:50:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 03:50:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:50:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:50:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:50:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:50:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:50:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:50:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:50:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:50:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:50:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:50:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:50:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:50:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:50:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:50:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:50:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:50:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:50:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:50:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:50:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:50:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:50:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:50:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:50:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:50:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:50:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:50:36 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 03:50:37 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 03:50:37 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 03:50:37 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 03:50:37 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 03:50:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:50:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:50:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:50:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:50:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:50:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:50:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:50:37 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:50:37 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:50:37 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 03:50:37 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:50:37 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:50:37 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:50:37 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:50:38 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 03:50:38 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 03:50:38 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:50:38 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:50:38 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:50:38 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:50:39 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 03:50:39 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 03:50:39 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:50:39 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:50:39 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:50:39 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:50:40 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 03:50:40 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 03:50:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:50:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:50:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:50:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:50:40 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 03:50:41 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 03:50:41 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:50:41 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:50:41 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:50:41 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:50:41 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 03:50:42 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 03:50:42 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 03:50:43 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 03:50:43 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 03:50:44 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 03:50:44 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 03:50:45 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 03:50:45 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 03:50:46 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 03:50:46 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 03:50:47 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 03:50:47 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-27 03:50:48 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-27 03:50:48 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-27 03:50:49 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-27 03:50:49 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-27 03:50:50 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-27 03:50:50 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-27 03:50:51 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-27 03:50:51 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-27 03:50:51 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-27 03:50:52 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-27 03:50:52 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-27 03:50:53 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-27 03:50:53 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-27 03:50:54 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-27 03:50:54 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-27 03:50:55 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2025-04-27 03:50:55 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2025-04-27 03:50:56 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2025-04-27 03:50:56 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2025-04-27 03:50:57 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2025-04-27 03:50:57 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2025-04-27 03:50:58 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2025-04-27 03:50:58 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2025-04-27 03:50:59 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2025-04-27 03:50:59 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2025-04-27 03:51:00 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2025-04-27 03:51:00 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2025-04-27 03:51:01 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2025-04-27 03:51:01 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2025-04-27 03:51:01 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2025-04-27 03:51:02 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2025-04-27 03:51:02 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2025-04-27 03:51:03 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2025-04-27 03:51:03 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2025-04-27 03:51:04 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2025-04-27 03:51:04 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2025-04-27 03:51:05 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2025-04-27 03:51:05 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2025-04-27 03:51:06 [DEBUG] clck_gen.py:102 IND CLOCK 6324
2025-04-27 03:51:06 [DEBUG] clck_gen.py:102 IND CLOCK 6426
2025-04-27 03:51:07 [DEBUG] clck_gen.py:102 IND CLOCK 6528
2025-04-27 03:51:07 [DEBUG] clck_gen.py:102 IND CLOCK 6630
2025-04-27 03:51:08 [DEBUG] clck_gen.py:102 IND CLOCK 6732
2025-04-27 03:51:08 [DEBUG] clck_gen.py:102 IND CLOCK 6834
2025-04-27 03:51:09 [DEBUG] clck_gen.py:102 IND CLOCK 6936
2025-04-27 03:51:09 [DEBUG] clck_gen.py:102 IND CLOCK 7038
2025-04-27 03:51:10 [DEBUG] clck_gen.py:102 IND CLOCK 7140
2025-04-27 03:51:10 [DEBUG] clck_gen.py:102 IND CLOCK 7242
2025-04-27 03:51:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:51:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:51:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:51:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:51:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:51:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:51:10 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:51:10 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:51:10 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:51:10 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:51:10 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:51:10 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 03:51:10 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:51:15 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:51:15 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:51:15 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:51:15 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:51:15 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:51:15 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:51:15 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:51:15 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:51:15 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:51:15 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:51:15 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 03:51:15 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 03:51:15 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 03:51:15 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:51:15 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:51:15 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:51:15 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 03:51:15 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:51:15 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 03:51:15 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 03:51:15 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 03:51:15 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:51:15 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:51:15 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:51:15 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 03:51:15 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:51:15 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 03:51:15 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 03:51:15 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 03:51:15 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:51:15 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:51:15 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:51:15 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 03:51:15 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:51:15 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 03:51:15 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 03:51:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 03:51:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 03:51:15 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 03:51:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 03:51:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 03:51:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 03:51:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 03:51:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 03:51:15 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 03:51:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:51:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:51:15 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 03:51:15 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 03:51:15 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 03:51:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:51:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:51:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:51:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 03:51:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:51:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:51:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:51:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:51:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:51:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:51:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:51:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:51:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:51:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:51:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:51:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:51:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:51:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:51:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:51:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:51:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:51:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:51:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:51:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:51:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:51:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:51:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:51:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:51:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:51:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:51:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:51:15 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 03:51:16 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 03:51:16 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 03:51:16 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 03:51:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:51:16 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 03:51:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:51:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:51:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:51:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:51:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:51:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:51:16 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:51:16 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:51:16 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 03:51:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:51:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:51:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:51:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:51:17 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 03:51:17 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 03:51:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:51:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:51:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:51:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:51:18 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 03:51:18 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 03:51:18 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:51:18 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:51:18 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:51:18 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:51:19 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 03:51:19 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 03:51:19 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:51:19 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:51:19 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:51:19 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:51:20 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 03:51:20 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 03:51:20 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:51:20 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:51:20 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:51:20 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:51:21 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 03:51:21 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 03:51:22 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 03:51:22 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 03:51:22 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 03:51:23 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 03:51:23 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 03:51:24 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 03:51:24 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 03:51:25 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 03:51:25 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 03:51:26 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 03:51:26 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-27 03:51:27 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-27 03:51:27 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-27 03:51:28 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-27 03:51:28 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-27 03:51:29 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-27 03:51:29 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-27 03:51:30 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-27 03:51:30 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-27 03:51:31 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-27 03:51:31 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-27 03:51:31 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-27 03:51:32 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-27 03:51:32 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-27 03:51:33 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-27 03:51:33 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-27 03:51:34 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2025-04-27 03:51:34 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2025-04-27 03:51:35 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2025-04-27 03:51:35 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2025-04-27 03:51:36 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2025-04-27 03:51:36 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2025-04-27 03:51:37 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2025-04-27 03:51:37 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2025-04-27 03:51:38 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2025-04-27 03:51:38 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2025-04-27 03:51:39 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2025-04-27 03:51:39 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2025-04-27 03:51:40 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2025-04-27 03:51:40 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2025-04-27 03:51:41 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2025-04-27 03:51:41 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2025-04-27 03:51:41 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2025-04-27 03:51:42 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2025-04-27 03:51:42 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2025-04-27 03:51:43 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2025-04-27 03:51:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:51:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:51:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:51:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:51:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:51:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:51:43 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:51:43 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:51:43 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:51:43 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:51:43 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:51:43 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 03:51:43 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=6009 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:51:43 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:51:43 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=6009 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:51:43 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=6009 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:51:43 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=6009 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:51:43 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=6009 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:51:43 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=6010 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:51:43 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=6010 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:51:43 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=6010 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:51:43 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=6010 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:51:43 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=6010 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:51:43 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=6010 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:51:43 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=6010 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:51:43 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=6010 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:51:48 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:51:48 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:51:48 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:51:48 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:51:48 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:51:48 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:51:48 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:51:48 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:51:48 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:51:48 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:51:48 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 03:51:48 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 03:51:48 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 03:51:48 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:51:48 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:51:48 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:51:48 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 03:51:48 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:51:48 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 03:51:48 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 03:51:48 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 03:51:48 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:51:48 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:51:48 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:51:48 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 03:51:48 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:51:48 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 03:51:48 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 03:51:48 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 03:51:48 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:51:48 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:51:48 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:51:48 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 03:51:48 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:51:48 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 03:51:48 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 03:51:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 03:51:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 03:51:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 03:51:48 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 03:51:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 03:51:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 03:51:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 03:51:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:51:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 03:51:48 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 03:51:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:51:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:51:48 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 03:51:48 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 03:51:48 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 03:51:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:51:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:51:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:51:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 03:51:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:51:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:51:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:51:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:51:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:51:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:51:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:51:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:51:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:51:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:51:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:51:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:51:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:51:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:51:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:51:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:51:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:51:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:51:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:51:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:51:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:51:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:51:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:51:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:51:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:51:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:51:48 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 03:51:49 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 03:51:49 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 03:51:49 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 03:51:49 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 03:51:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:51:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:51:49 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:51:49 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:51:49 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:51:49 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:51:49 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:51:49 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:51:49 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:51:49 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:51:49 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:51:49 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 03:51:49 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=123 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:51:49 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=123 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:51:49 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=123 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:51:49 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=123 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:51:49 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=123 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:51:49 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=123 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:51:49 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=123 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:51:49 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=123 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:51:54 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:51:54 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:51:54 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:51:54 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:51:54 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:51:54 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:51:54 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:51:54 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:51:54 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:51:54 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:51:54 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 03:51:54 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 03:51:54 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 03:51:54 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:51:54 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:51:54 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:51:54 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 03:51:54 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:51:54 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 03:51:54 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 03:51:54 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 03:51:54 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:51:54 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:51:54 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:51:54 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 03:51:54 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:51:54 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 03:51:54 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 03:51:54 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 03:51:54 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:51:54 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:51:54 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:51:54 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 03:51:54 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:51:54 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 03:51:54 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 03:51:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 03:51:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 03:51:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 03:51:54 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 03:51:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 03:51:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 03:51:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 03:51:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 03:51:54 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 03:51:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:51:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:51:54 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 03:51:54 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 03:51:54 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 03:51:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:51:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:51:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:51:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 03:51:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:51:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:51:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:51:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:51:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:51:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:51:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:51:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:51:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:51:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:51:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:51:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:51:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:51:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:51:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:51:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:51:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:51:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:51:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:51:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:51:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:51:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:51:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:51:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:51:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:51:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:51:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:51:54 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 03:51:54 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 03:51:54 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 03:51:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:51:54 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 03:51:54 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 03:51:55 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:51:55 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:51:55 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:51:55 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:51:55 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:51:55 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:51:55 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:51:55 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:51:55 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:51:55 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:51:55 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 03:52:00 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:52:00 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:52:00 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:52:00 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:52:00 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:52:00 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:52:00 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:52:00 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:52:00 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:52:00 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:52:00 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 03:52:00 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 03:52:00 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 03:52:00 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:52:00 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:52:00 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:52:00 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 03:52:00 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:52:00 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 03:52:00 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 03:52:00 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 03:52:00 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:52:00 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:52:00 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:52:00 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 03:52:00 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:52:00 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 03:52:00 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 03:52:00 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 03:52:00 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:52:00 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:52:00 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:52:00 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 03:52:00 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:52:00 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 03:52:00 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 03:52:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 03:52:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 03:52:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 03:52:00 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 03:52:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 03:52:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 03:52:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 03:52:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:52:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 03:52:00 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 03:52:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:52:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:52:00 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 03:52:00 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 03:52:00 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 03:52:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:52:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:52:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:52:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 03:52:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:52:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:52:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:52:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:52:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:52:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:52:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:52:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:52:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:52:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:52:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:52:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:52:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:52:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:52:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:52:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:52:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:52:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:52:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:52:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:52:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:52:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:52:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:52:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:52:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:52:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:52:00 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 03:52:00 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 03:52:00 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 03:52:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:52:00 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 03:52:00 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 03:52:00 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:52:00 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:52:00 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:52:00 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:52:00 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:52:00 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:52:00 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:52:00 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:52:00 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:52:00 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 03:52:00 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:52:00 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=123 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:52:00 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=123 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:52:00 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=123 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:52:00 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=123 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:52:00 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=123 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:52:00 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=123 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:52:00 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=123 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:52:00 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=123 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:52:05 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:52:05 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:52:05 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:52:05 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:52:05 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:52:05 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:52:05 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:52:05 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:52:05 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:52:05 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:52:05 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 03:52:05 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 03:52:05 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 03:52:05 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:52:05 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:52:05 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:52:05 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 03:52:05 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:52:05 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 03:52:05 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 03:52:05 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 03:52:05 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:52:05 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:52:05 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:52:05 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 03:52:05 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:52:05 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 03:52:05 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 03:52:05 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 03:52:05 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:52:05 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:52:05 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:52:05 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 03:52:05 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:52:05 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 03:52:05 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 03:52:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 03:52:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 03:52:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 03:52:05 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 03:52:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 03:52:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 03:52:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 03:52:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 03:52:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:52:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:52:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:52:05 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 03:52:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:52:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:52:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:52:05 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 03:52:05 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 03:52:05 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 03:52:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:52:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:52:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:52:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 03:52:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:52:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:52:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:52:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:52:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:52:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:52:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:52:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:52:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:52:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:52:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:52:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:52:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:52:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:52:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:52:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:52:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:52:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:52:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:52:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:52:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:52:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:52:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:52:05 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 03:52:06 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 03:52:06 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 03:52:06 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 03:52:06 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 03:52:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:52:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:52:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:52:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:52:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:52:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:52:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:52:06 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:52:06 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:52:06 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 03:52:06 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:52:06 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:52:06 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:52:06 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:52:07 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 03:52:07 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 03:52:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:52:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:52:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:52:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:52:08 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 03:52:08 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 03:52:08 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:52:08 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:52:08 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:52:08 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:52:09 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 03:52:09 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 03:52:09 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:52:09 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:52:09 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:52:09 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:52:09 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 03:52:10 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 03:52:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:52:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:52:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:52:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:52:10 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 03:52:11 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 03:52:11 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 03:52:12 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 03:52:12 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 03:52:13 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 03:52:13 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 03:52:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:52:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:52:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:52:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:52:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:52:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:52:14 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:52:14 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:52:14 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:52:14 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:52:14 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 03:52:14 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1832 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:52:14 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:52:14 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:52:14 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1832 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:52:14 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1832 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:52:14 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1832 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:52:14 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1832 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:52:14 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1833 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:52:14 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1833 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:52:14 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1833 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:52:14 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1833 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:52:14 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1833 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:52:14 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1833 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:52:14 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1833 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:52:14 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1833 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:52:19 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:52:19 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:52:19 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:52:19 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:52:19 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:52:19 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:52:19 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:52:19 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:52:19 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:52:19 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:52:19 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 03:52:19 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 03:52:19 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 03:52:19 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:52:19 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:52:19 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:52:19 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 03:52:19 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:52:19 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 03:52:19 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 03:52:19 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 03:52:19 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:52:19 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:52:19 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:52:19 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 03:52:19 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:52:19 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 03:52:19 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 03:52:19 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 03:52:19 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:52:19 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:52:19 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:52:19 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 03:52:19 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:52:19 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 03:52:19 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 03:52:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 03:52:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 03:52:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 03:52:19 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 03:52:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 03:52:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 03:52:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 03:52:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:52:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 03:52:19 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 03:52:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:52:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:52:19 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 03:52:19 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 03:52:19 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 03:52:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:52:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:52:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:52:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 03:52:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:52:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:52:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:52:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:52:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:52:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:52:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:52:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:52:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:52:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:52:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:52:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:52:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:52:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:52:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:52:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:52:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:52:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:52:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:52:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:52:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:52:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:52:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:52:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:52:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:52:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:52:19 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 03:52:19 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 03:52:19 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 03:52:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:52:19 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 03:52:19 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 03:52:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:52:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:52:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:52:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:52:19 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:52:19 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:52:19 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:52:19 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:52:20 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 03:52:20 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:52:20 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:52:20 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:52:20 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:52:20 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 03:52:21 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 03:52:21 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:52:21 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:52:21 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:52:21 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:52:21 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 03:52:22 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 03:52:22 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:52:22 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:52:22 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:52:22 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:52:22 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 03:52:23 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 03:52:23 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:52:23 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:52:23 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:52:23 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:52:23 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 03:52:24 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 03:52:24 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:52:24 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:52:24 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:52:24 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:52:24 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 03:52:25 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 03:52:25 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 03:52:26 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 03:52:26 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 03:52:26 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 03:52:27 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 03:52:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:52:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:52:27 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:52:27 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:52:27 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:52:27 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:52:27 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:52:27 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:52:27 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:52:27 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:52:27 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 03:52:27 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1823 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:52:27 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:52:27 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:52:27 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1823 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:52:27 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1823 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:52:27 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1823 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:52:27 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1823 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:52:27 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1824 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:52:27 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1824 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:52:27 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1824 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:52:27 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1824 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:52:27 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1824 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:52:27 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1824 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:52:27 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1824 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:52:27 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1824 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:52:32 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:52:32 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:52:32 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:52:32 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:52:32 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:52:32 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:52:32 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:52:32 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:52:32 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:52:32 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:52:32 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 03:52:32 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 03:52:32 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 03:52:32 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:52:32 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:52:32 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:52:32 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 03:52:32 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:52:32 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 03:52:32 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 03:52:32 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 03:52:32 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:52:32 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:52:32 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:52:32 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 03:52:32 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:52:32 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 03:52:32 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 03:52:32 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 03:52:32 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:52:32 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:52:32 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:52:32 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 03:52:32 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:52:32 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 03:52:32 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 03:52:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 03:52:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 03:52:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 03:52:32 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 03:52:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 03:52:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 03:52:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 03:52:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:52:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 03:52:32 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 03:52:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:52:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:52:32 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 03:52:32 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 03:52:32 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 03:52:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:52:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:52:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:52:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 03:52:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:52:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:52:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:52:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:52:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:52:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:52:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:52:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:52:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:52:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:52:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:52:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:52:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:52:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:52:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:52:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:52:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:52:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:52:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:52:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:52:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:52:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:52:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:52:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:52:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:52:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:52:32 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 03:52:33 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 03:52:33 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 03:52:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:52:33 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 03:52:33 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 03:52:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:52:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:52:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:52:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:52:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:52:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:52:33 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:52:33 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:52:33 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 03:52:33 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:52:33 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:52:33 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:52:33 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:52:34 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 03:52:34 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 03:52:34 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:52:34 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:52:34 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:52:34 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:52:35 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 03:52:35 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 03:52:35 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:52:35 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:52:35 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:52:35 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:52:36 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 03:52:36 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 03:52:36 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:52:36 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:52:36 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:52:36 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:52:37 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 03:52:37 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 03:52:37 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:52:37 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:52:37 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:52:37 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:52:38 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 03:52:38 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 03:52:39 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 03:52:39 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 03:52:40 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 03:52:40 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 03:52:40 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 03:52:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:52:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:52:41 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:52:41 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:52:41 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:52:41 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:52:41 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:52:41 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:52:41 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:52:41 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 03:52:41 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1832 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:52:41 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:52:41 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:52:41 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:52:41 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1832 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:52:41 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1832 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:52:41 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1832 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:52:41 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1832 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:52:46 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:52:46 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:52:46 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:52:46 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:52:46 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:52:46 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:52:46 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:52:46 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:52:46 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:52:46 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:52:46 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 03:52:46 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 03:52:46 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 03:52:46 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:52:46 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:52:46 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:52:46 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 03:52:46 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:52:46 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 03:52:46 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 03:52:46 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 03:52:46 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:52:46 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:52:46 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:52:46 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 03:52:46 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:52:46 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 03:52:46 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 03:52:46 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 03:52:46 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:52:46 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:52:46 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:52:46 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 03:52:46 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:52:46 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 03:52:46 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 03:52:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 03:52:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 03:52:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 03:52:46 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 03:52:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 03:52:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 03:52:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 03:52:46 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 03:52:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 03:52:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:52:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:52:46 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 03:52:46 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 03:52:46 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 03:52:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:52:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:52:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:52:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 03:52:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:52:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:52:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:52:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:52:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:52:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:52:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:52:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:52:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:52:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:52:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:52:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:52:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:52:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:52:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:52:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:52:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:52:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:52:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:52:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:52:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:52:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:52:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:52:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:52:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:52:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:52:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:52:46 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 03:52:46 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 03:52:46 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 03:52:46 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 03:52:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:52:46 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 03:52:46 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:52:46 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:52:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:52:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:52:46 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:52:46 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:52:46 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:52:46 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:52:47 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 03:52:47 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:52:47 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:52:47 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:52:47 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:52:47 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 03:52:48 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 03:52:48 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:52:48 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:52:48 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:52:48 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:52:48 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 03:52:49 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 03:52:49 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:52:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:52:49 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:52:49 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:52:49 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 03:52:50 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 03:52:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:52:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:52:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:52:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:52:50 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 03:52:51 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 03:52:51 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:52:51 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:52:51 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:52:51 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:52:51 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 03:52:52 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 03:52:52 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 03:52:53 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 03:52:53 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 03:52:54 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 03:52:54 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 03:52:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:52:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:52:54 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:52:54 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:52:54 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:52:54 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:52:54 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:52:54 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:52:54 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:52:54 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:52:55 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:52:55 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:52:55 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 03:52:55 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1832 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:52:55 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1832 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:52:55 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1833 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:52:55 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1833 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:52:55 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1833 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:52:55 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1833 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:52:55 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1833 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:52:55 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1833 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:52:55 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1833 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:52:55 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1833 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:52:59 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:52:59 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:52:59 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:52:59 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:52:59 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:52:59 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:53:00 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:53:00 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:53:00 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:53:00 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:53:00 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 03:53:00 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 03:53:00 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 03:53:00 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:53:00 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:53:00 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:53:00 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 03:53:00 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:53:00 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 03:53:00 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 03:53:00 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 03:53:00 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:53:00 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:53:00 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:53:00 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 03:53:00 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:53:00 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 03:53:00 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 03:53:00 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 03:53:00 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:53:00 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:53:00 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:53:00 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 03:53:00 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:53:00 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 03:53:00 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 03:53:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 03:53:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 03:53:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 03:53:00 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 03:53:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 03:53:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 03:53:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 03:53:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:53:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 03:53:00 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 03:53:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:53:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:53:00 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 03:53:00 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 03:53:00 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 03:53:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:53:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:53:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:53:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 03:53:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:53:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:53:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:53:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:53:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:53:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:53:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:53:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:53:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:53:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:53:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:53:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:53:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:53:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:53:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:53:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:53:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:53:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:53:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:53:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:53:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:53:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:53:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:53:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:53:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:53:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:53:00 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 03:53:00 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 03:53:00 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 03:53:00 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 03:53:00 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 03:53:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:53:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:53:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:53:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:53:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:53:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:53:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:53:00 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:53:00 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:53:00 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 03:53:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:53:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:53:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:53:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:53:01 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 03:53:01 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 03:53:02 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:53:02 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:53:02 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:53:02 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:53:02 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 03:53:02 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 03:53:03 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:53:03 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:53:03 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:53:03 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:53:03 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 03:53:03 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 03:53:04 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:53:04 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:53:04 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:53:04 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:53:04 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 03:53:04 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 03:53:05 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:53:05 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:53:05 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:53:05 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:53:05 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 03:53:05 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 03:53:06 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 03:53:06 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 03:53:07 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 03:53:07 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 03:53:08 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 03:53:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:53:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:53:08 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:53:08 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:53:08 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:53:08 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:53:08 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:53:08 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:53:08 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:53:08 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:53:08 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:53:08 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 03:53:08 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:53:13 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:53:13 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:53:13 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:53:13 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:53:13 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:53:13 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:53:13 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:53:13 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:53:13 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:53:13 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:53:13 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 03:53:13 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 03:53:13 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 03:53:13 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:53:13 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:53:13 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:53:13 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 03:53:13 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:53:13 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 03:53:13 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 03:53:13 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 03:53:13 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:53:13 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:53:13 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:53:13 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 03:53:13 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:53:13 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 03:53:13 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 03:53:13 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 03:53:13 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:53:13 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:53:13 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:53:13 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 03:53:13 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:53:13 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 03:53:13 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 03:53:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 03:53:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 03:53:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 03:53:13 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 03:53:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 03:53:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 03:53:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 03:53:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:53:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 03:53:13 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 03:53:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:53:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:53:13 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 03:53:13 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 03:53:13 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 03:53:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:53:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:53:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:53:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 03:53:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:53:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:53:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:53:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:53:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:53:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:53:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:53:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:53:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:53:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:53:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:53:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:53:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:53:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:53:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:53:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:53:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:53:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:53:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:53:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:53:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:53:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:53:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:53:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:53:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:53:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:53:13 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 03:53:14 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 03:53:14 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 03:53:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:53:14 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 03:53:14 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 03:53:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:53:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:53:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:53:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:53:14 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:53:14 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:53:14 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:53:14 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:53:14 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 03:53:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:53:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:53:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:53:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:53:15 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 03:53:15 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 03:53:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:53:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:53:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:53:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:53:16 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 03:53:16 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 03:53:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:53:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:53:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:53:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:53:16 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 03:53:17 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 03:53:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:53:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:53:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:53:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:53:17 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 03:53:18 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 03:53:18 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:53:18 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:53:18 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:53:18 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:53:18 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 03:53:19 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 03:53:19 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 03:53:20 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 03:53:20 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 03:53:21 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 03:53:21 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 03:53:22 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 03:53:22 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 03:53:23 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 03:53:23 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 03:53:24 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 03:53:24 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-27 03:53:25 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-27 03:53:25 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-27 03:53:26 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-27 03:53:26 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-27 03:53:26 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-27 03:53:27 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-27 03:53:27 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-27 03:53:28 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-27 03:53:28 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-27 03:53:29 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-27 03:53:29 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-27 03:53:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:53:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:53:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:53:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:53:30 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:53:30 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:53:30 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:53:30 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:53:30 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:53:30 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3533 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:53:30 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:53:30 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3533 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:53:30 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3533 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:53:30 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3533 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:53:30 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3533 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:53:30 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3533 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:53:30 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3534 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:53:30 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3534 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:53:30 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3534 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:53:30 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3534 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:53:30 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3534 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:53:30 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3534 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:53:30 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3534 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:53:30 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3534 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:53:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:53:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:53:30 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 03:53:35 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:53:35 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:53:35 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:53:35 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:53:35 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:53:35 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:53:35 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:53:35 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:53:35 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:53:35 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:53:35 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 03:53:35 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 03:53:35 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 03:53:35 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:53:35 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:53:35 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:53:35 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 03:53:35 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:53:35 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 03:53:35 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 03:53:35 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 03:53:35 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:53:35 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:53:35 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:53:35 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 03:53:35 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:53:35 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 03:53:35 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 03:53:35 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 03:53:35 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:53:35 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:53:35 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:53:35 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 03:53:35 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:53:35 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 03:53:35 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 03:53:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 03:53:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 03:53:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 03:53:35 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 03:53:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 03:53:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 03:53:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 03:53:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:53:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 03:53:35 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 03:53:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:53:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:53:35 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 03:53:35 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 03:53:35 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 03:53:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:53:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:53:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:53:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 03:53:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:53:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:53:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:53:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:53:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:53:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:53:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:53:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:53:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:53:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:53:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:53:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:53:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:53:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:53:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:53:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:53:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:53:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:53:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:53:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:53:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:53:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:53:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:53:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:53:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:53:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:53:35 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 03:53:35 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 03:53:35 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 03:53:35 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 03:53:35 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 03:53:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:53:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:53:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:53:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:53:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:53:35 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:53:35 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:53:35 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:53:35 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:53:36 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 03:53:36 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:53:36 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:53:36 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:53:36 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:53:36 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 03:53:37 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 03:53:37 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:53:37 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:53:37 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:53:37 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:53:37 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 03:53:38 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 03:53:38 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:53:38 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:53:38 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:53:38 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:53:38 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 03:53:39 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 03:53:39 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:53:39 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:53:39 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:53:39 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:53:39 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 03:53:39 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 03:53:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:53:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:53:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:53:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:53:40 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 03:53:40 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 03:53:41 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 03:53:41 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 03:53:42 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 03:53:42 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 03:53:43 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 03:53:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:53:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:53:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:53:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:53:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:53:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:53:43 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:53:43 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:53:43 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:53:43 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:53:43 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:53:43 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:53:43 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 03:53:43 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1831 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:53:43 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1831 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:53:43 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1831 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:53:43 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1831 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:53:43 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1831 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:53:43 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1831 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:53:43 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1831 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:53:48 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:53:48 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:53:48 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:53:48 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:53:48 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:53:48 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:53:48 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:53:48 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:53:48 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:53:48 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:53:48 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 03:53:48 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 03:53:48 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 03:53:48 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:53:48 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:53:48 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:53:48 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 03:53:48 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:53:48 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 03:53:48 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 03:53:48 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 03:53:48 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:53:48 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:53:48 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:53:48 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 03:53:48 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:53:48 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 03:53:48 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 03:53:48 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 03:53:48 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:53:48 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:53:48 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:53:48 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 03:53:48 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:53:48 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 03:53:48 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 03:53:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 03:53:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 03:53:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 03:53:48 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 03:53:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 03:53:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 03:53:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 03:53:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 03:53:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:53:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:53:48 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 03:53:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:53:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:53:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:53:48 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 03:53:48 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 03:53:48 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 03:53:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:53:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:53:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:53:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 03:53:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:53:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:53:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:53:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:53:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:53:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:53:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:53:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:53:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:53:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:53:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:53:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:53:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:53:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:53:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:53:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:53:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:53:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:53:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:53:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:53:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:53:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:53:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:53:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:53:48 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 03:53:49 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 03:53:49 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 03:53:49 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 03:53:49 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 03:53:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:53:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:53:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:53:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:53:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:53:49 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:53:49 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:53:49 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:53:49 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:53:49 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 03:53:49 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:53:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:53:49 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:53:49 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:53:50 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 03:53:50 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 03:53:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:53:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:53:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:53:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:53:51 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 03:53:51 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 03:53:51 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:53:51 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:53:51 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:53:51 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:53:52 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 03:53:52 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 03:53:52 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:53:52 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:53:52 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:53:52 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:53:53 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 03:53:53 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 03:53:53 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:53:53 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:53:53 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:53:53 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:53:54 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 03:53:54 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 03:53:54 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 03:53:55 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 03:53:55 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 03:53:56 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 03:53:56 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 03:53:57 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 03:53:57 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 03:53:58 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 03:53:58 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 03:53:59 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 03:53:59 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-27 03:54:00 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-27 03:54:00 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-27 03:54:01 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-27 03:54:01 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-27 03:54:02 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-27 03:54:02 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-27 03:54:03 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-27 03:54:03 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-27 03:54:04 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-27 03:54:04 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-27 03:54:05 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-27 03:54:05 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:54:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:54:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:54:05 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:54:05 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:54:05 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:54:05 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:54:05 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:54:05 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:54:05 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 03:54:05 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:54:05 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:54:05 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:54:10 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:54:10 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:54:10 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:54:10 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:54:10 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:54:10 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:54:10 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:54:10 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:54:10 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:54:10 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:54:10 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 03:54:10 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 03:54:10 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 03:54:10 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:54:10 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:54:10 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:54:10 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 03:54:10 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:54:10 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 03:54:10 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 03:54:10 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 03:54:10 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:54:10 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:54:10 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:54:10 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 03:54:10 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:54:10 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 03:54:10 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 03:54:10 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 03:54:10 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:54:10 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:54:10 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:54:10 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 03:54:10 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:54:10 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 03:54:10 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 03:54:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 03:54:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 03:54:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 03:54:10 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 03:54:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 03:54:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 03:54:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 03:54:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 03:54:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:54:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:54:10 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 03:54:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:54:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:54:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:54:10 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 03:54:10 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 03:54:10 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 03:54:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:54:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:54:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:54:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 03:54:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:54:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:54:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:54:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:54:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:54:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:54:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:54:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:54:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:54:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:54:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:54:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:54:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:54:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:54:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:54:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:54:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:54:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:54:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:54:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:54:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:54:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:54:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:54:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:54:10 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 03:54:10 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 03:54:10 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 03:54:10 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 03:54:10 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 03:54:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:54:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:54:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:54:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:54:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:54:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:54:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:54:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:54:11 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:54:11 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:54:11 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:54:11 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:54:11 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:54:11 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 03:54:11 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:54:16 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:54:16 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:54:16 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:54:16 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:54:16 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:54:16 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:54:16 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:54:16 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:54:16 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:54:16 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:54:16 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 03:54:16 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 03:54:16 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 03:54:16 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:54:16 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:54:16 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:54:16 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 03:54:16 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:54:16 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 03:54:16 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 03:54:16 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 03:54:16 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:54:16 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:54:16 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:54:16 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 03:54:16 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:54:16 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 03:54:16 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 03:54:16 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 03:54:16 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:54:16 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:54:16 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:54:16 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 03:54:16 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:54:16 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 03:54:16 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 03:54:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 03:54:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 03:54:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 03:54:16 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 03:54:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 03:54:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 03:54:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 03:54:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 03:54:16 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 03:54:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:54:16 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 03:54:16 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 03:54:16 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 03:54:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:54:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:54:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:54:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 03:54:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:54:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:54:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:54:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:54:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:54:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:54:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:54:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:54:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:54:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:54:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:54:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:54:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:54:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:54:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:54:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:54:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:54:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:54:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:54:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:54:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:54:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:54:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:54:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:54:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:54:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:54:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:54:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:54:16 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 03:54:16 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 03:54:16 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 03:54:16 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 03:54:16 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 03:54:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:54:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:54:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:54:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:54:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:54:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:54:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:54:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:54:16 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:54:16 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:54:16 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:54:16 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:54:16 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:54:16 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:54:16 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 03:54:16 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=115 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:54:16 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=115 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:54:16 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=115 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:54:16 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=115 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:54:16 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=115 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:54:16 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=115 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:54:16 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=115 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:54:21 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:54:21 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:54:21 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:54:21 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:54:21 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:54:21 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:54:21 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:54:21 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:54:21 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:54:21 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:54:21 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 03:54:21 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 03:54:21 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 03:54:21 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:54:21 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:54:21 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:54:21 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 03:54:21 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:54:21 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 03:54:21 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 03:54:21 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 03:54:21 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:54:21 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:54:21 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:54:21 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 03:54:21 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:54:21 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 03:54:21 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 03:54:21 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 03:54:21 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:54:21 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:54:21 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:54:21 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 03:54:21 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:54:21 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 03:54:21 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 03:54:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 03:54:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 03:54:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 03:54:21 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 03:54:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 03:54:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 03:54:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 03:54:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:54:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 03:54:21 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 03:54:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:54:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:54:21 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 03:54:21 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 03:54:21 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 03:54:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:54:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:54:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:54:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 03:54:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:54:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:54:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:54:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:54:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:54:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:54:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:54:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:54:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:54:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:54:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:54:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:54:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:54:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:54:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:54:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:54:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:54:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:54:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:54:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:54:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:54:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:54:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:54:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:54:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:54:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:54:21 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 03:54:22 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 03:54:22 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 03:54:22 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 03:54:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:54:22 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 03:54:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:54:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:54:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:54:22 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:54:22 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:54:22 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:54:22 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:54:22 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:54:22 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:54:22 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:54:22 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:54:22 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:54:22 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:54:22 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 03:54:22 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=125 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:54:22 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=125 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:54:22 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=125 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:54:22 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=125 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:54:22 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=125 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:54:22 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=125 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:54:22 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=126 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:54:22 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=126 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:54:22 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=126 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:54:22 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=126 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:54:22 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=126 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:54:22 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=126 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:54:22 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=126 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:54:22 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=126 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:54:27 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:54:27 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:54:27 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:54:27 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:54:27 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:54:27 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:54:27 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:54:27 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:54:27 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:54:27 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:54:27 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 03:54:27 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 03:54:27 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 03:54:27 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:54:27 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:54:27 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:54:27 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 03:54:27 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:54:27 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 03:54:27 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 03:54:27 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 03:54:27 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:54:27 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:54:27 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:54:27 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 03:54:27 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:54:27 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 03:54:27 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 03:54:27 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 03:54:27 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:54:27 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:54:27 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:54:27 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 03:54:27 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:54:27 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 03:54:27 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 03:54:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 03:54:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 03:54:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 03:54:27 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 03:54:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 03:54:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 03:54:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 03:54:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 03:54:27 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 03:54:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:54:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:54:27 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 03:54:27 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 03:54:27 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 03:54:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:54:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:54:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:54:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 03:54:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:54:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:54:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:54:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:54:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:54:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:54:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:54:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:54:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:54:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:54:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:54:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:54:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:54:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:54:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:54:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:54:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:54:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:54:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:54:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:54:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:54:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:54:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:54:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:54:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:54:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:54:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:54:27 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 03:54:27 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 03:54:27 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 03:54:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:54:27 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 03:54:27 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 03:54:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:54:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:54:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:54:27 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:54:27 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:54:27 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:54:27 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:54:27 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:54:27 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:54:27 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:54:27 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:54:27 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 03:54:27 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=127 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:54:27 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:54:27 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:54:27 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=127 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:54:27 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=127 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:54:27 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=127 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:54:27 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=127 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:54:27 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=128 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:54:27 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=128 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:54:27 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=128 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:54:27 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=128 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:54:27 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=128 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:54:27 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=128 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:54:27 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=128 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:54:27 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=128 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:54:32 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:54:32 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:54:32 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:54:32 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:54:32 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:54:32 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:54:32 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:54:32 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:54:32 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:54:32 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:54:32 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 03:54:32 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 03:54:32 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 03:54:32 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:54:32 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:54:32 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:54:32 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 03:54:32 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:54:32 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 03:54:32 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 03:54:32 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 03:54:32 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:54:32 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:54:32 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:54:32 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 03:54:32 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:54:32 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 03:54:32 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 03:54:32 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 03:54:32 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:54:32 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:54:32 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:54:32 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 03:54:32 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:54:32 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 03:54:32 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 03:54:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 03:54:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 03:54:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 03:54:32 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 03:54:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 03:54:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 03:54:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 03:54:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:54:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 03:54:32 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 03:54:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:54:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:54:32 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 03:54:32 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 03:54:32 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 03:54:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:54:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:54:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:54:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 03:54:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:54:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:54:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:54:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:54:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:54:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:54:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:54:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:54:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:54:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:54:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:54:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:54:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:54:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:54:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:54:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:54:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:54:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:54:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:54:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:54:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:54:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:54:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:54:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:54:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:54:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:54:32 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 03:54:33 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 03:54:33 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 03:54:33 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 03:54:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:54:33 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 03:54:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:54:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:54:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:54:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:54:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:54:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:54:33 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:54:33 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:54:33 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:54:33 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:54:33 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:54:33 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:54:33 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:54:33 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:54:33 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 03:54:33 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:54:33 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:54:33 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=128 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:54:33 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=128 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:54:33 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=128 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:54:33 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=128 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:54:33 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=128 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:54:33 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=128 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:54:38 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:54:38 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:54:38 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:54:38 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:54:38 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:54:38 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:54:38 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:54:38 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:54:38 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:54:38 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:54:38 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 03:54:38 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 03:54:38 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 03:54:38 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:54:38 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:54:38 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:54:38 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 03:54:38 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:54:38 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 03:54:38 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 03:54:38 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 03:54:38 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:54:38 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:54:38 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:54:38 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 03:54:38 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:54:38 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 03:54:38 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 03:54:38 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 03:54:38 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:54:38 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:54:38 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:54:38 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 03:54:38 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:54:38 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 03:54:38 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 03:54:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 03:54:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 03:54:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 03:54:38 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 03:54:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 03:54:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 03:54:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 03:54:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:54:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 03:54:38 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 03:54:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:54:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:54:38 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 03:54:38 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 03:54:38 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 03:54:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:54:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:54:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:54:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 03:54:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:54:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:54:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:54:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:54:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:54:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:54:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:54:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:54:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:54:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:54:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:54:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:54:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:54:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:54:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:54:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:54:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:54:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:54:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:54:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:54:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:54:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:54:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:54:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:54:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:54:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:54:38 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 03:54:38 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 03:54:39 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 03:54:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:54:39 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 03:54:39 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 03:54:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:54:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:54:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:54:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:54:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:54:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:54:39 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:54:39 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:54:39 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:54:39 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:54:39 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:54:39 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:54:39 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:54:39 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:54:39 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 03:54:39 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:54:39 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:54:39 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=127 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:54:39 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=127 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:54:39 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=127 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:54:39 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=127 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:54:39 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=127 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:54:39 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=127 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:54:39 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=127 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:54:44 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:54:44 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:54:44 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:54:44 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:54:44 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:54:44 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:54:44 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:54:44 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:54:44 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:54:44 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:54:44 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 03:54:44 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 03:54:44 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 03:54:44 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:54:44 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:54:44 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:54:44 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 03:54:44 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:54:44 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 03:54:44 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 03:54:44 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 03:54:44 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:54:44 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:54:44 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:54:44 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 03:54:44 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:54:44 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 03:54:44 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 03:54:44 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 03:54:44 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:54:44 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:54:44 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:54:44 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 03:54:44 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:54:44 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 03:54:44 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 03:54:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 03:54:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 03:54:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 03:54:44 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 03:54:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 03:54:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 03:54:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 03:54:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 03:54:44 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 03:54:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:54:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:54:44 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 03:54:44 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 03:54:44 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 03:54:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:54:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:54:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:54:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 03:54:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:54:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:54:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:54:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:54:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:54:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:54:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:54:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:54:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:54:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:54:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:54:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:54:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:54:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:54:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:54:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:54:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:54:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:54:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:54:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:54:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:54:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:54:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:54:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:54:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:54:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:54:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:54:44 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 03:54:44 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 03:54:44 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 03:54:44 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 03:54:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:54:44 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 03:54:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:54:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:54:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:54:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:54:44 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:54:44 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:54:44 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:54:44 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:54:45 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 03:54:45 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:54:45 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:54:45 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:54:45 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:54:45 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 03:54:46 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 03:54:46 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:54:46 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:54:46 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:54:46 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:54:46 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 03:54:46 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 03:54:47 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:54:47 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:54:47 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:54:47 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:54:47 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 03:54:47 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 03:54:48 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:54:48 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:54:48 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:54:48 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:54:48 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 03:54:48 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 03:54:49 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:54:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:54:49 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:54:49 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:54:49 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 03:54:49 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 03:54:50 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 03:54:50 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 03:54:51 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 03:54:51 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 03:54:52 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 03:54:52 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 03:54:53 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 03:54:53 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 03:54:54 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 03:54:54 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 03:54:55 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-27 03:54:55 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-27 03:54:56 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-27 03:54:56 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-27 03:54:56 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-27 03:54:57 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-27 03:54:57 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-27 03:54:58 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-27 03:54:58 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-27 03:54:59 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-27 03:54:59 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-27 03:55:00 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-27 03:55:00 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-27 03:55:01 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-27 03:55:01 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-27 03:55:02 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-27 03:55:02 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2025-04-27 03:55:03 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2025-04-27 03:55:03 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2025-04-27 03:55:04 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2025-04-27 03:55:04 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2025-04-27 03:55:05 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2025-04-27 03:55:05 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2025-04-27 03:55:05 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2025-04-27 03:55:06 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2025-04-27 03:55:06 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2025-04-27 03:55:07 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2025-04-27 03:55:07 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2025-04-27 03:55:08 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2025-04-27 03:55:08 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2025-04-27 03:55:09 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2025-04-27 03:55:09 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2025-04-27 03:55:10 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2025-04-27 03:55:10 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2025-04-27 03:55:11 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2025-04-27 03:55:11 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2025-04-27 03:55:12 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2025-04-27 03:55:12 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2025-04-27 03:55:13 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2025-04-27 03:55:13 [DEBUG] clck_gen.py:102 IND CLOCK 6324
2025-04-27 03:55:14 [DEBUG] clck_gen.py:102 IND CLOCK 6426
2025-04-27 03:55:14 [DEBUG] clck_gen.py:102 IND CLOCK 6528
2025-04-27 03:55:15 [DEBUG] clck_gen.py:102 IND CLOCK 6630
2025-04-27 03:55:15 [DEBUG] clck_gen.py:102 IND CLOCK 6732
2025-04-27 03:55:15 [DEBUG] clck_gen.py:102 IND CLOCK 6834
2025-04-27 03:55:16 [DEBUG] clck_gen.py:102 IND CLOCK 6936
2025-04-27 03:55:16 [DEBUG] clck_gen.py:102 IND CLOCK 7038
2025-04-27 03:55:17 [DEBUG] clck_gen.py:102 IND CLOCK 7140
2025-04-27 03:55:17 [DEBUG] clck_gen.py:102 IND CLOCK 7242
2025-04-27 03:55:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:55:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:55:18 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:55:18 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:55:18 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:55:18 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:55:18 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:55:18 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:55:18 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:55:18 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 03:55:18 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=7303 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:55:18 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:55:18 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:55:18 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:55:18 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=7303 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:55:18 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=7303 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:55:18 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=7303 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:55:18 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=7303 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:55:23 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:55:23 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:55:23 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:55:23 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:55:23 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:55:23 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:55:23 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:55:23 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:55:23 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:55:23 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:55:23 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 03:55:23 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 03:55:23 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 03:55:23 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:55:23 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:55:23 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:55:23 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 03:55:23 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:55:23 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 03:55:23 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 03:55:23 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 03:55:23 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:55:23 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:55:23 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:55:23 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 03:55:23 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:55:23 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 03:55:23 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 03:55:23 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 03:55:23 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:55:23 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:55:23 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:55:23 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 03:55:23 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:55:23 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 03:55:23 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 03:55:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 03:55:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 03:55:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 03:55:23 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 03:55:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 03:55:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 03:55:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 03:55:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:55:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 03:55:23 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 03:55:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:55:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:55:23 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 03:55:23 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 03:55:23 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 03:55:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:55:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:55:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:55:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 03:55:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:55:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:55:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:55:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:55:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:55:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:55:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:55:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:55:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:55:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:55:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:55:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:55:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:55:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:55:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:55:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:55:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:55:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:55:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:55:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:55:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:55:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:55:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:55:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:55:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:55:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:55:23 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 03:55:23 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 03:55:23 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 03:55:23 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 03:55:23 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 03:55:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:55:24 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 03:55:24 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:55:24 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:55:24 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:55:24 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:55:24 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 03:55:25 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 03:55:25 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:55:25 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:55:25 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:55:25 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:55:25 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 03:55:26 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 03:55:26 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:55:26 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:55:26 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:55:26 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:55:26 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 03:55:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:55:26 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:55:26 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:55:26 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:55:26 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:55:26 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:55:26 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:55:26 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:55:26 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:55:26 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 03:55:26 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:55:26 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:55:26 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=761 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:55:26 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=761 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:55:26 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=761 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:55:26 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=761 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:55:26 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=761 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:55:26 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=761 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:55:26 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=761 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:55:31 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:55:31 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:55:31 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:55:31 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:55:31 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:55:31 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:55:31 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:55:31 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:55:31 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:55:31 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:55:31 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 03:55:31 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 03:55:31 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 03:55:31 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:55:31 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:55:31 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:55:31 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 03:55:31 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:55:31 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 03:55:31 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 03:55:31 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 03:55:31 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:55:31 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:55:31 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:55:31 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 03:55:31 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:55:31 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 03:55:31 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 03:55:31 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 03:55:31 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:55:31 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:55:31 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:55:31 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 03:55:31 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:55:31 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 03:55:31 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 03:55:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 03:55:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 03:55:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 03:55:31 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 03:55:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 03:55:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 03:55:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 03:55:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 03:55:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:55:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:55:31 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 03:55:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:55:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:55:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:55:31 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 03:55:31 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 03:55:31 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 03:55:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:55:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:55:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:55:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 03:55:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:55:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:55:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:55:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:55:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:55:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:55:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:55:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:55:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:55:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:55:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:55:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:55:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:55:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:55:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:55:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:55:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:55:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:55:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:55:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:55:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:55:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:55:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:55:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:55:31 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 03:55:32 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 03:55:32 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 03:55:32 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 03:55:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:55:32 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 03:55:32 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 03:55:32 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:55:32 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:55:32 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:55:32 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:55:33 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 03:55:33 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 03:55:33 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:55:33 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:55:33 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:55:33 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:55:34 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 03:55:34 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 03:55:34 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:55:34 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:55:34 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:55:34 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:55:35 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 03:55:35 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 03:55:35 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:55:35 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:55:35 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:55:35 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:55:36 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 03:55:36 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 03:55:36 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:55:36 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:55:36 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:55:36 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:55:37 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 03:55:37 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 03:55:37 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 03:55:38 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:55:38 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:55:38 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:55:38 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:55:38 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:55:38 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:55:38 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:55:38 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:55:38 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:55:38 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 03:55:38 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:55:38 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1402 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:55:38 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1402 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:55:38 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1402 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:55:38 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1402 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:55:38 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1402 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:55:38 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1402 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:55:43 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:55:43 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:55:43 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:55:43 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:55:43 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:55:43 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:55:43 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:55:43 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:55:43 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:55:43 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:55:43 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 03:55:43 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 03:55:43 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 03:55:43 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:55:43 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:55:43 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:55:43 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 03:55:43 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:55:43 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 03:55:43 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 03:55:43 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 03:55:43 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:55:43 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:55:43 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:55:43 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 03:55:43 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:55:43 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 03:55:43 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 03:55:43 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 03:55:43 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:55:43 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:55:43 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:55:43 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 03:55:43 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:55:43 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 03:55:43 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 03:55:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 03:55:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 03:55:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 03:55:43 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 03:55:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 03:55:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 03:55:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 03:55:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:55:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:55:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 03:55:43 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 03:55:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:55:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:55:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:55:43 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 03:55:43 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 03:55:43 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 03:55:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:55:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:55:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:55:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 03:55:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:55:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:55:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:55:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:55:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:55:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:55:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:55:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:55:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:55:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:55:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:55:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:55:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:55:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:55:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:55:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:55:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:55:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:55:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:55:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:55:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:55:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:55:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:55:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:55:43 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 03:55:43 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 03:55:43 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 03:55:43 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 03:55:43 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 03:55:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:55:44 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 03:55:44 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:55:44 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:55:44 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:55:44 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:55:44 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 03:55:45 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 03:55:45 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:55:45 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:55:45 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:55:45 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:55:45 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 03:55:46 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 03:55:46 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:55:46 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:55:46 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:55:46 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:55:46 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 03:55:47 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 03:55:47 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:55:47 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:55:47 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:55:47 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:55:47 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 03:55:48 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 03:55:48 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:55:48 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:55:48 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:55:48 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:55:48 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 03:55:49 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 03:55:49 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 03:55:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:55:49 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:55:49 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:55:49 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:55:49 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:55:49 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:55:49 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:55:49 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:55:49 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:55:49 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 03:55:49 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:55:54 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:55:54 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:55:54 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:55:54 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:55:54 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:55:54 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:55:54 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:55:54 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:55:54 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:55:54 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:55:54 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 03:55:54 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 03:55:54 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 03:55:54 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:55:54 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:55:54 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:55:54 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 03:55:54 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:55:54 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 03:55:54 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 03:55:54 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 03:55:54 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:55:54 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:55:54 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:55:54 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 03:55:54 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:55:54 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 03:55:54 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 03:55:54 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 03:55:54 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:55:54 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:55:54 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:55:54 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 03:55:54 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:55:54 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 03:55:54 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 03:55:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 03:55:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 03:55:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 03:55:54 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 03:55:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 03:55:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 03:55:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 03:55:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 03:55:54 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 03:55:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:55:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:55:54 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 03:55:54 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 03:55:54 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 03:55:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:55:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:55:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:55:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 03:55:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:55:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:55:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:55:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:55:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:55:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:55:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:55:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:55:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:55:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:55:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:55:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:55:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:55:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:55:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:55:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:55:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:55:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:55:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:55:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:55:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:55:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:55:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:55:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:55:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:55:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:55:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:55:54 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 03:55:55 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 03:55:55 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 03:55:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:55:55 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 03:55:55 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 03:55:55 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 03:55:55 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:55:55 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:55:55 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:55:55 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:55:56 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 03:55:56 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 03:55:56 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:55:56 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:55:56 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:55:56 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:55:57 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 03:55:57 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 03:55:57 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:55:57 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:55:57 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:55:57 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:55:58 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 03:55:58 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 03:55:58 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:55:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:55:58 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:55:58 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:55:59 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 03:55:59 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 03:55:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:55:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:55:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:55:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:56:00 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 03:56:00 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 03:56:01 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 03:56:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:56:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:56:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:56:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:56:01 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:56:01 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:56:01 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:56:01 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:56:01 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:56:01 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 03:56:01 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1398 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:56:01 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:56:01 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1398 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:56:01 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1398 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:56:01 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1399 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:56:01 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1399 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:56:01 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1399 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:56:01 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1399 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:56:01 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1399 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:56:01 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1399 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:56:01 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1399 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:56:01 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1399 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:56:06 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:56:06 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:56:06 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:56:06 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:56:06 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:56:06 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:56:06 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:56:06 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:56:06 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:56:06 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:56:06 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 03:56:06 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 03:56:06 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 03:56:06 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:56:06 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:56:06 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:56:06 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 03:56:06 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:56:06 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 03:56:06 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 03:56:06 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 03:56:06 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:56:06 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:56:06 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:56:06 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 03:56:06 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:56:06 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 03:56:06 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 03:56:06 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 03:56:06 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:56:06 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:56:06 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:56:06 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 03:56:06 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:56:06 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 03:56:06 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 03:56:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 03:56:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 03:56:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 03:56:06 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 03:56:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 03:56:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 03:56:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 03:56:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 03:56:06 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 03:56:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:56:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:56:06 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 03:56:06 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 03:56:06 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 03:56:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:56:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:56:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:56:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 03:56:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:56:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:56:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:56:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:56:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:56:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:56:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:56:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:56:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:56:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:56:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:56:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:56:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:56:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:56:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:56:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:56:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:56:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:56:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:56:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:56:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:56:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:56:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:56:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:56:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:56:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:56:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:56:06 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 03:56:06 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 03:56:07 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 03:56:07 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 03:56:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:56:07 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 03:56:07 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 03:56:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:56:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:56:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:56:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:56:07 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 03:56:08 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 03:56:08 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:56:08 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:56:08 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:56:08 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:56:08 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 03:56:09 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 03:56:09 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:56:09 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:56:09 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:56:09 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:56:09 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 03:56:10 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 03:56:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:56:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:56:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:56:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:56:10 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 03:56:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:56:11 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 03:56:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:56:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:56:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:56:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:56:11 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 03:56:12 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 03:56:12 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 03:56:13 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 03:56:13 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 03:56:14 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 03:56:14 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 03:56:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:56:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:56:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:56:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:56:15 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:56:15 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:56:15 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:56:15 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:56:15 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:56:15 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:56:15 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 03:56:15 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1827 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:56:15 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1827 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:56:15 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1827 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:56:15 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1827 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:56:15 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1827 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:56:20 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:56:20 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:56:20 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:56:20 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:56:20 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:56:20 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:56:20 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:56:20 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:56:20 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:56:20 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:56:20 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 03:56:20 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 03:56:20 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 03:56:20 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:56:20 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:56:20 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:56:20 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 03:56:20 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:56:20 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 03:56:20 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 03:56:20 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 03:56:20 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:56:20 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:56:20 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:56:20 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 03:56:20 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:56:20 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 03:56:20 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 03:56:20 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 03:56:20 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:56:20 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:56:20 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:56:20 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 03:56:20 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:56:20 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 03:56:20 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 03:56:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 03:56:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 03:56:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 03:56:20 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 03:56:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 03:56:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 03:56:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 03:56:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 03:56:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:56:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:56:20 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 03:56:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:56:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:56:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:56:20 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 03:56:20 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 03:56:20 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 03:56:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:56:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:56:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:56:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 03:56:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:56:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:56:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:56:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:56:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:56:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:56:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:56:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:56:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:56:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:56:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:56:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:56:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:56:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:56:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:56:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:56:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:56:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:56:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:56:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:56:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:56:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:56:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:56:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:56:20 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 03:56:20 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 03:56:20 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 03:56:20 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 03:56:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:56:20 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 03:56:21 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 03:56:21 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:56:21 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:56:21 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:56:21 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:56:21 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 03:56:21 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 03:56:22 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:56:22 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:56:22 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:56:22 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:56:22 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 03:56:22 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 03:56:23 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:56:23 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:56:23 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:56:23 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:56:23 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 03:56:23 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 03:56:24 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:56:24 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:56:24 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:56:24 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:56:24 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 03:56:24 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:56:24 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:56:24 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:56:24 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:56:24 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:56:24 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:56:24 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:56:24 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:56:24 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:56:24 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:56:24 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 03:56:24 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=971 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:56:29 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:56:29 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:56:29 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:56:29 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:56:29 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:56:29 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:56:29 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:56:29 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:56:29 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:56:29 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:56:29 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 03:56:29 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 03:56:29 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 03:56:29 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:56:29 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:56:29 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:56:29 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 03:56:29 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:56:29 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 03:56:29 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 03:56:29 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 03:56:29 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:56:29 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:56:29 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:56:29 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 03:56:29 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:56:29 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 03:56:29 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 03:56:29 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 03:56:29 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:56:29 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:56:29 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:56:29 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 03:56:29 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:56:29 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 03:56:29 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 03:56:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 03:56:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 03:56:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 03:56:29 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 03:56:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 03:56:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 03:56:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 03:56:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:56:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 03:56:29 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 03:56:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:56:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:56:29 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 03:56:29 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 03:56:29 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 03:56:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:56:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:56:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:56:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 03:56:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:56:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:56:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:56:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:56:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:56:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:56:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:56:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:56:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:56:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:56:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:56:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:56:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:56:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:56:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:56:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:56:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:56:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:56:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:56:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:56:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:56:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:56:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:56:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:56:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:56:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:56:29 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 03:56:30 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 03:56:30 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 03:56:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:56:30 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 03:56:30 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 03:56:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:56:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:56:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:56:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:56:30 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:56:30 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:56:30 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:56:30 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:56:30 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:56:30 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:56:30 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 03:56:35 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:56:35 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:56:35 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:56:35 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:56:35 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:56:35 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:56:35 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:56:35 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:56:35 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:56:35 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:56:35 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 03:56:35 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 03:56:35 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 03:56:35 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:56:35 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:56:35 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:56:35 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 03:56:35 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:56:35 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 03:56:35 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 03:56:35 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 03:56:35 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:56:35 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:56:35 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:56:35 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 03:56:35 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:56:35 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 03:56:35 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 03:56:35 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 03:56:35 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:56:35 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:56:35 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:56:35 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 03:56:35 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:56:35 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 03:56:35 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 03:56:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 03:56:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 03:56:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 03:56:35 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 03:56:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 03:56:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 03:56:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 03:56:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:56:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 03:56:35 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 03:56:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:56:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:56:35 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 03:56:35 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 03:56:35 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 03:56:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:56:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:56:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:56:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 03:56:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:56:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:56:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:56:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:56:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:56:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:56:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:56:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:56:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:56:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:56:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:56:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:56:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:56:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:56:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:56:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:56:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:56:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:56:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:56:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:56:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:56:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:56:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:56:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:56:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:56:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:56:35 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 03:56:35 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 03:56:35 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 03:56:35 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 03:56:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:56:35 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 03:56:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:56:35 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:56:35 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:56:35 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:56:35 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:56:35 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:56:35 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:56:35 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:56:35 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:56:35 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:56:35 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:56:35 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 03:56:35 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=125 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:56:35 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=125 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:56:35 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=125 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:56:35 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=125 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:56:35 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=125 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:56:35 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=125 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:56:40 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:56:40 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:56:40 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:56:40 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:56:40 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:56:40 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:56:40 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:56:40 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:56:40 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:56:40 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:56:40 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 03:56:40 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 03:56:40 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 03:56:40 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:56:40 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:56:40 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:56:40 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 03:56:40 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:56:40 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 03:56:40 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 03:56:40 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 03:56:40 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:56:40 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:56:40 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:56:40 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 03:56:40 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:56:40 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 03:56:40 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 03:56:40 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 03:56:40 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:56:40 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:56:40 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:56:40 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 03:56:40 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:56:40 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 03:56:40 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 03:56:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 03:56:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 03:56:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 03:56:40 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 03:56:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 03:56:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 03:56:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 03:56:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 03:56:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:56:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:56:40 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 03:56:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:56:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:56:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:56:40 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 03:56:40 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 03:56:40 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 03:56:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:56:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:56:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:56:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 03:56:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:56:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:56:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:56:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:56:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:56:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:56:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:56:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:56:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:56:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:56:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:56:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:56:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:56:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:56:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:56:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:56:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:56:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:56:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:56:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:56:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:56:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:56:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:56:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:56:40 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 03:56:41 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 03:56:41 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 03:56:41 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 03:56:41 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 03:56:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:56:41 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:56:41 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:56:41 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:56:41 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:56:41 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:56:41 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:56:41 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:56:41 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:56:41 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:56:41 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:56:41 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 03:56:46 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:56:46 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:56:46 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:56:46 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:56:46 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:56:46 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:56:46 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:56:46 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:56:46 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:56:46 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:56:46 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 03:56:46 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 03:56:46 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 03:56:46 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:56:46 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:56:46 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:56:46 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 03:56:46 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:56:46 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 03:56:46 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 03:56:46 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 03:56:46 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:56:46 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:56:46 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:56:46 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 03:56:46 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:56:46 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 03:56:46 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 03:56:46 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 03:56:46 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:56:46 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:56:46 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:56:46 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 03:56:46 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:56:46 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 03:56:46 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 03:56:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 03:56:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 03:56:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 03:56:46 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 03:56:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 03:56:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 03:56:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 03:56:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:56:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 03:56:46 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 03:56:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:56:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:56:46 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 03:56:46 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 03:56:46 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 03:56:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:56:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:56:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:56:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 03:56:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:56:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:56:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:56:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:56:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:56:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:56:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:56:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:56:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:56:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:56:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:56:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:56:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:56:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:56:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:56:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:56:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:56:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:56:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:56:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:56:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:56:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:56:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:56:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:56:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:56:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:56:46 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 03:56:46 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 03:56:46 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 03:56:46 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 03:56:46 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 03:56:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:56:46 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:56:46 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:56:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:56:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:56:46 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:56:46 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:56:47 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:56:47 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:56:47 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 03:56:47 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:56:47 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:56:47 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:56:47 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:56:47 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 03:56:48 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 03:56:48 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:56:48 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:56:48 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:56:48 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:56:48 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 03:56:49 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 03:56:49 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:56:49 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:56:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:56:49 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:56:49 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 03:56:50 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:56:50 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:56:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:56:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:56:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:56:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:56:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:56:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:56:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:56:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:56:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:56:50 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:56:50 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:56:50 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:56:50 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:56:50 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 03:56:50 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:56:50 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:56:50 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=781 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:56:50 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=781 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:56:50 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=781 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:56:50 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=781 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:56:50 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=781 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:56:50 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=781 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:56:50 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=781 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:56:55 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:56:55 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:56:55 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:56:55 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:56:55 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:56:55 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:56:55 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:56:55 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:56:55 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:56:55 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:56:55 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 03:56:55 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 03:56:55 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 03:56:55 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:56:55 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:56:55 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:56:55 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 03:56:55 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:56:55 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 03:56:55 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 03:56:55 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 03:56:55 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:56:55 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:56:55 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:56:55 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 03:56:55 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:56:55 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 03:56:55 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 03:56:55 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 03:56:55 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:56:55 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:56:55 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:56:55 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 03:56:55 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:56:55 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 03:56:55 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 03:56:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 03:56:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 03:56:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 03:56:55 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 03:56:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 03:56:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 03:56:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 03:56:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:56:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 03:56:55 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 03:56:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:56:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:56:55 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 03:56:55 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 03:56:55 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 03:56:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:56:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:56:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:56:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 03:56:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:56:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:56:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:56:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:56:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:56:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:56:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:56:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:56:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:56:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:56:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:56:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:56:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:56:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:56:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:56:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:56:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:56:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:56:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:56:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:56:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:56:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:56:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:56:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:56:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:56:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:56:55 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 03:56:55 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 03:56:55 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 03:56:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:56:55 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 03:56:55 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 03:56:55 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:56:55 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:56:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:56:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:56:55 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:56:55 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:56:55 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:56:55 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:56:56 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 03:56:56 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:56:56 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:56:56 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:56:56 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:56:56 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 03:56:57 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 03:56:57 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:56:57 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:56:57 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:56:57 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:56:57 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 03:56:58 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 03:56:58 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:56:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:56:58 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:56:58 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:56:58 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 03:56:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:56:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:56:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:56:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:56:58 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 03:56:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:56:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:56:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:56:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:56:59 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 03:56:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:56:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:56:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:56:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:56:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:56:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:56:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:56:59 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:56:59 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:56:59 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:56:59 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:56:59 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 03:56:59 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=924 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:56:59 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:56:59 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:56:59 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=924 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:56:59 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=924 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:56:59 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=924 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:56:59 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=924 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:56:59 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=924 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:57:04 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:57:04 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:57:04 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:57:04 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:57:04 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:57:04 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:57:04 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:57:04 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:57:04 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:57:04 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:57:04 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 03:57:04 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 03:57:04 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 03:57:04 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:57:04 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:57:04 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:57:04 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 03:57:04 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:57:04 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 03:57:04 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 03:57:04 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 03:57:04 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:57:04 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:57:04 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:57:04 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 03:57:04 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:57:04 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 03:57:04 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 03:57:04 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 03:57:04 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:57:04 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:57:04 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:57:04 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 03:57:04 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:57:04 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 03:57:04 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 03:57:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 03:57:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 03:57:04 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 03:57:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 03:57:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 03:57:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 03:57:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 03:57:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 03:57:04 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 03:57:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:57:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:57:04 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 03:57:04 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 03:57:04 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 03:57:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:57:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:57:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:57:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 03:57:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:57:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:57:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:57:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:57:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:57:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:57:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:57:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:57:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:57:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:57:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:57:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:57:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:57:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:57:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:57:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:57:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:57:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:57:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:57:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:57:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:57:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:57:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:57:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:57:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:57:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:57:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:57:04 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 03:57:04 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 03:57:05 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 03:57:05 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 03:57:05 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 03:57:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:57:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:57:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:57:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:57:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:57:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:57:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:57:05 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:57:05 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:57:05 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 03:57:05 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:57:05 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:57:05 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:57:05 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:57:05 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 03:57:06 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 03:57:06 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:57:06 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:57:06 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:57:06 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:57:06 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 03:57:07 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 03:57:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:57:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:57:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:57:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:57:07 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 03:57:08 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:57:08 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:57:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:57:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:57:08 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 03:57:08 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:57:08 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:57:08 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:57:08 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:57:08 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 03:57:09 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 03:57:09 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:57:09 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:57:09 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:57:09 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:57:09 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 03:57:10 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 03:57:10 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 03:57:11 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 03:57:11 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 03:57:12 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 03:57:12 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 03:57:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:57:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:57:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:57:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:57:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:57:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:57:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:57:13 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:57:13 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:57:13 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:57:13 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:57:13 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:57:13 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:57:13 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 03:57:13 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1836 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:57:13 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1836 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:57:13 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1836 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:57:13 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1836 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:57:13 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1836 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:57:13 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1836 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:57:18 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:57:18 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:57:18 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:57:18 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:57:18 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:57:18 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:57:18 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:57:18 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:57:18 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:57:18 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:57:18 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 03:57:18 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 03:57:18 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 03:57:18 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:57:18 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:57:18 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:57:18 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 03:57:18 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:57:18 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 03:57:18 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 03:57:18 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 03:57:18 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:57:18 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:57:18 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:57:18 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 03:57:18 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:57:18 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 03:57:18 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 03:57:18 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 03:57:18 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:57:18 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:57:18 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:57:18 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 03:57:18 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:57:18 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 03:57:18 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 03:57:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 03:57:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 03:57:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 03:57:18 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 03:57:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 03:57:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 03:57:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 03:57:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 03:57:18 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 03:57:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:57:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:57:18 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 03:57:18 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 03:57:18 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 03:57:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:57:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:57:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:57:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 03:57:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:57:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:57:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:57:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:57:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:57:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:57:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:57:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:57:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:57:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:57:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:57:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:57:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:57:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:57:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:57:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:57:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:57:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:57:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:57:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:57:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:57:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:57:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:57:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:57:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:57:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:57:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:57:18 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 03:57:18 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 03:57:18 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 03:57:18 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 03:57:18 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 03:57:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:57:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:57:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:57:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:57:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:57:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:57:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:57:18 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:57:18 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:57:19 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 03:57:19 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:57:19 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:57:19 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:57:19 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:57:19 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 03:57:20 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 03:57:20 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:57:20 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:57:20 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:57:20 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:57:20 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 03:57:20 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 03:57:21 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:57:21 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:57:21 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:57:21 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:57:21 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 03:57:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:57:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:57:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:57:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:57:21 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 03:57:22 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:57:22 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:57:22 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:57:22 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:57:22 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 03:57:22 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 03:57:23 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:57:23 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:57:23 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:57:23 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:57:23 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 03:57:23 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 03:57:24 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 03:57:24 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 03:57:25 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 03:57:25 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 03:57:26 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 03:57:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:57:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:57:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:57:26 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:57:26 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:57:26 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:57:26 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:57:26 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:57:26 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:57:26 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:57:26 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 03:57:26 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:57:26 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:57:26 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:57:26 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1832 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:57:26 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1832 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:57:26 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1832 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:57:26 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1832 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:57:26 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1832 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:57:26 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1832 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:57:26 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1833 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:57:26 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1833 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:57:26 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1833 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:57:26 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1833 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:57:26 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1833 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:57:26 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1833 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:57:26 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1833 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:57:26 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1833 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:57:31 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:57:31 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:57:31 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:57:31 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:57:31 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:57:31 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:57:31 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:57:31 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:57:31 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:57:31 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:57:31 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 03:57:31 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 03:57:31 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 03:57:31 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:57:31 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:57:31 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:57:31 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 03:57:31 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:57:31 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 03:57:31 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 03:57:31 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 03:57:31 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:57:31 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:57:31 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:57:31 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 03:57:31 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:57:31 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 03:57:31 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 03:57:31 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 03:57:31 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:57:31 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:57:31 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:57:31 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 03:57:31 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:57:31 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 03:57:31 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 03:57:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 03:57:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 03:57:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 03:57:31 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 03:57:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 03:57:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 03:57:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 03:57:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:57:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 03:57:31 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 03:57:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:57:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:57:31 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 03:57:31 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 03:57:31 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 03:57:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:57:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:57:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:57:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 03:57:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:57:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:57:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:57:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:57:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:57:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:57:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:57:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:57:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:57:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:57:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:57:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:57:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:57:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:57:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:57:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:57:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:57:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:57:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:57:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:57:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:57:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:57:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:57:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:57:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:57:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:57:31 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 03:57:32 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 03:57:32 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 03:57:32 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 03:57:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:57:32 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 03:57:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:57:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:57:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:57:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:57:32 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:57:32 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:57:32 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:57:32 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:57:32 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 03:57:32 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:57:32 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:57:32 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:57:32 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:57:33 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 03:57:33 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 03:57:33 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:57:33 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:57:33 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:57:33 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:57:34 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 03:57:34 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 03:57:34 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:57:34 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:57:34 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:57:34 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:57:35 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 03:57:35 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:57:35 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:57:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:57:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:57:35 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 03:57:35 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:57:35 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:57:35 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:57:35 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:57:36 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 03:57:36 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 03:57:36 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:57:36 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:57:36 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:57:36 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:57:36 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 03:57:37 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 03:57:37 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 03:57:38 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 03:57:38 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 03:57:39 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 03:57:39 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 03:57:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:57:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:57:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:57:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:57:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:57:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:57:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:57:40 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:57:40 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:57:40 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:57:40 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 03:57:40 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:57:40 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:57:40 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:57:40 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1827 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:57:40 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1827 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:57:40 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1827 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:57:40 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1827 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:57:40 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1827 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:57:40 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1827 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:57:40 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1827 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:57:45 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:57:45 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:57:45 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:57:45 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:57:45 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:57:45 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:57:45 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:57:45 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:57:45 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:57:45 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:57:45 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 03:57:45 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 03:57:45 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 03:57:45 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:57:45 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:57:45 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:57:45 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 03:57:45 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:57:45 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 03:57:45 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 03:57:45 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 03:57:45 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:57:45 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:57:45 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:57:45 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 03:57:45 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:57:45 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 03:57:45 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 03:57:45 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 03:57:45 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:57:45 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:57:45 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:57:45 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 03:57:45 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:57:45 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 03:57:45 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 03:57:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 03:57:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 03:57:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 03:57:45 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 03:57:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 03:57:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 03:57:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 03:57:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 03:57:45 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 03:57:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:57:45 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 03:57:45 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 03:57:45 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 03:57:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:57:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:57:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:57:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 03:57:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:57:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:57:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:57:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:57:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:57:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:57:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:57:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:57:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:57:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:57:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:57:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:57:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:57:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:57:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:57:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:57:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:57:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:57:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:57:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:57:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:57:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:57:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:57:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:57:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:57:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:57:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:57:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:57:45 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 03:57:45 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 03:57:45 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 03:57:45 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 03:57:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:57:45 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 03:57:45 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:57:45 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:57:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:57:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:57:45 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:57:45 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:57:45 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:57:45 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:57:45 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:57:45 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:57:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:57:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:57:46 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 03:57:46 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:57:46 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:57:46 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:57:46 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:57:46 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 03:57:47 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 03:57:47 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:57:47 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:57:47 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:57:47 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:57:47 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 03:57:48 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 03:57:48 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:57:48 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:57:48 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:57:48 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:57:48 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 03:57:49 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 03:57:49 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:57:49 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:57:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:57:49 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:57:49 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 03:57:50 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 03:57:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:57:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:57:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:57:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:57:50 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 03:57:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:57:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:57:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:57:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:57:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:57:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:57:50 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:57:50 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:57:50 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:57:50 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:57:50 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:57:50 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 03:57:50 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:57:50 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1183 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:57:50 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1183 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:57:50 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1183 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:57:50 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1183 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:57:50 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1183 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:57:50 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1183 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:57:55 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:57:55 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:57:55 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:57:55 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:57:55 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:57:55 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:57:55 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:57:55 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:57:55 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:57:55 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:57:55 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 03:57:55 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 03:57:55 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 03:57:55 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:57:55 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:57:55 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:57:55 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 03:57:55 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:57:55 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 03:57:55 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 03:57:55 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 03:57:55 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:57:55 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:57:55 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 03:57:55 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:57:55 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 03:57:55 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:57:55 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 03:57:55 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 03:57:55 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:57:55 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:57:55 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:57:55 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 03:57:55 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:57:55 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 03:57:55 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 03:57:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 03:57:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 03:57:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 03:57:55 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 03:57:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 03:57:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 03:57:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 03:57:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 03:57:55 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 03:57:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:57:55 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 03:57:55 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 03:57:55 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 03:57:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:57:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:57:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:57:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 03:57:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:57:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:57:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:57:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:57:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:57:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:57:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:57:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:57:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:57:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:57:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:57:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:57:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:57:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:57:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:57:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:57:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:57:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:57:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:57:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:57:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:57:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:57:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:57:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:57:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:57:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:57:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:57:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:57:55 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 03:57:56 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 03:57:56 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 03:57:56 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 03:57:56 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 03:57:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:57:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:57:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:57:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:57:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:57:56 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:57:56 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:57:56 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:57:56 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:57:56 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 03:57:56 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:57:56 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:57:56 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:57:56 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:57:57 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 03:57:57 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 03:57:57 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:57:57 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:57:57 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:57:57 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:57:58 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 03:57:58 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 03:57:58 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:57:58 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:57:58 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:57:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:57:59 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 03:57:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:57:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:57:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:57:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:57:59 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 03:57:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:57:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:57:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:57:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:58:00 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 03:58:00 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 03:58:00 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:58:00 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:58:00 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:58:00 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:58:01 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 03:58:01 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 03:58:02 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 03:58:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:58:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:58:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:58:02 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:58:02 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:58:02 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:58:02 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:58:02 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:58:02 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:58:02 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:58:02 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:58:02 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:58:02 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:58:02 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 03:58:02 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1340 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:58:02 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1340 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:58:02 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1340 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:58:02 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1340 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:58:02 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1340 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:58:02 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1340 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:58:07 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:58:07 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:58:07 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:58:07 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:58:07 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:58:07 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:58:07 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:58:07 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:58:07 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:58:07 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:58:07 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 03:58:07 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 03:58:07 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 03:58:07 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:58:07 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:58:07 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:58:07 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 03:58:07 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:58:07 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 03:58:07 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 03:58:07 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 03:58:07 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:58:07 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:58:07 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:58:07 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 03:58:07 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:58:07 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 03:58:07 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 03:58:07 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 03:58:07 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:58:07 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:58:07 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:58:07 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 03:58:07 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:58:07 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 03:58:07 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 03:58:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 03:58:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 03:58:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 03:58:07 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 03:58:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 03:58:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 03:58:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 03:58:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:58:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 03:58:07 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 03:58:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:58:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:58:07 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 03:58:07 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 03:58:07 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 03:58:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:58:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:58:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:58:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 03:58:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:58:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:58:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:58:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:58:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:58:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:58:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:58:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:58:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:58:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:58:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:58:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:58:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:58:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:58:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:58:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:58:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:58:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:58:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:58:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:58:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:58:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:58:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:58:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:58:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:58:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:58:07 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 03:58:07 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 03:58:07 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 03:58:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:58:07 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 03:58:07 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 03:58:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:58:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:58:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:58:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:58:07 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:58:07 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:58:07 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:58:07 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:58:08 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 03:58:08 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:58:08 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:58:08 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:58:08 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:58:08 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 03:58:09 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 03:58:09 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:58:09 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:58:09 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:58:09 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:58:09 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 03:58:10 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 03:58:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:58:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:58:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:58:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:58:10 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 03:58:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:58:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:58:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:58:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:58:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:58:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:58:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:58:10 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:58:10 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:58:10 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:58:10 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:58:10 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 03:58:10 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:58:10 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:58:15 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:58:15 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:58:15 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:58:15 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:58:15 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:58:15 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:58:15 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:58:15 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:58:15 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:58:15 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:58:15 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 03:58:15 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 03:58:15 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 03:58:15 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:58:15 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:58:15 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:58:15 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 03:58:15 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:58:15 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 03:58:15 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 03:58:15 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 03:58:15 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:58:15 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:58:15 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:58:15 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 03:58:15 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:58:15 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 03:58:15 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 03:58:15 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 03:58:15 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:58:15 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:58:15 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:58:15 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 03:58:15 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:58:15 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 03:58:15 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 03:58:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 03:58:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 03:58:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 03:58:15 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 03:58:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 03:58:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 03:58:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 03:58:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:58:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 03:58:15 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 03:58:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:58:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:58:15 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 03:58:15 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 03:58:15 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 03:58:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:58:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:58:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:58:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 03:58:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:58:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:58:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:58:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:58:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:58:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:58:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:58:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:58:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:58:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:58:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:58:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:58:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:58:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:58:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:58:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:58:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:58:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:58:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:58:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:58:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:58:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:58:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:58:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:58:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:58:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:58:15 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 03:58:16 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 03:58:16 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 03:58:16 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 03:58:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:58:16 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 03:58:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:58:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:58:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:58:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:58:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:58:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:58:16 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:58:16 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:58:16 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 03:58:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:58:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:58:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:58:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:58:17 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 03:58:17 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 03:58:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:58:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:58:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:58:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:58:18 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 03:58:18 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 03:58:18 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:58:18 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:58:18 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:58:18 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:58:19 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 03:58:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:58:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:58:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:58:19 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:58:19 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:58:19 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:58:19 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:58:19 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:58:19 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:58:19 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:58:19 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:58:19 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 03:58:19 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=786 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:58:19 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:58:19 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:58:19 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=786 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:58:19 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=786 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:58:19 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=786 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:58:19 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=786 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:58:19 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=786 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:58:19 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=786 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:58:19 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=786 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:58:19 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=787 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:58:19 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=787 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:58:19 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=787 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:58:19 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=787 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:58:19 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=787 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:58:19 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=787 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:58:19 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=787 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:58:19 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=787 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:58:24 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:58:24 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:58:24 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:58:24 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:58:24 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:58:24 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:58:24 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:58:24 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:58:24 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:58:24 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:58:24 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 03:58:24 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 03:58:24 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 03:58:24 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:58:24 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:58:24 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:58:24 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 03:58:24 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:58:24 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 03:58:24 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 03:58:24 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 03:58:24 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:58:24 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:58:24 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:58:24 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 03:58:24 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:58:24 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 03:58:24 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 03:58:24 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 03:58:24 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:58:24 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:58:24 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:58:24 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 03:58:24 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:58:24 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 03:58:24 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 03:58:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 03:58:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 03:58:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 03:58:24 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 03:58:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 03:58:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 03:58:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 03:58:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:58:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 03:58:24 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 03:58:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:58:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:58:24 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 03:58:24 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 03:58:24 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 03:58:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:58:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:58:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:58:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 03:58:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:58:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:58:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:58:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:58:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:58:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:58:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:58:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:58:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:58:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:58:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:58:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:58:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:58:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:58:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:58:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:58:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:58:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:58:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:58:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:58:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:58:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:58:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:58:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:58:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:58:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:58:24 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 03:58:25 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 03:58:25 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 03:58:25 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 03:58:25 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 03:58:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:58:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:58:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:58:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:58:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:58:25 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:58:25 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:58:25 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:58:25 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:58:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:58:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:58:25 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:58:25 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:58:25 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:58:25 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:58:25 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:58:25 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:58:25 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:58:25 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:58:25 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 03:58:25 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:58:25 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:58:30 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:58:30 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:58:30 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:58:30 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:58:30 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:58:30 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:58:30 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:58:30 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:58:30 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:58:30 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:58:30 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 03:58:30 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 03:58:30 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 03:58:30 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:58:30 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:58:30 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:58:30 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 03:58:30 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:58:30 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 03:58:30 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 03:58:30 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 03:58:30 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:58:30 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:58:30 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:58:30 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 03:58:30 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:58:30 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 03:58:30 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 03:58:30 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 03:58:30 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:58:30 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:58:30 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:58:30 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 03:58:30 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:58:30 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 03:58:30 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 03:58:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 03:58:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 03:58:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 03:58:30 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 03:58:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 03:58:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 03:58:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 03:58:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:58:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 03:58:30 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 03:58:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:58:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:58:30 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 03:58:30 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 03:58:30 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 03:58:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:58:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:58:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:58:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 03:58:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:58:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:58:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:58:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:58:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:58:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:58:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:58:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:58:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:58:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:58:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:58:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:58:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:58:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:58:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:58:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:58:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:58:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:58:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:58:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:58:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:58:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:58:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:58:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:58:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:58:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:58:30 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 03:58:30 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 03:58:30 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 03:58:30 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 03:58:30 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 03:58:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:58:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:58:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:58:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:58:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:58:30 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:58:30 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:58:30 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:58:30 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:58:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:58:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:58:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:58:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:58:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:58:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:58:31 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:58:31 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:58:31 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:58:31 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:58:31 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:58:31 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 03:58:31 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=124 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:58:31 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:58:36 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:58:36 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:58:36 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:58:36 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:58:36 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:58:36 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:58:36 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:58:36 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:58:36 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:58:36 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:58:36 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 03:58:36 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 03:58:36 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 03:58:36 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:58:36 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:58:36 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:58:36 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 03:58:36 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:58:36 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 03:58:36 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 03:58:36 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 03:58:36 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:58:36 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:58:36 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:58:36 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 03:58:36 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:58:36 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 03:58:36 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 03:58:36 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 03:58:36 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:58:36 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:58:36 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:58:36 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 03:58:36 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:58:36 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 03:58:36 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 03:58:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 03:58:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 03:58:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 03:58:36 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 03:58:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 03:58:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 03:58:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 03:58:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:58:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 03:58:36 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 03:58:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:58:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:58:36 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 03:58:36 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 03:58:36 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 03:58:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:58:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:58:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:58:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 03:58:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:58:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:58:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:58:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:58:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:58:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:58:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:58:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:58:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:58:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:58:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:58:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:58:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:58:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:58:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:58:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:58:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:58:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:58:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:58:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:58:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:58:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:58:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:58:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:58:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:58:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:58:36 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 03:58:36 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 03:58:36 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 03:58:36 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 03:58:36 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 03:58:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:58:36 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:58:36 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:58:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:58:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:58:36 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:58:36 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:58:36 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:58:36 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:58:37 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 03:58:37 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:58:37 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:58:37 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:58:37 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:58:37 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 03:58:37 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 03:58:38 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:58:38 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:58:38 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:58:38 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:58:38 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 03:58:38 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 03:58:39 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:58:39 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:58:39 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:58:39 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:58:39 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 03:58:39 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 03:58:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:58:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:58:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:58:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:58:40 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 03:58:40 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 03:58:41 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:58:41 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:58:41 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:58:41 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:58:41 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 03:58:41 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 03:58:42 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 03:58:42 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 03:58:43 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 03:58:43 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 03:58:44 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 03:58:44 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 03:58:45 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 03:58:45 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:58:45 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:58:45 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:58:45 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:58:45 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:58:45 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:58:45 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:58:45 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:58:45 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:58:45 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:58:45 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:58:45 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:58:45 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 03:58:45 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2014 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:58:45 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2014 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:58:45 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2014 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:58:45 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2014 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:58:45 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2014 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:58:45 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2014 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:58:45 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2015 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:58:45 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2015 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:58:45 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2015 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:58:45 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2015 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:58:45 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2015 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:58:45 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2015 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:58:45 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2015 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:58:45 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2015 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:58:50 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:58:50 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:58:50 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:58:50 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:58:50 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:58:50 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:58:50 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:58:50 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:58:50 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:58:50 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:58:50 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 03:58:50 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 03:58:50 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 03:58:50 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:58:50 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:58:50 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:58:50 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 03:58:50 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:58:50 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 03:58:50 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 03:58:50 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 03:58:50 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:58:50 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:58:50 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:58:50 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 03:58:50 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:58:50 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 03:58:50 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 03:58:50 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 03:58:50 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:58:50 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:58:50 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:58:50 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 03:58:50 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:58:50 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 03:58:50 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 03:58:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 03:58:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 03:58:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 03:58:50 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 03:58:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 03:58:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 03:58:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 03:58:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:58:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 03:58:50 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 03:58:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:58:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:58:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:58:50 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 03:58:50 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 03:58:50 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 03:58:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:58:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:58:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:58:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 03:58:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:58:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:58:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:58:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:58:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:58:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:58:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:58:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:58:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:58:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:58:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:58:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:58:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:58:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:58:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:58:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:58:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:58:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:58:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:58:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:58:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:58:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:58:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:58:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:58:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:58:50 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 03:58:50 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 03:58:50 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 03:58:50 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 03:58:50 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 03:58:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:58:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:58:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:58:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:58:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:58:50 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:58:50 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:58:50 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:58:50 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:58:51 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 03:58:51 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:58:51 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:58:51 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:58:51 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:58:51 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 03:58:52 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 03:58:52 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:58:52 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:58:52 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:58:52 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:58:52 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 03:58:53 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 03:58:53 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:58:53 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:58:53 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:58:53 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:58:53 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 03:58:54 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 03:58:54 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:58:54 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:58:54 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:58:54 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:58:54 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 03:58:55 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 03:58:55 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:58:55 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:58:55 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:58:55 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:58:55 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 03:58:56 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 03:58:56 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 03:58:57 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 03:58:57 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 03:58:58 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 03:58:58 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 03:58:59 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 03:58:59 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 03:58:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:58:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:58:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:58:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:58:59 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:58:59 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:58:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:58:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:58:59 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:58:59 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:58:59 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 03:58:59 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:58:59 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:58:59 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2011 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:58:59 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2011 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:58:59 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2011 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:58:59 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2011 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:58:59 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2011 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:58:59 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2011 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:59:04 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:59:04 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:59:04 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:59:04 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:59:04 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:59:04 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:59:04 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:59:04 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:59:04 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:59:04 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:59:04 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 03:59:04 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 03:59:04 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 03:59:04 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:59:04 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:59:04 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:59:04 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 03:59:04 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:59:04 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 03:59:04 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 03:59:04 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 03:59:04 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:59:04 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:59:04 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:59:04 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 03:59:04 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:59:04 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 03:59:04 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 03:59:04 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 03:59:04 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:59:04 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:59:04 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:59:04 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 03:59:04 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:59:04 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 03:59:04 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 03:59:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 03:59:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 03:59:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 03:59:04 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 03:59:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 03:59:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 03:59:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 03:59:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 03:59:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:59:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:59:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:59:04 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 03:59:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:59:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:59:04 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 03:59:04 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 03:59:04 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 03:59:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:59:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:59:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:59:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 03:59:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:59:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:59:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:59:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:59:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:59:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:59:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:59:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:59:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:59:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:59:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:59:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:59:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:59:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:59:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:59:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:59:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:59:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:59:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:59:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:59:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:59:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:59:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:59:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:59:04 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 03:59:05 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 03:59:05 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 03:59:05 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 03:59:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:59:05 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 03:59:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:59:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:59:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:59:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:59:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:59:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:59:05 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:59:05 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:59:05 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 03:59:05 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:59:05 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:59:05 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:59:05 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:59:06 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 03:59:06 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 03:59:06 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:59:06 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:59:06 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:59:06 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:59:07 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 03:59:07 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 03:59:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:59:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:59:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:59:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:59:08 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 03:59:08 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:59:08 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 03:59:08 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:59:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:59:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:59:08 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 03:59:08 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 03:59:08 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 03:59:08 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 03:59:08 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 03:59:08 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 03:59:08 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 03:59:08 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 03:59:08 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 03:59:08 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 03:59:08 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 03:59:08 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 03:59:08 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:59:08 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:59:08 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:59:08 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:59:08 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 03:59:09 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 03:59:09 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 03:59:09 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:59:09 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:59:09 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:59:09 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:59:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:59:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:59:09 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:59:09 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:59:09 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:59:09 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:59:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:59:09 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:59:09 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:59:09 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:59:09 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:59:09 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:59:09 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:59:09 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 03:59:14 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:59:14 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:59:14 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:59:14 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:59:14 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:59:14 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:59:14 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:59:14 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:59:14 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:59:14 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:59:14 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 03:59:14 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 03:59:14 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 03:59:14 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:59:14 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:59:14 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:59:14 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 03:59:14 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:59:14 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 03:59:14 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 03:59:14 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 03:59:14 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:59:14 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:59:14 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:59:14 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 03:59:14 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:59:14 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 03:59:14 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 03:59:14 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 03:59:14 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:59:14 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:59:14 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:59:14 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 03:59:14 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:59:14 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 03:59:14 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 03:59:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 03:59:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 03:59:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 03:59:14 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 03:59:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 03:59:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 03:59:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 03:59:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:59:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 03:59:14 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 03:59:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:59:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:59:14 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 03:59:14 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 03:59:14 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 03:59:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:59:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:59:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:59:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 03:59:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:59:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:59:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:59:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:59:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:59:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:59:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:59:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:59:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:59:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:59:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:59:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:59:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:59:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:59:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:59:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:59:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:59:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:59:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:59:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:59:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:59:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:59:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:59:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:59:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:59:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:59:14 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 03:59:15 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 03:59:15 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 03:59:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:59:15 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 03:59:15 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 03:59:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:59:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:59:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:59:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:59:15 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:59:15 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:59:15 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:59:15 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:59:15 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:59:15 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:59:15 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 03:59:20 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:59:20 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:59:20 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:59:20 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:59:20 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:59:20 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:59:20 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:59:20 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:59:20 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:59:20 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:59:20 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 03:59:20 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 03:59:20 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 03:59:20 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:59:20 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:59:20 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:59:20 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 03:59:20 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:59:20 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 03:59:20 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 03:59:20 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 03:59:20 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:59:20 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:59:20 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:59:20 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 03:59:20 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:59:20 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 03:59:20 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 03:59:20 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 03:59:20 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:59:20 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:59:20 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:59:20 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 03:59:20 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:59:20 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 03:59:20 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 03:59:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 03:59:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 03:59:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 03:59:20 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 03:59:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 03:59:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 03:59:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 03:59:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:59:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 03:59:20 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 03:59:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:59:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:59:20 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 03:59:20 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 03:59:20 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 03:59:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:59:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:59:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:59:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 03:59:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:59:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:59:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:59:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:59:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:59:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:59:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:59:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:59:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:59:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:59:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:59:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:59:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:59:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:59:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:59:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:59:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:59:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:59:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:59:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:59:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:59:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:59:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:59:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:59:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:59:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:59:20 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 03:59:21 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 03:59:21 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 03:59:21 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 03:59:21 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 03:59:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:59:21 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 03:59:21 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:59:21 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:59:21 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:59:21 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:59:22 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 03:59:22 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 03:59:22 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:59:22 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:59:22 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:59:22 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:59:23 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 03:59:23 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 03:59:23 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:59:23 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:59:23 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:59:23 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:59:24 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 03:59:24 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 03:59:24 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:59:24 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:59:24 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:59:24 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:59:25 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 03:59:25 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 03:59:25 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:59:25 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:59:25 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:59:25 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:59:26 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 03:59:26 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 03:59:27 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 03:59:27 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 03:59:27 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 03:59:28 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 03:59:28 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 03:59:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:59:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:59:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:59:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:59:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:59:29 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:59:29 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:59:29 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:59:29 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 03:59:29 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1832 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:59:29 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:59:29 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:59:29 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:59:29 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1832 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:59:29 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1832 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:59:29 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1832 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:59:29 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1833 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:59:29 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1833 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:59:29 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1833 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:59:29 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1833 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:59:29 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1833 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:59:29 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1833 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:59:29 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1833 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:59:29 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1833 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:59:34 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:59:34 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:59:34 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:59:34 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:59:34 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:59:34 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:59:34 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:59:34 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:59:34 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:59:34 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:59:34 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 03:59:34 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 03:59:34 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 03:59:34 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:59:34 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:59:34 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:59:34 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 03:59:34 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:59:34 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 03:59:34 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 03:59:34 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 03:59:34 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:59:34 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:59:34 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:59:34 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 03:59:34 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:59:34 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 03:59:34 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 03:59:34 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 03:59:34 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:59:34 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:59:34 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:59:34 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 03:59:34 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:59:34 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 03:59:34 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 03:59:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 03:59:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 03:59:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 03:59:34 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 03:59:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 03:59:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 03:59:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 03:59:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 03:59:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:59:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:59:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:59:34 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 03:59:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:59:34 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 03:59:34 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 03:59:34 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 03:59:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:59:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:59:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:59:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 03:59:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:59:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:59:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:59:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:59:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:59:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:59:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:59:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:59:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:59:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:59:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:59:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:59:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:59:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:59:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:59:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:59:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:59:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:59:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:59:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:59:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:59:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:59:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:59:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:59:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:59:34 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 03:59:34 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 03:59:34 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 03:59:34 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 03:59:34 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 03:59:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:59:35 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 03:59:35 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:59:35 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:59:35 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:59:35 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:59:35 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 03:59:36 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 03:59:36 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:59:36 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:59:36 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:59:36 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:59:36 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 03:59:37 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 03:59:37 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:59:37 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:59:37 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:59:37 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:59:37 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 03:59:38 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 03:59:38 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:59:38 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:59:38 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:59:38 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:59:38 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 03:59:39 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 03:59:39 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:59:39 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:59:39 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:59:39 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:59:39 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 03:59:40 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 03:59:40 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 03:59:41 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 03:59:41 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 03:59:42 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 03:59:42 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 03:59:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:59:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:59:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:59:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:59:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:59:42 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:59:42 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:59:42 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:59:42 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:59:42 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:59:42 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 03:59:42 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:59:47 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:59:47 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:59:47 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:59:47 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:59:47 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:59:47 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:59:47 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:59:47 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:59:47 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:59:47 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:59:47 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 03:59:47 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 03:59:47 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 03:59:47 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:59:47 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:59:47 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:59:47 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 03:59:47 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:59:47 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 03:59:48 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 03:59:48 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 03:59:48 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:59:48 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:59:48 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:59:48 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 03:59:48 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:59:48 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 03:59:48 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 03:59:48 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 03:59:48 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:59:48 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:59:48 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:59:48 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 03:59:48 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:59:48 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 03:59:48 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 03:59:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 03:59:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 03:59:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 03:59:48 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 03:59:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 03:59:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 03:59:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 03:59:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:59:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 03:59:48 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 03:59:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:59:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:59:48 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 03:59:48 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 03:59:48 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 03:59:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:59:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:59:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:59:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 03:59:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:59:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:59:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:59:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:59:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:59:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:59:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:59:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:59:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:59:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:59:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:59:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:59:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:59:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:59:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:59:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:59:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:59:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:59:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:59:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:59:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:59:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:59:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:59:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:59:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:59:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:59:48 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 03:59:48 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 03:59:48 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 03:59:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:59:48 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 03:59:48 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 03:59:48 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 03:59:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:59:49 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:59:49 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:59:49 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:59:49 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 03:59:49 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 03:59:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:59:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:59:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:59:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:59:50 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 03:59:50 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 03:59:51 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:59:51 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:59:51 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:59:51 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:59:51 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 03:59:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:59:51 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:59:51 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:59:51 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:59:51 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:59:51 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:59:51 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:59:51 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:59:51 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:59:51 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:59:51 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:59:51 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 03:59:56 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:59:56 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:59:56 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:59:56 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:59:56 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:59:56 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:59:56 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:59:56 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:59:56 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:59:56 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 03:59:56 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 03:59:56 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 03:59:56 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 03:59:56 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:59:56 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:59:56 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:59:56 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 03:59:56 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 03:59:56 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 03:59:56 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 03:59:56 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 03:59:56 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:59:56 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:59:56 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:59:56 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 03:59:56 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 03:59:56 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 03:59:56 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 03:59:56 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 03:59:56 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:59:56 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 03:59:56 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:59:56 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 03:59:56 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 03:59:56 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 03:59:56 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 03:59:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 03:59:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 03:59:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 03:59:56 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 03:59:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 03:59:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 03:59:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 03:59:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 03:59:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:59:56 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 03:59:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:59:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:59:56 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 03:59:56 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 03:59:56 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 03:59:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:59:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:59:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:59:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 03:59:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:59:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:59:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:59:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:59:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:59:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:59:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:59:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:59:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:59:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:59:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:59:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:59:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:59:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:59:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:59:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:59:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:59:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:59:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:59:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 03:59:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:59:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:59:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:59:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 03:59:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 03:59:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 03:59:56 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 03:59:57 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 03:59:57 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 03:59:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:59:57 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 03:59:57 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 03:59:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:59:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:59:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 03:59:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:59:57 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:59:57 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:59:57 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 03:59:57 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 03:59:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:59:57 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 03:59:57 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 03:59:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:59:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:59:57 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 03:59:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 03:59:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 03:59:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 03:59:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 03:59:57 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 03:59:57 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 03:59:57 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 03:59:57 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 03:59:57 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 03:59:57 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 03:59:57 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 03:59:57 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 03:59:57 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 03:59:57 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 03:59:57 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 03:59:57 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=211 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:59:57 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=211 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:59:57 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=211 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:59:57 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=211 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:59:57 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=211 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 03:59:57 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=211 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:00:02 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:00:02 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:00:02 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:00:02 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:00:02 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:00:02 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:00:02 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:00:02 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:00:02 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:00:02 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:00:02 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:00:02 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:00:02 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:00:02 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:00:02 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:00:02 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:00:02 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:00:02 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:00:02 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:00:02 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:00:02 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:00:02 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:00:02 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:00:02 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:00:02 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:00:02 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:00:02 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:00:02 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:00:02 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:00:02 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:00:02 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:00:02 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:00:02 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:00:02 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:00:02 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:00:02 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:00:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:00:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:00:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:00:02 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:00:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:00:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:00:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:00:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:00:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:00:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:00:02 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:00:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:00:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:00:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:00:02 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:00:02 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:00:02 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:00:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:00:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:00:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:00:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:00:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:00:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:00:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:00:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:00:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:00:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:00:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:00:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:00:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:00:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:00:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:00:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:00:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:00:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:00:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:00:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:00:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:00:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:00:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:00:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:00:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:00:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:00:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:00:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:00:02 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:00:03 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:00:03 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:00:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:00:03 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:00:03 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:00:03 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:00:03 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:00:03 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:00:03 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:00:03 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:00:03 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:00:03 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:00:03 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:00:03 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:00:03 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:00:03 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:00:08 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:00:08 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:00:08 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:00:08 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:00:08 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:00:08 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:00:08 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:00:08 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:00:08 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:00:08 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:00:08 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:00:08 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:00:08 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:00:08 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:00:08 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:00:08 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:00:08 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:00:08 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:00:08 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:00:08 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:00:08 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:00:08 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:00:08 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:00:08 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:00:08 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:00:08 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:00:08 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:00:08 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:00:08 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:00:08 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:00:08 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:00:08 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:00:08 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:00:08 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:00:08 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:00:08 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:00:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:00:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:00:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:00:08 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:00:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:00:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:00:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:00:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:00:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:00:08 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:00:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:00:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:00:08 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:00:08 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:00:08 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:00:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:00:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:00:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:00:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:00:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:00:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:00:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:00:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:00:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:00:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:00:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:00:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:00:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:00:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:00:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:00:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:00:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:00:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:00:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:00:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:00:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:00:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:00:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:00:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:00:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:00:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:00:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:00:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:00:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:00:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:00:08 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:00:08 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:00:08 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:00:08 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:00:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:00:08 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:00:09 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:00:09 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:00:09 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:00:09 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:00:09 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:00:09 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:00:10 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:00:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:00:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:00:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:00:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:00:10 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 04:00:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:00:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:00:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:00:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:00:10 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:00:10 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:00:10 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:00:10 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:00:10 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:00:10 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:00:10 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:00:10 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=546 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:00:10 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=546 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:00:10 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=546 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:00:10 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=546 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:00:10 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=546 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:00:10 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=546 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:00:15 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:00:15 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:00:15 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:00:15 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:00:15 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:00:15 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:00:15 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:00:15 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:00:15 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:00:15 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:00:15 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:00:15 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:00:15 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:00:15 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:00:15 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:00:15 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:00:15 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:00:15 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:00:15 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:00:15 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:00:15 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:00:15 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:00:15 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:00:15 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:00:15 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:00:15 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:00:15 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:00:15 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:00:15 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:00:15 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:00:15 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:00:15 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:00:15 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:00:15 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:00:15 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:00:15 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:00:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:00:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:00:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:00:15 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:00:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:00:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:00:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:00:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:00:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:00:15 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:00:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:00:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:00:15 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:00:15 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:00:15 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:00:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:00:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:00:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:00:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:00:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:00:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:00:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:00:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:00:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:00:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:00:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:00:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:00:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:00:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:00:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:00:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:00:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:00:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:00:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:00:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:00:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:00:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:00:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:00:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:00:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:00:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:00:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:00:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:00:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:00:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:00:15 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:00:16 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:00:16 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:00:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:00:16 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:00:16 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:00:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:00:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:00:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:00:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:00:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:00:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:00:16 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:00:16 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:00:16 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:00:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:00:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:00:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:00:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:00:17 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:00:17 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:00:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:00:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:00:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:00:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:00:18 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 04:00:18 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 04:00:18 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:00:18 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:00:18 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:00:18 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:00:19 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 04:00:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:00:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:00:19 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:00:19 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:00:19 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:00:19 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:00:19 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:00:19 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:00:19 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:00:19 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:00:19 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:00:19 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:00:19 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:00:24 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:00:24 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:00:24 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:00:24 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:00:24 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:00:24 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:00:24 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:00:24 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:00:24 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:00:24 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:00:24 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:00:24 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:00:24 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:00:24 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:00:24 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:00:24 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:00:24 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:00:24 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:00:24 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:00:24 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:00:24 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:00:24 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:00:24 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:00:24 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:00:24 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:00:24 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:00:24 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:00:24 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:00:24 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:00:24 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:00:24 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:00:24 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:00:24 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:00:24 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:00:24 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:00:24 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:00:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:00:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:00:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:00:24 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:00:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:00:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:00:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:00:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:00:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:00:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:00:24 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:00:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:00:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:00:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:00:24 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:00:24 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:00:24 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:00:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:00:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:00:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:00:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:00:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:00:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:00:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:00:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:00:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:00:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:00:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:00:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:00:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:00:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:00:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:00:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:00:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:00:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:00:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:00:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:00:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:00:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:00:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:00:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:00:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:00:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:00:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:00:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:00:24 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:00:24 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:00:24 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:00:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:00:24 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:00:24 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:00:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:00:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:00:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:00:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:00:24 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:00:24 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:00:24 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:00:24 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:00:25 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:00:25 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:00:25 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:00:25 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:00:25 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:00:25 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:00:26 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:00:26 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:00:26 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:00:26 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:00:26 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:00:26 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 04:00:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:00:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:00:26 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:00:26 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:00:26 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:00:26 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:00:26 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:00:26 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:00:26 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:00:26 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:00:26 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:00:26 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:00:26 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:00:26 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=568 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:00:26 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=568 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:00:26 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=568 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:00:26 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=568 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:00:26 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=568 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:00:26 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=568 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:00:31 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:00:31 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:00:31 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:00:31 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:00:31 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:00:31 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:00:31 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:00:31 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:00:31 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:00:31 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:00:31 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:00:31 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:00:31 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:00:31 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:00:31 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:00:31 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:00:31 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:00:31 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:00:31 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:00:31 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:00:31 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:00:31 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:00:31 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:00:31 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:00:31 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:00:31 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:00:31 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:00:31 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:00:31 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:00:31 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:00:31 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:00:31 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:00:31 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:00:31 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:00:31 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:00:31 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:00:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:00:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:00:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:00:31 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:00:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:00:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:00:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:00:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:00:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:00:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:00:31 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:00:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:00:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:00:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:00:31 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:00:31 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:00:31 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:00:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:00:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:00:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:00:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:00:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:00:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:00:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:00:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:00:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:00:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:00:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:00:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:00:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:00:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:00:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:00:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:00:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:00:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:00:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:00:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:00:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:00:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:00:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:00:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:00:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:00:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:00:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:00:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:00:31 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:00:32 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:00:32 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:00:32 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:00:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:00:32 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:00:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:00:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:00:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:00:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:00:32 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:00:32 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:00:32 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:00:32 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:00:32 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:00:32 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:00:32 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:00:32 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:00:32 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:00:33 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:00:33 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:00:33 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:00:33 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:00:33 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:00:33 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:00:34 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 04:00:34 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 04:00:34 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:00:34 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:00:34 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:00:34 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:00:35 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 04:00:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:00:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:00:35 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:00:35 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:00:35 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:00:35 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:00:35 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:00:35 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:00:35 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:00:35 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:00:35 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:00:35 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=720 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:00:35 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:00:35 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:00:35 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=720 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:00:35 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=720 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:00:35 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=721 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:00:35 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=721 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:00:35 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=721 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:00:35 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=721 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:00:35 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=721 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:00:35 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=721 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:00:35 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=721 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:00:35 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=721 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:00:40 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:00:40 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:00:40 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:00:40 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:00:40 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:00:40 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:00:40 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:00:40 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:00:40 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:00:40 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:00:40 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:00:40 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:00:40 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:00:40 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:00:40 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:00:40 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:00:40 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:00:40 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:00:40 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:00:40 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:00:40 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:00:40 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:00:40 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:00:40 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:00:40 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:00:40 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:00:40 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:00:40 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:00:40 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:00:40 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:00:40 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:00:40 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:00:40 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:00:40 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:00:40 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:00:40 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:00:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:00:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:00:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:00:40 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:00:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:00:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:00:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:00:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:00:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:00:40 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:00:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:00:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:00:40 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:00:40 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:00:40 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:00:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:00:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:00:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:00:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:00:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:00:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:00:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:00:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:00:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:00:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:00:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:00:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:00:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:00:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:00:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:00:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:00:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:00:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:00:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:00:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:00:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:00:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:00:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:00:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:00:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:00:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:00:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:00:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:00:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:00:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:00:40 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:00:40 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:00:40 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:00:40 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:00:40 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:00:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:00:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:00:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:00:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:00:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:00:40 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:00:40 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:00:40 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:00:40 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:00:41 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:00:41 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:00:41 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:00:41 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:00:41 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:00:41 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:00:42 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:00:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:00:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:00:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:00:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:00:42 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 04:00:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:00:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:00:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:00:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:00:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:00:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:00:42 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:00:42 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:00:42 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:00:42 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:00:42 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=567 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:00:42 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:00:42 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:00:42 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:00:42 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=567 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:00:42 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=567 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:00:42 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=567 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:00:42 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=567 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:00:47 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:00:47 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:00:47 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:00:47 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:00:47 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:00:47 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:00:47 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:00:48 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:00:48 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:00:48 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:00:48 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:00:48 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:00:48 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:00:48 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:00:48 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:00:48 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:00:48 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:00:48 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:00:48 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:00:48 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:00:48 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:00:48 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:00:48 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:00:48 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:00:48 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:00:48 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:00:48 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:00:48 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:00:48 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:00:48 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:00:48 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:00:48 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:00:48 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:00:48 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:00:48 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:00:48 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:00:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:00:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:00:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:00:48 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:00:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:00:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:00:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:00:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:00:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:00:48 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:00:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:00:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:00:48 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:00:48 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:00:48 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:00:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:00:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:00:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:00:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:00:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:00:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:00:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:00:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:00:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:00:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:00:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:00:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:00:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:00:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:00:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:00:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:00:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:00:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:00:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:00:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:00:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:00:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:00:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:00:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:00:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:00:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:00:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:00:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:00:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:00:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:00:48 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:00:48 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:00:48 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:00:48 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:00:48 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:00:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:00:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:00:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:00:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:00:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:00:48 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:00:48 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:00:48 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:00:48 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:00:48 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:00:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:00:49 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:00:49 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:00:49 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:00:49 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:00:49 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:00:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:00:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:00:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:00:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:00:50 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 04:00:50 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 04:00:51 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:00:51 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:00:51 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:00:51 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:00:51 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 04:00:51 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 04:00:52 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:00:52 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:00:52 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:00:52 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:00:52 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 04:00:52 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:00:52 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:00:52 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:00:52 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:00:52 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:00:52 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:00:52 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:00:52 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:00:52 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:00:52 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:00:52 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:00:52 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:00:52 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:00:52 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=924 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:00:52 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=924 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:00:52 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=924 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:00:52 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=924 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:00:52 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=924 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:00:52 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=925 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:00:52 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=925 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:00:52 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=925 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:00:52 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=925 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:00:52 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=925 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:00:52 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=925 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:00:52 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=925 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:00:52 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=925 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:00:57 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:00:57 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:00:57 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:00:57 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:00:57 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:00:57 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:00:57 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:00:57 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:00:57 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:00:57 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:00:57 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:00:57 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:00:57 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:00:57 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:00:57 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:00:57 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:00:57 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:00:57 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:00:57 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:00:57 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:00:57 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:00:57 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:00:57 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:00:57 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:00:57 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:00:57 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:00:57 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:00:57 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:00:57 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:00:57 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:00:57 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:00:57 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:00:57 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:00:57 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:00:57 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:00:57 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:00:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:00:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:00:57 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:00:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:00:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:00:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:00:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:00:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:00:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:00:57 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:00:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:00:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:00:57 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:00:57 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:00:57 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:00:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:00:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:00:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:00:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:00:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:00:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:00:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:00:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:00:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:00:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:00:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:00:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:00:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:00:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:00:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:00:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:00:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:00:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:00:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:00:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:00:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:00:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:00:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:00:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:00:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:00:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:00:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:00:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:00:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:00:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:00:57 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:00:57 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:00:57 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:00:57 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:00:57 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:00:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:00:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:00:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:00:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:00:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:00:57 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:00:57 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:00:57 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:00:57 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:00:58 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:00:58 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:00:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:00:58 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:00:58 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:00:58 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:00:59 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:00:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:00:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:00:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:00:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:00:59 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 04:01:00 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 04:01:00 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:01:00 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:01:00 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:01:00 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:01:00 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 04:01:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:01:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:01:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:01:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:01:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:01:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:01:01 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:01:01 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:01:01 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:01:01 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:01:01 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:01:01 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:01:01 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:01:01 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=772 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:01:01 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=772 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:01:01 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=772 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:01:01 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=772 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:01:01 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=772 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:01:01 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=772 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:01:01 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=772 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:01:06 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:01:06 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:01:06 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:01:06 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:01:06 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:01:06 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:01:06 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:01:06 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:01:06 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:01:06 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:01:06 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:01:06 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:01:06 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:01:06 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:01:06 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:01:06 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:01:06 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:01:06 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:01:06 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:01:06 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:01:06 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:01:06 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:01:06 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:01:06 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:01:06 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:01:06 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:01:06 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:01:06 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:01:06 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:01:06 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:01:06 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:01:06 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:01:06 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:01:06 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:01:06 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:01:06 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:01:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:01:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:01:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:01:06 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:01:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:01:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:01:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:01:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:01:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:01:06 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:01:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:01:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:01:06 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:01:06 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:01:06 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:01:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:01:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:01:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:01:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:01:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:01:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:01:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:01:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:01:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:01:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:01:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:01:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:01:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:01:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:01:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:01:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:01:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:01:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:01:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:01:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:01:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:01:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:01:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:01:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:01:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:01:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:01:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:01:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:01:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:01:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:01:06 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:01:06 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:01:06 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:01:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:01:06 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:01:06 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:01:07 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:01:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:01:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:01:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:01:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:01:07 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:01:07 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:01:08 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:01:08 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:01:08 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:01:08 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:01:08 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 04:01:08 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:01:08 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:01:08 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:01:08 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:01:08 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:01:08 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:01:08 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:01:08 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:01:08 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:01:08 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:01:08 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:01:08 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=545 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:01:08 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=545 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:01:08 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=545 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:01:08 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=545 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:01:08 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=545 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:01:08 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=545 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:01:08 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=545 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:01:13 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:01:13 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:01:13 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:01:13 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:01:13 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:01:13 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:01:13 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:01:13 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:01:13 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:01:13 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:01:13 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:01:13 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:01:13 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:01:13 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:01:13 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:01:13 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:01:13 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:01:13 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:01:13 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:01:13 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:01:13 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:01:13 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:01:13 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:01:13 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:01:13 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:01:13 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:01:13 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:01:13 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:01:13 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:01:13 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:01:13 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:01:13 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:01:13 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:01:13 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:01:13 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:01:13 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:01:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:01:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:01:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:01:13 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:01:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:01:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:01:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:01:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:01:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:01:13 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:01:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:01:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:01:13 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:01:13 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:01:13 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:01:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:01:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:01:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:01:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:01:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:01:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:01:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:01:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:01:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:01:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:01:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:01:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:01:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:01:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:01:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:01:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:01:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:01:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:01:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:01:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:01:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:01:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:01:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:01:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:01:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:01:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:01:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:01:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:01:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:01:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:01:13 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:01:14 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:01:14 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:01:14 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:01:14 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:01:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:01:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:01:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:01:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:01:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:01:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:01:14 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:01:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:01:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:01:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:01:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:01:15 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:01:15 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:01:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:01:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:01:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:01:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:01:16 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 04:01:16 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 04:01:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:01:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:01:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:01:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:01:17 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 04:01:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:01:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:01:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:01:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:01:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:01:17 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:01:17 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:01:17 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:01:17 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:01:17 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:01:17 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:01:17 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:01:17 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=763 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:01:17 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=763 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:01:17 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=763 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:01:17 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=763 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:01:17 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=763 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:01:17 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=763 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:01:17 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=763 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:01:17 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=763 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:01:22 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:01:22 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:01:22 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:01:22 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:01:22 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:01:22 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:01:22 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:01:22 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:01:22 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:01:22 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:01:22 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:01:22 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:01:22 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:01:22 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:01:22 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:01:22 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:01:22 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:01:22 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:01:22 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:01:22 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:01:22 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:01:22 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:01:22 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:01:22 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:01:22 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:01:22 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:01:22 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:01:22 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:01:22 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:01:22 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:01:22 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:01:22 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:01:22 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:01:22 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:01:22 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:01:22 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:01:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:01:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:01:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:01:22 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:01:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:01:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:01:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:01:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:01:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:01:22 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:01:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:01:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:01:22 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:01:22 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:01:22 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:01:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:01:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:01:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:01:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:01:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:01:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:01:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:01:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:01:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:01:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:01:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:01:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:01:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:01:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:01:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:01:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:01:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:01:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:01:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:01:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:01:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:01:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:01:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:01:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:01:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:01:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:01:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:01:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:01:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:01:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:01:22 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:01:22 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:01:22 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:01:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:01:22 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:01:22 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:01:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:01:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:01:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:01:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:01:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:01:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:01:22 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:01:22 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:01:22 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:01:22 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:01:22 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:01:22 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:01:22 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:01:22 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:01:22 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:01:22 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:01:22 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:01:22 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=124 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:01:22 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=124 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:01:22 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=124 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:01:22 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=124 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:01:22 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=124 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:01:22 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=124 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:01:22 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=124 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:01:22 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=125 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:01:22 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=125 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:01:22 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=125 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:01:22 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=125 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:01:22 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=125 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:01:22 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=125 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:01:22 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=125 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:01:22 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=125 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:01:27 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:01:27 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:01:27 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:01:27 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:01:27 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:01:27 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:01:27 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:01:27 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:01:27 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:01:27 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:01:27 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:01:27 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:01:27 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:01:27 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:01:27 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:01:27 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:01:27 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:01:27 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:01:27 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:01:27 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:01:27 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:01:27 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:01:27 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:01:27 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:01:27 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:01:27 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:01:27 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:01:27 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:01:27 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:01:27 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:01:27 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:01:27 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:01:27 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:01:27 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:01:27 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:01:27 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:01:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:01:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:01:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:01:27 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:01:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:01:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:01:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:01:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:01:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:01:27 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:01:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:01:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:01:27 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:01:27 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:01:27 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:01:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:01:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:01:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:01:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:01:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:01:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:01:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:01:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:01:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:01:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:01:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:01:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:01:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:01:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:01:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:01:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:01:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:01:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:01:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:01:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:01:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:01:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:01:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:01:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:01:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:01:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:01:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:01:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:01:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:01:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:01:27 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:01:28 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:01:28 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:01:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:01:28 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:01:28 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:01:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:01:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:01:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:01:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:01:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:01:28 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:01:28 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:01:28 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:01:28 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:01:28 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:01:29 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:01:29 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:01:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:01:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:01:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:01:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:01:30 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 04:01:30 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 04:01:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:01:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:01:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:01:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:01:31 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 04:01:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:01:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:01:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:01:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:01:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:01:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:01:31 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:01:31 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:01:31 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:01:31 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:01:31 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:01:31 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:01:31 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:01:31 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=765 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:01:31 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=765 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:01:31 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=765 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:01:31 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=765 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:01:31 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=765 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:01:31 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=766 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:01:31 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=766 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:01:31 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=766 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:01:31 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=766 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:01:31 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=766 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:01:31 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=766 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:01:31 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=766 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:01:31 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=766 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:01:36 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:01:36 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:01:36 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:01:36 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:01:36 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:01:36 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:01:36 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:01:36 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:01:36 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:01:36 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:01:36 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:01:36 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:01:36 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:01:36 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:01:36 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:01:36 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:01:36 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:01:36 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:01:36 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:01:36 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:01:36 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:01:36 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:01:36 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:01:36 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:01:36 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:01:36 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:01:36 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:01:36 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:01:36 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:01:36 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:01:36 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:01:36 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:01:36 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:01:36 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:01:36 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:01:36 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:01:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:01:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:01:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:01:36 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:01:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:01:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:01:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:01:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:01:36 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:01:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:01:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:01:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:01:36 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:01:36 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:01:36 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:01:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:01:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:01:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:01:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:01:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:01:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:01:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:01:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:01:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:01:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:01:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:01:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:01:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:01:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:01:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:01:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:01:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:01:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:01:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:01:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:01:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:01:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:01:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:01:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:01:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:01:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:01:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:01:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:01:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:01:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:01:36 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:01:37 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:01:37 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:01:37 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:01:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:01:37 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:01:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:01:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:01:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:01:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:01:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:01:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:01:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:01:37 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:01:37 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:01:37 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:01:37 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:01:37 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:01:37 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:01:37 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:01:37 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:01:37 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:01:37 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:01:37 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=126 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:01:37 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:01:37 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=126 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:01:37 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=126 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:01:37 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=126 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:01:37 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=127 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:01:37 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=127 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:01:37 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=127 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:01:37 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=127 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:01:37 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=127 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:01:37 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=127 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:01:37 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=127 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:01:37 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=127 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:01:42 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:01:42 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:01:42 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:01:42 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:01:42 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:01:42 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:01:42 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:01:42 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:01:42 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:01:42 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:01:42 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:01:42 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:01:42 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:01:42 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:01:42 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:01:42 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:01:42 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:01:42 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:01:42 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:01:42 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:01:42 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:01:42 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:01:42 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:01:42 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:01:42 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:01:42 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:01:42 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:01:42 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:01:42 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:01:42 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:01:42 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:01:42 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:01:42 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:01:42 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:01:42 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:01:42 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:01:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:01:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:01:42 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:01:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:01:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:01:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:01:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:01:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:01:42 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:01:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:01:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:01:42 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:01:42 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:01:42 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:01:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:01:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:01:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:01:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:01:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:01:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:01:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:01:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:01:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:01:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:01:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:01:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:01:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:01:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:01:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:01:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:01:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:01:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:01:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:01:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:01:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:01:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:01:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:01:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:01:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:01:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:01:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:01:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:01:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:01:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:01:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:01:42 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:01:42 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:01:42 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:01:42 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:01:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:01:42 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:01:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:01:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:01:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:01:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:01:42 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:01:42 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:01:42 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:01:42 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:01:42 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:01:42 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:01:42 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:01:42 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=112 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:01:42 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=112 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:01:42 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=112 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:01:42 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=112 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:01:42 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=112 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:01:42 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=112 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:01:47 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:01:47 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:01:47 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:01:47 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:01:47 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:01:47 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:01:47 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:01:47 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:01:47 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:01:47 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:01:47 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:01:47 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:01:47 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:01:47 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:01:47 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:01:47 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:01:47 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:01:47 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:01:47 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:01:47 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:01:47 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:01:47 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:01:47 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:01:47 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:01:47 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:01:47 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:01:47 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:01:47 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:01:47 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:01:47 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:01:47 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:01:47 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:01:47 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:01:47 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:01:47 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:01:47 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:01:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:01:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:01:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:01:47 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:01:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:01:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:01:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:01:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:01:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:01:47 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:01:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:01:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:01:47 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:01:47 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:01:47 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:01:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:01:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:01:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:01:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:01:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:01:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:01:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:01:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:01:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:01:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:01:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:01:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:01:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:01:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:01:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:01:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:01:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:01:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:01:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:01:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:01:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:01:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:01:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:01:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:01:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:01:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:01:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:01:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:01:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:01:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:01:47 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:01:48 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:01:48 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:01:48 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:01:48 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:01:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:01:48 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:01:48 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:01:48 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:01:48 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:01:48 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:01:48 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:01:48 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:01:48 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:01:48 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:01:48 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=113 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:01:48 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:01:48 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:01:48 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=113 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:01:48 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=113 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:01:48 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=113 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:01:48 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=113 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:01:48 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=113 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:01:48 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=114 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:01:48 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=114 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:01:48 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=114 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:01:48 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=114 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:01:48 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=114 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:01:48 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=114 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:01:48 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=114 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:01:48 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=114 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:01:53 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:01:53 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:01:53 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:01:53 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:01:53 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:01:53 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:01:53 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:01:53 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:01:53 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:01:53 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:01:53 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:01:53 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:01:53 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:01:53 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:01:53 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:01:53 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:01:53 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:01:53 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:01:53 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:01:53 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:01:53 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:01:53 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:01:53 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:01:53 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:01:53 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:01:53 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:01:53 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:01:53 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:01:53 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:01:53 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:01:53 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:01:53 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:01:53 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:01:53 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:01:53 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:01:53 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:01:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:01:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:01:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:01:53 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:01:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:01:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:01:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:01:53 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:01:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:01:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:01:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:01:53 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:01:53 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:01:53 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:01:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:01:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:01:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:01:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:01:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:01:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:01:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:01:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:01:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:01:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:01:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:01:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:01:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:01:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:01:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:01:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:01:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:01:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:01:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:01:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:01:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:01:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:01:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:01:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:01:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:01:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:01:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:01:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:01:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:01:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:01:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:01:53 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:01:53 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:01:53 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:01:53 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:01:53 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:01:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:01:53 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:01:53 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:01:53 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:01:53 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:01:53 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:01:53 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:01:53 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:01:53 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:01:53 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:01:53 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:01:53 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:01:53 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=112 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:01:53 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=112 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:01:53 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=112 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:01:53 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=112 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:01:53 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=112 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:01:53 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=112 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:01:53 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=112 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:01:58 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:01:58 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:01:58 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:01:58 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:01:58 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:01:58 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:01:58 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:01:58 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:01:58 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:01:58 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:01:58 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:01:58 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:01:58 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:01:58 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:01:58 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:01:58 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:01:58 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:01:58 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:01:58 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:01:58 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:01:58 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:01:58 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:01:58 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:01:58 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:01:58 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:01:58 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:01:58 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:01:58 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:01:58 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:01:58 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:01:58 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:01:58 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:01:58 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:01:58 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:01:58 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:01:58 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:01:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:01:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:01:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:01:58 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:01:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:01:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:01:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:01:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:01:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:01:58 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:01:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:01:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:01:58 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:01:58 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:01:58 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:01:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:01:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:01:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:01:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:01:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:01:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:01:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:01:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:01:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:01:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:01:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:01:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:01:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:01:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:01:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:01:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:01:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:01:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:01:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:01:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:01:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:01:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:01:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:01:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:01:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:01:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:01:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:01:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:01:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:01:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:01:58 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:01:59 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:01:59 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:01:59 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:01:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:01:59 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:01:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:01:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:01:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:01:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:01:59 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:01:59 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:01:59 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:01:59 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:01:59 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:01:59 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:01:59 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:01:59 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=113 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:01:59 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=113 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:01:59 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=113 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:01:59 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=113 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:01:59 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=113 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:01:59 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=113 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:01:59 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=113 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:02:04 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:02:04 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:02:04 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:02:04 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:02:04 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:02:04 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:02:04 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:02:04 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:02:04 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:02:04 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:02:04 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:02:04 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:02:04 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:02:04 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:02:04 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:02:04 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:02:04 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:02:04 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:02:04 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:02:04 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:02:04 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:02:04 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:02:04 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:02:04 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:02:04 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:02:04 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:02:04 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:02:04 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:02:04 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:02:04 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:02:04 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:02:04 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:02:04 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:02:04 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:02:04 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:02:04 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:02:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:02:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:02:04 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:02:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:02:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:02:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:02:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:02:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:02:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:02:04 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:02:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:02:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:02:04 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:02:04 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:02:04 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:02:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:02:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:02:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:02:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:02:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:02:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:02:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:02:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:02:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:02:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:02:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:02:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:02:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:02:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:02:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:02:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:02:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:02:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:02:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:02:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:02:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:02:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:02:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:02:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:02:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:02:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:02:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:02:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:02:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:02:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:02:04 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:02:04 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:02:04 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:02:04 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:02:04 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:02:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:02:05 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:02:05 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:02:05 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:02:05 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:02:05 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:02:05 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:02:06 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:02:06 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:02:06 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:02:06 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:02:06 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:02:06 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 04:02:07 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 04:02:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:02:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:02:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:02:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:02:07 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 04:02:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:02:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:02:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:02:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:02:07 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:02:07 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:02:07 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:02:07 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:02:08 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 04:02:08 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:02:08 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:02:08 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:02:08 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:02:08 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 04:02:09 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 04:02:09 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:02:09 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:02:09 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:02:09 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:02:09 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 04:02:10 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 04:02:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:02:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:02:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:02:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:02:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:02:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:02:10 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:02:10 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:02:10 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:02:10 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:02:10 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:02:10 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1255 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:02:10 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:02:10 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:02:10 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1256 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:02:10 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1256 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:02:10 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1256 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:02:10 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1256 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:02:10 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1256 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:02:10 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1256 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:02:10 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1256 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:02:10 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1256 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:02:10 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1257 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:02:10 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1257 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:02:10 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1257 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:02:10 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1257 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:02:10 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1257 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:02:10 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1257 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:02:10 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1257 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:02:10 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1257 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:02:15 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:02:15 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:02:15 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:02:15 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:02:15 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:02:15 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:02:15 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:02:15 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:02:15 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:02:15 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:02:15 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:02:15 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:02:15 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:02:15 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:02:15 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:02:15 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:02:15 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:02:15 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:02:15 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:02:15 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:02:15 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:02:15 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:02:15 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:02:15 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:02:15 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:02:15 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:02:15 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:02:15 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:02:15 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:02:15 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:02:15 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:02:15 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:02:15 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:02:15 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:02:15 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:02:15 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:02:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:02:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:02:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:02:15 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:02:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:02:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:02:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:02:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:02:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:02:15 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:02:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:02:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:02:15 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:02:15 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:02:15 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:02:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:02:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:02:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:02:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:02:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:02:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:02:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:02:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:02:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:02:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:02:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:02:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:02:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:02:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:02:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:02:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:02:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:02:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:02:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:02:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:02:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:02:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:02:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:02:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:02:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:02:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:02:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:02:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:02:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:02:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:02:15 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:02:15 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:02:15 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:02:15 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:02:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:02:15 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:02:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:02:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:02:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:02:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:02:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:02:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:02:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:02:15 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:02:15 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:02:15 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:02:15 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:02:15 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:02:15 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:02:15 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:02:15 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=123 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:02:15 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=123 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:02:15 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=123 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:02:15 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=123 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:02:15 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=123 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:02:15 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=123 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:02:15 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=123 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:02:20 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:02:20 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:02:20 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:02:20 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:02:20 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:02:20 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:02:20 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:02:20 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:02:20 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:02:20 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:02:20 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:02:20 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:02:20 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:02:20 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:02:20 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:02:20 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:02:20 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:02:20 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:02:20 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:02:20 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:02:20 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:02:20 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:02:20 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:02:20 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:02:20 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:02:20 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:02:20 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:02:20 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:02:20 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:02:20 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:02:20 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:02:20 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:02:20 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:02:20 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:02:20 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:02:20 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:02:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:02:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:02:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:02:20 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:02:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:02:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:02:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:02:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:02:20 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:02:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:02:20 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:02:20 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:02:20 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:02:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:02:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:02:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:02:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:02:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:02:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:02:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:02:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:02:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:02:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:02:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:02:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:02:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:02:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:02:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:02:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:02:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:02:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:02:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:02:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:02:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:02:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:02:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:02:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:02:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:02:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:02:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:02:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:02:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:02:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:02:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:02:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:02:20 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:02:21 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:02:21 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:02:21 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:02:21 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:02:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:02:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:02:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:02:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:02:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:02:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:02:21 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:02:21 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:02:21 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:02:21 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:02:21 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:02:21 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:02:21 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:02:21 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:02:21 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:02:21 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:02:21 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:02:21 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=121 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:02:21 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=121 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:02:21 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=121 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:02:21 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=121 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:02:21 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=121 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:02:21 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=121 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:02:21 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=122 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:02:21 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=122 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:02:21 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=122 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:02:21 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=122 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:02:21 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=122 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:02:21 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=122 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:02:21 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=122 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:02:21 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=122 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:02:21 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=123 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:02:21 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=123 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:02:21 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=123 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:02:21 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=123 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:02:21 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=123 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:02:21 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=123 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:02:21 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=123 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:02:21 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=123 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:02:26 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:02:26 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:02:26 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:02:26 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:02:26 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:02:26 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:02:26 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:02:26 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:02:26 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:02:26 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:02:26 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:02:26 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:02:26 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:02:26 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:02:26 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:02:26 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:02:26 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:02:26 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:02:26 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:02:26 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:02:26 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:02:26 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:02:26 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:02:26 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:02:26 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:02:26 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:02:26 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:02:26 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:02:26 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:02:26 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:02:26 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:02:26 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:02:26 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:02:26 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:02:26 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:02:26 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:02:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:02:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:02:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:02:26 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:02:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:02:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:02:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:02:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:02:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:02:26 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:02:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:02:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:02:26 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:02:26 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:02:26 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:02:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:02:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:02:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:02:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:02:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:02:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:02:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:02:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:02:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:02:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:02:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:02:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:02:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:02:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:02:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:02:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:02:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:02:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:02:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:02:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:02:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:02:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:02:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:02:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:02:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:02:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:02:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:02:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:02:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:02:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:02:26 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:02:27 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:02:27 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:02:27 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:02:27 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:02:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:02:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:02:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:02:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:02:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:02:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:02:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:02:27 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:02:27 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:02:27 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:02:27 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:02:27 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:02:27 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:02:27 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:02:27 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:02:27 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:02:27 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:02:27 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=125 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:02:27 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:02:27 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=125 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:02:27 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=125 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:02:27 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=125 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:02:27 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=125 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:02:27 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=125 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:02:32 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:02:32 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:02:32 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:02:32 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:02:32 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:02:32 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:02:32 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:02:32 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:02:32 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:02:32 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:02:32 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:02:32 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:02:32 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:02:32 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:02:32 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:02:32 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:02:32 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:02:32 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:02:32 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:02:32 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:02:32 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:02:32 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:02:32 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:02:32 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:02:32 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:02:32 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:02:32 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:02:32 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:02:32 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:02:32 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:02:32 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:02:32 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:02:32 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:02:32 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:02:32 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:02:32 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:02:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:02:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:02:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:02:32 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:02:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:02:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:02:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:02:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:02:32 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:02:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:02:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:02:32 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:02:32 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:02:32 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:02:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:02:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:02:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:02:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:02:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:02:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:02:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:02:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:02:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:02:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:02:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:02:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:02:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:02:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:02:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:02:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:02:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:02:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:02:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:02:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:02:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:02:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:02:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:02:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:02:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:02:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:02:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:02:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:02:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:02:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:02:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:02:32 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:02:32 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:02:32 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:02:32 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:02:32 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:02:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:02:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:02:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:02:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:02:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:02:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:02:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:02:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:02:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:02:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:02:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:02:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:02:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:02:32 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:02:32 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:02:32 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:02:32 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:02:32 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:02:32 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:02:32 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:02:32 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:02:32 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:02:32 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=126 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:02:32 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:02:32 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:02:32 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=126 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:02:32 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=126 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:02:32 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=126 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:02:32 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=126 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:02:32 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=126 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:02:32 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=127 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:02:32 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=127 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:02:32 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=127 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:02:32 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=127 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:02:32 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=127 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:02:32 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=127 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:02:32 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=127 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:02:32 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=127 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:02:37 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:02:37 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:02:37 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:02:37 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:02:37 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:02:37 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:02:37 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:02:37 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:02:37 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:02:37 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:02:37 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:02:37 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:02:37 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:02:37 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:02:37 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:02:37 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:02:37 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:02:37 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:02:37 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:02:37 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:02:37 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:02:37 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:02:37 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:02:37 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:02:37 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:02:37 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:02:37 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:02:37 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:02:37 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:02:37 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:02:37 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:02:37 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:02:37 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:02:37 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:02:37 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:02:37 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:02:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:02:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:02:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:02:37 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:02:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:02:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:02:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:02:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:02:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:02:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:02:37 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:02:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:02:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:02:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:02:37 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:02:37 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:02:37 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:02:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:02:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:02:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:02:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:02:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:02:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:02:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:02:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:02:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:02:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:02:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:02:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:02:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:02:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:02:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:02:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:02:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:02:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:02:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:02:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:02:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:02:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:02:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:02:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:02:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:02:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:02:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:02:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:02:37 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:02:38 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:02:38 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:02:38 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:02:38 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:02:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:02:38 [DEBUG] fake_trx.py:376 (BTS@172.18.127.20:5700) Recv FAKE_TRXC_DELAY cmd
2025-04-27 04:02:38 [INFO] fake_trx.py:379 (BTS@172.18.127.20:5700) Artificial TRXC delay set to 200
2025-04-27 04:02:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD FAKE_TRXC_DELAY
2025-04-27 04:02:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:02:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:02:38 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:02:38 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:02:38 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:02:38 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:02:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:02:39 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:02:39 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:02:39 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:02:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:02:39 [DEBUG] fake_trx.py:376 (BTS@172.18.127.20:5700) Recv FAKE_TRXC_DELAY cmd
2025-04-27 04:02:39 [INFO] fake_trx.py:379 (BTS@172.18.127.20:5700) Artificial TRXC delay set to 0
2025-04-27 04:02:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD FAKE_TRXC_DELAY
2025-04-27 04:02:39 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:02:39 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:02:39 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:02:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:02:39 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:02:39 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:02:39 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:02:39 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:02:39 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:02:39 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:02:39 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:02:39 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:02:39 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:02:39 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:02:39 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:02:39 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=462 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:02:39 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=462 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:02:39 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=462 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:02:39 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=462 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:02:39 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=462 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:02:39 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=462 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:02:39 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=462 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:02:39 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=462 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:02:44 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:02:44 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:02:44 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:02:44 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:02:44 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:02:44 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:02:45 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:02:45 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:02:45 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:02:45 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:02:45 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:02:45 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:02:45 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:02:45 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:02:45 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:02:45 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:02:45 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:02:45 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:02:45 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:02:45 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:02:45 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:02:45 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:02:45 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:02:45 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:02:45 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:02:45 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:02:45 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:02:45 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:02:45 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:02:45 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:02:45 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:02:45 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:02:45 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:02:45 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:02:45 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:02:45 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:02:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:02:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:02:45 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:02:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:02:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:02:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:02:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:02:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:02:45 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:02:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:02:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:02:45 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:02:45 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:02:45 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:02:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:02:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:02:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:02:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:02:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:02:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:02:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:02:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:02:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:02:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:02:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:02:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:02:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:02:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:02:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:02:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:02:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:02:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:02:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:02:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:02:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:02:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:02:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:02:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:02:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:02:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:02:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:02:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:02:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:02:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:02:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:02:45 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:02:45 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:02:45 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:02:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:02:45 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:02:45 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:02:45 [DEBUG] fake_trx.py:376 (BTS@172.18.127.20:5700) Recv FAKE_TRXC_DELAY cmd
2025-04-27 04:02:45 [INFO] fake_trx.py:379 (BTS@172.18.127.20:5700) Artificial TRXC delay set to 200
2025-04-27 04:02:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD FAKE_TRXC_DELAY
2025-04-27 04:02:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:02:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:02:46 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:02:46 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:02:46 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:02:46 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:02:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:02:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:02:46 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:02:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:02:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:02:46 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:02:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:02:47 [DEBUG] fake_trx.py:376 (BTS@172.18.127.20:5700) Recv FAKE_TRXC_DELAY cmd
2025-04-27 04:02:47 [INFO] fake_trx.py:379 (BTS@172.18.127.20:5700) Artificial TRXC delay set to 0
2025-04-27 04:02:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD FAKE_TRXC_DELAY
2025-04-27 04:02:47 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:02:47 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:02:47 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:02:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:02:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:02:47 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:02:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:02:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:02:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:02:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:02:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:02:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:02:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:02:47 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:02:47 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:02:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:02:47 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:02:47 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:02:47 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:02:47 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:02:47 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:02:47 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:02:47 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:02:47 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:02:47 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:02:52 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:02:52 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:02:52 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:02:52 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:02:52 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:02:52 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:02:52 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:02:52 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:02:52 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:02:52 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:02:52 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:02:52 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:02:52 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:02:52 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:02:52 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:02:52 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:02:52 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:02:52 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:02:52 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:02:52 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:02:52 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:02:52 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:02:52 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:02:52 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:02:52 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:02:52 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:02:52 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:02:52 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:02:52 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:02:52 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:02:52 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:02:52 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:02:52 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:02:52 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:02:52 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:02:52 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:02:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:02:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:02:52 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:02:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:02:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:02:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:02:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:02:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:02:52 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:02:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:02:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:02:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:02:52 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:02:52 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:02:52 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:02:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:02:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:02:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:02:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:02:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:02:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:02:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:02:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:02:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:02:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:02:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:02:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:02:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:02:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:02:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:02:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:02:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:02:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:02:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:02:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:02:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:02:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:02:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:02:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:02:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:02:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:02:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:02:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:02:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:02:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:02:52 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:02:52 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:02:52 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:02:52 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:02:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:02:52 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:02:52 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:02:52 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:02:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:02:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:02:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:02:52 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:02:52 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:02:52 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:02:52 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:02:52 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:02:52 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:02:52 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:02:52 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:02:52 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:02:52 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:02:52 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:02:57 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:02:57 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:02:57 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:02:57 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:02:57 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:02:57 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:02:57 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:02:57 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:02:57 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:02:57 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:02:57 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:02:57 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:02:57 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:02:57 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:02:57 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:02:57 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:02:57 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:02:57 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:02:57 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:02:57 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:02:57 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:02:57 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:02:57 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:02:57 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:02:57 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:02:57 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:02:57 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:02:57 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:02:57 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:02:57 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:02:57 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:02:57 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:02:57 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:02:57 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:02:57 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:02:57 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:02:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:02:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:02:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:02:57 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:02:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:02:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:02:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:02:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:02:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:02:57 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:02:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:02:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:02:57 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:02:57 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:02:57 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:02:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:02:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:02:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:02:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:02:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:02:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:02:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:02:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:02:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:02:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:02:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:02:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:02:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:02:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:02:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:02:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:02:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:02:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:02:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:02:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:02:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:02:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:02:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:02:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:02:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:02:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:02:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:02:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:02:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:02:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:02:57 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:02:58 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:02:58 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:02:58 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:02:58 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:02:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:02:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:02:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:02:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:02:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:02:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:02:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:02:58 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:02:58 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:02:58 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:02:58 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:02:58 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:02:58 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:02:58 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:02:58 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:02:58 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:02:58 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:03:03 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:03:03 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:03:03 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:03:03 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:03:03 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:03:03 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:03:03 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:03:03 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:03:03 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:03:03 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:03:03 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:03:03 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:03:03 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:03:03 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:03:03 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:03:03 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:03:03 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:03:03 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:03:03 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:03:03 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:03:03 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:03:03 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:03:03 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:03:03 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:03:03 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:03:03 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:03:03 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:03:03 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:03:03 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:03:03 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:03:03 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:03:03 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:03:03 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:03:03 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:03:03 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:03:03 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:03:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:03:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:03:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:03:03 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:03:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:03:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:03:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:03:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:03:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:03:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:03:03 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:03:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:03:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:03:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:03:03 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:03:03 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:03:03 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:03:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:03:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:03:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:03:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:03:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:03:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:03:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:03:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:03:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:03:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:03:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:03:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:03:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:03:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:03:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:03:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:03:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:03:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:03:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:03:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:03:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:03:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:03:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:03:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:03:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:03:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:03:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:03:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:03:03 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:03:03 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:03:04 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:03:04 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:03:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:03:04 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:03:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:03:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:03:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:03:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:03:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:03:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:03:04 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:03:04 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:03:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:03:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:03:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:03:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:03:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:03:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:03:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:03:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:03:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:03:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:03:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:03:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:03:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:03:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:03:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:03:04 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:03:04 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:03:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:03:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:03:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:03:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:03:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:03:04 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:03:04 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:03:04 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:03:04 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:03:04 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:03:04 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:03:05 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:03:05 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:03:05 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:03:05 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:03:05 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:03:05 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 04:03:06 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 04:03:06 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:03:06 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:03:06 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:03:06 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:03:06 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 04:03:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:03:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:03:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:03:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:03:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:03:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:03:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:03:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:03:07 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:03:07 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:03:07 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:03:07 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:03:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:03:07 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:03:07 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:03:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:03:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:03:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:03:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:03:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:03:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:03:07 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 04:03:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:03:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:03:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:03:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:03:07 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:03:07 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:03:07 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:03:07 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:03:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:03:07 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:03:07 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:03:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:03:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:03:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:03:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:03:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:03:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:03:07 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 04:03:08 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 04:03:08 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:03:08 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:03:08 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:03:08 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:03:08 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 04:03:09 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 04:03:09 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 04:03:10 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 04:03:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:03:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:03:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:03:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:03:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:03:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:03:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:03:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:03:10 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:03:10 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:03:10 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:03:10 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:03:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:03:10 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:03:10 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:03:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:03:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:03:10 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 04:03:11 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 04:03:11 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 04:03:12 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 04:03:12 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 04:03:13 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 04:03:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:03:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:03:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:03:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:03:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:03:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:03:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:03:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:03:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:03:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:03:13 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:03:13 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:03:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:03:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:03:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:03:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:03:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:03:13 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 04:03:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:03:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:03:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:03:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:03:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:03:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:03:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:03:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:03:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:03:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:03:13 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:03:13 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:03:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:03:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:03:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:03:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:03:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:03:13 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 04:03:14 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-27 04:03:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:03:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:03:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:03:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:03:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:03:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:03:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:03:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:03:14 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:03:14 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:03:14 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:03:14 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:03:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:03:14 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:03:14 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:03:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:03:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:03:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:03:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:03:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:03:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:03:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:03:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:03:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:03:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:03:14 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:03:14 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:03:14 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:03:14 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:03:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:03:14 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:03:14 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:03:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:03:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:03:14 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-27 04:03:15 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-27 04:03:15 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-27 04:03:16 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-27 04:03:16 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-27 04:03:17 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-27 04:03:17 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-27 04:03:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:03:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:03:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:03:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:03:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:03:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:03:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:03:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:03:17 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:03:17 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:03:17 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:03:17 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:03:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:03:17 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:03:17 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:03:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:03:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:03:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:03:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:03:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:03:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:03:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:03:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:03:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:03:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:03:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:03:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:03:18 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:03:18 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:03:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:03:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:03:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:03:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:03:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:03:18 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-27 04:03:18 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-27 04:03:19 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-27 04:03:19 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-27 04:03:20 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-27 04:03:20 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-27 04:03:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:03:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:03:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:03:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:03:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:03:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:03:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:03:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:03:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:03:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:03:21 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:03:21 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:03:21 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-27 04:03:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:03:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:03:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:03:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:03:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:03:21 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-27 04:03:22 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2025-04-27 04:03:22 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2025-04-27 04:03:23 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2025-04-27 04:03:23 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2025-04-27 04:03:23 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2025-04-27 04:03:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:03:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:03:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:03:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:03:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:03:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:03:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:03:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:03:24 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:03:24 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:03:24 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:03:24 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:03:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:03:24 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:03:24 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:03:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:03:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:03:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:03:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:03:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:03:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:03:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:03:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:03:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:03:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:03:24 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:03:24 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:03:24 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:03:24 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:03:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:03:24 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:03:24 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:03:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:03:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:03:24 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2025-04-27 04:03:24 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2025-04-27 04:03:25 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2025-04-27 04:03:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:03:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:03:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:03:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:03:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:03:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:03:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:03:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:03:25 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:03:25 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:03:25 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:03:25 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:03:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:03:25 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:03:25 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:03:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:03:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:03:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:03:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:03:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:03:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:03:25 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2025-04-27 04:03:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:03:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:03:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:03:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:03:25 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:03:25 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:03:25 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:03:25 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:03:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:03:25 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:03:25 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:03:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:03:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:03:26 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2025-04-27 04:03:26 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2025-04-27 04:03:27 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2025-04-27 04:03:27 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2025-04-27 04:03:28 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2025-04-27 04:03:28 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2025-04-27 04:03:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:03:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:03:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:03:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:03:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:03:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:03:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:03:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:03:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:03:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:03:28 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:03:28 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:03:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:03:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:03:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:03:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:03:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:03:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:03:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:03:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:03:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:03:29 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2025-04-27 04:03:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:03:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:03:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:03:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:03:29 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:03:29 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:03:29 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:03:29 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:03:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:03:29 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:03:29 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:03:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:03:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:03:29 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2025-04-27 04:03:30 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2025-04-27 04:03:30 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2025-04-27 04:03:31 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2025-04-27 04:03:31 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2025-04-27 04:03:32 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2025-04-27 04:03:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:03:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:03:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:03:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:03:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:03:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:03:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:03:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:03:32 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:03:32 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:03:32 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:03:32 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:03:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:03:32 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:03:32 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:03:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:03:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:03:32 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2025-04-27 04:03:33 [DEBUG] clck_gen.py:102 IND CLOCK 6324
2025-04-27 04:03:33 [DEBUG] clck_gen.py:102 IND CLOCK 6426
2025-04-27 04:03:33 [DEBUG] clck_gen.py:102 IND CLOCK 6528
2025-04-27 04:03:34 [DEBUG] clck_gen.py:102 IND CLOCK 6630
2025-04-27 04:03:34 [DEBUG] clck_gen.py:102 IND CLOCK 6732
2025-04-27 04:03:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:03:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:03:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:03:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:03:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:03:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:03:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:03:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:03:35 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:03:35 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:03:35 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:03:35 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:03:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:03:35 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:03:35 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:03:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:03:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:03:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:03:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:03:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:03:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:03:35 [DEBUG] clck_gen.py:102 IND CLOCK 6834
2025-04-27 04:03:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:03:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:03:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:03:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:03:35 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:03:35 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:03:35 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:03:35 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:03:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:03:35 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:03:35 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:03:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:03:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:03:35 [DEBUG] clck_gen.py:102 IND CLOCK 6936
2025-04-27 04:03:36 [DEBUG] clck_gen.py:102 IND CLOCK 7038
2025-04-27 04:03:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:03:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:03:36 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:03:36 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:03:36 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:03:36 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:03:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:03:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:03:36 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:03:36 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:03:36 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:03:36 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:03:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:03:36 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:03:36 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:03:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:03:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:03:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:03:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:03:36 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:03:36 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:03:36 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:03:36 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:03:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:03:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:03:36 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:03:36 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:03:36 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:03:36 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:03:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:03:36 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:03:36 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:03:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:03:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:03:36 [DEBUG] clck_gen.py:102 IND CLOCK 7140
2025-04-27 04:03:37 [DEBUG] clck_gen.py:102 IND CLOCK 7242
2025-04-27 04:03:37 [DEBUG] clck_gen.py:102 IND CLOCK 7344
2025-04-27 04:03:38 [DEBUG] clck_gen.py:102 IND CLOCK 7446
2025-04-27 04:03:38 [DEBUG] clck_gen.py:102 IND CLOCK 7548
2025-04-27 04:03:39 [DEBUG] clck_gen.py:102 IND CLOCK 7650
2025-04-27 04:03:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:03:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:03:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:03:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:03:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:03:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:03:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:03:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:03:39 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:03:39 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:03:39 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:03:39 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:03:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:03:39 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:03:39 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:03:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:03:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:03:39 [DEBUG] clck_gen.py:102 IND CLOCK 7752
2025-04-27 04:03:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:03:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:03:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:03:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:03:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:03:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:03:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:03:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:03:39 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:03:39 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:03:39 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:03:39 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:03:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:03:39 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:03:39 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:03:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:03:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:03:40 [DEBUG] clck_gen.py:102 IND CLOCK 7854
2025-04-27 04:03:40 [DEBUG] clck_gen.py:102 IND CLOCK 7956
2025-04-27 04:03:41 [DEBUG] clck_gen.py:102 IND CLOCK 8058
2025-04-27 04:03:41 [DEBUG] clck_gen.py:102 IND CLOCK 8160
2025-04-27 04:03:42 [DEBUG] clck_gen.py:102 IND CLOCK 8262
2025-04-27 04:03:42 [DEBUG] clck_gen.py:102 IND CLOCK 8364
2025-04-27 04:03:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:03:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:03:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:03:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:03:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:03:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:03:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:03:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:03:42 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:03:42 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:03:42 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:03:42 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:03:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:03:42 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:03:42 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:03:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:03:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:03:43 [DEBUG] clck_gen.py:102 IND CLOCK 8466
2025-04-27 04:03:43 [DEBUG] clck_gen.py:102 IND CLOCK 8568
2025-04-27 04:03:44 [DEBUG] clck_gen.py:102 IND CLOCK 8670
2025-04-27 04:03:44 [DEBUG] clck_gen.py:102 IND CLOCK 8772
2025-04-27 04:03:44 [DEBUG] clck_gen.py:102 IND CLOCK 8874
2025-04-27 04:03:45 [DEBUG] clck_gen.py:102 IND CLOCK 8976
2025-04-27 04:03:45 [DEBUG] clck_gen.py:102 IND CLOCK 9078
2025-04-27 04:03:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:03:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:03:45 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:03:45 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:03:45 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:03:45 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:03:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:03:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:03:45 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:03:45 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:03:45 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:03:45 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:03:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:03:46 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:03:46 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:03:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:03:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:03:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:03:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:03:46 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:03:46 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:03:46 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:03:46 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:03:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:03:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:03:46 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:03:46 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:03:46 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:03:46 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:03:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:03:46 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:03:46 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:03:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:03:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:03:46 [DEBUG] clck_gen.py:102 IND CLOCK 9180
2025-04-27 04:03:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:03:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:03:46 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:03:46 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:03:46 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:03:46 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:03:46 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:03:46 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:03:46 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:03:46 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:03:46 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:03:46 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:03:46 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:03:46 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:03:46 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:03:46 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=9284 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:03:46 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=9284 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:03:46 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=9284 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:03:46 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=9284 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:03:46 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=9284 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:03:46 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=9284 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:03:46 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=9285 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:03:46 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=9285 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:03:46 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=9285 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:03:46 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=9285 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:03:46 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=9285 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:03:46 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=9285 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:03:46 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=9285 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:03:46 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=9285 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:03:51 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:03:51 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:03:51 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:03:51 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:03:51 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:03:51 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:03:51 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:03:51 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:03:51 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:03:51 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:03:51 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:03:51 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:03:51 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:03:51 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:03:51 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:03:51 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:03:51 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:03:51 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:03:51 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:03:51 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:03:51 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:03:51 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:03:51 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:03:51 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:03:51 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:03:51 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:03:51 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:03:51 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:03:51 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:03:51 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:03:51 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:03:51 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:03:51 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:03:51 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:03:51 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:03:51 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:03:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:03:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:03:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:03:51 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:03:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:03:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:03:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:03:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:03:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:03:51 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:03:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:03:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:03:51 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:03:51 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:03:51 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:03:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:03:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:03:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:03:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:03:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:03:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:03:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:03:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:03:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:03:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:03:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:03:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:03:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:03:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:03:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:03:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:03:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:03:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:03:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:03:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:03:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:03:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:03:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:03:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:03:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:03:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:03:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:03:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:03:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:03:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:03:51 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:03:52 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:03:52 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:03:52 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:03:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:03:52 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:03:52 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:03:52 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:03:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:03:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:03:52 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:03:52 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:03:52 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:03:52 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:03:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:03:52 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:03:52 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:03:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:03:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:03:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:03:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:03:52 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:03:52 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:03:52 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:03:52 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:03:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:03:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:03:52 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:03:52 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:03:52 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:03:52 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:03:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:03:52 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:03:52 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:03:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:03:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:03:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:03:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:03:52 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:03:52 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:03:52 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:03:52 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:03:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:03:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:03:52 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:03:52 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:03:52 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:03:52 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:03:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:03:52 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:03:52 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:03:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:03:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:03:52 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:03:52 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:03:52 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:03:52 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:03:52 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:03:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:03:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:03:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:03:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:03:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:03:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:03:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:03:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:03:53 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:03:53 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:03:53 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:03:53 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:03:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:03:53 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:03:53 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:03:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:03:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:03:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:03:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:03:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:03:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:03:53 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:03:53 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:03:53 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:03:53 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:03:53 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:03:53 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:03:53 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:03:53 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:03:53 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:03:53 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:03:53 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:03:58 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:03:58 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:03:58 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:03:58 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:03:58 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:03:58 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:03:58 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:03:58 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:03:58 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:03:58 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:03:58 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:03:58 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:03:58 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:03:58 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:03:58 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:03:58 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:03:58 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:03:58 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:03:58 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:03:58 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:03:58 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:03:58 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:03:58 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:03:58 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:03:58 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:03:58 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:03:58 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:03:58 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:03:58 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:03:58 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:03:58 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:03:58 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:03:58 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:03:58 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:03:58 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:03:58 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:03:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:03:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:03:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:03:58 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:03:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:03:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:03:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:03:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:03:58 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:03:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:03:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:03:58 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:03:58 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:03:58 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:03:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:03:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:03:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:03:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:03:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:03:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:03:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:03:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:03:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:03:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:03:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:03:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:03:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:03:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:03:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:03:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:03:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:03:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:03:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:03:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:03:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:03:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:03:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:03:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:03:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:03:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:03:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:03:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:03:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:03:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:03:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:03:58 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:03:58 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:03:58 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:03:58 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:03:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:03:58 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:03:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:03:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:03:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:03:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:03:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:03:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:03:58 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:03:58 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:03:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:03:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:03:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:03:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:03:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:03:59 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:03:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:03:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:03:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:03:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:03:59 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:03:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:03:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:03:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:03:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:03:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:03:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:03:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:03:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:03:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:03:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:03:59 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:03:59 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:03:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:03:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:03:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:03:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:03:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:04:00 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:04:00 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:04:00 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:04:00 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:04:00 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:04:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:04:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:04:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:04:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:04:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:04:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:04:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:04:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:04:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:04:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:04:00 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:04:00 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:04:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:04:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:04:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:04:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:04:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:04:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:04:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:04:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:04:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:04:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:04:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:04:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:04:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:04:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:04:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:04:00 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:04:00 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:04:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:04:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:04:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:04:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:04:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:04:00 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 04:04:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:04:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:04:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:04:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:04:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:04:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:04:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:04:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:04:01 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:04:01 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:04:01 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:04:01 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:04:01 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:04:01 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=600 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:04:01 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:04:01 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:04:01 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=600 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:04:01 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=600 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:04:01 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=600 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:04:01 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=600 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:04:01 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=600 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:04:01 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=600 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:04:01 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=600 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:04:06 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:04:06 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:04:06 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:04:06 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:04:06 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:04:06 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:04:06 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:04:06 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:04:06 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:04:06 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:04:06 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:04:06 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:04:06 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:04:06 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:04:06 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:04:06 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:04:06 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:04:06 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:04:06 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:04:06 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:04:06 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:04:06 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:04:06 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:04:06 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:04:06 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:04:06 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:04:06 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:04:06 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:04:06 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:04:06 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:04:06 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:04:06 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:04:06 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:04:06 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:04:06 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:04:06 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:04:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:04:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:04:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:04:06 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:04:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:04:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:04:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:04:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:04:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:04:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:04:06 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:04:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:04:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:04:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:04:06 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:04:06 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:04:06 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:04:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:04:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:04:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:04:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:04:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:04:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:04:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:04:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:04:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:04:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:04:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:04:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:04:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:04:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:04:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:04:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:04:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:04:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:04:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:04:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:04:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:04:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:04:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:04:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:04:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:04:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:04:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:04:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:04:06 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:04:06 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:04:06 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:04:06 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:04:06 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:04:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:04:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:04:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:04:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:04:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:04:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:04:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:04:06 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:04:06 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:04:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:04:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:04:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:04:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:04:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:04:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:04:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:04:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:04:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:04:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:04:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:04:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:04:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:04:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:04:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:04:06 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:04:06 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:04:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:04:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:04:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:04:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:04:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:04:07 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:04:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:04:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:04:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:04:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:04:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:04:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:04:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:04:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:04:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:04:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:04:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:04:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:04:07 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:04:07 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:04:07 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:04:07 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:04:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:04:07 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:04:07 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:04:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:04:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:04:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:04:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:04:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:04:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:04:07 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:04:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:04:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:04:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:04:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:04:07 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:04:07 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:04:07 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:04:07 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:04:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:04:07 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:04:07 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:04:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:04:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:04:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:04:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:04:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:04:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:04:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:04:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:04:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:04:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:04:07 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:04:07 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:04:07 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:04:07 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:04:07 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:04:07 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=396 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:04:07 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:04:07 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:04:07 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=396 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:04:07 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=396 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:04:07 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=396 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:04:07 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=396 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:04:07 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=396 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:04:12 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:04:12 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:04:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:04:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:04:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:04:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:04:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:04:12 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:04:12 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:04:12 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:04:12 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:04:12 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:04:12 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:04:12 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:04:12 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:04:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:04:12 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:04:12 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:04:12 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:04:12 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:04:12 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:04:12 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:04:12 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:04:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:04:12 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:04:12 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:04:12 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:04:12 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:04:12 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:04:12 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:04:12 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:04:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:04:12 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:04:12 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:04:12 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:04:12 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:04:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:04:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:04:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:04:12 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:04:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:04:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:04:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:04:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:04:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:04:12 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:04:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:04:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:04:12 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:04:12 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:04:12 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:04:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:04:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:04:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:04:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:04:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:04:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:04:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:04:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:04:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:04:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:04:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:04:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:04:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:04:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:04:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:04:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:04:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:04:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:04:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:04:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:04:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:04:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:04:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:04:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:04:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:04:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:04:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:04:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:04:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:04:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:04:12 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:04:13 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:04:13 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:04:13 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:04:13 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:04:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:04:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:04:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:04:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:04:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:04:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:04:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:04:13 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:04:13 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:04:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:04:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:04:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:04:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:04:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:04:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:04:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:04:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:04:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:04:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:04:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:04:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:04:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:04:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:04:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:04:13 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:04:13 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:04:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:04:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:04:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:04:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:04:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:04:13 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:04:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:04:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:04:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:04:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:04:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:04:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:04:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:04:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:04:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:04:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:04:13 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:04:13 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:04:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:04:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:04:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:04:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:04:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:04:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:04:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:04:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:04:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:04:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:04:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:04:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:04:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:04:14 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:04:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:04:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:04:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:04:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:04:14 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:04:14 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:04:14 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:04:14 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:04:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:04:14 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:04:14 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:04:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:04:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:04:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:04:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:04:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:04:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:04:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:04:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:04:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:04:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:04:14 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:04:14 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:04:14 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:04:14 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:04:14 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:04:14 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:04:14 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:04:14 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=394 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:04:14 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=394 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:04:14 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=394 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:04:14 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=394 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:04:14 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=394 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:04:14 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=394 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:04:14 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=395 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:04:14 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=395 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:04:14 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=395 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:04:14 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=395 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:04:14 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=395 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:04:14 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=395 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:04:14 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=395 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:04:14 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=395 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:04:19 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:04:19 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:04:19 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:04:19 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:04:19 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:04:19 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:04:19 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:04:19 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:04:19 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:04:19 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:04:19 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:04:19 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:04:19 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:04:19 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:04:19 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:04:19 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:04:19 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:04:19 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:04:19 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:04:19 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:04:19 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:04:19 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:04:19 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:04:19 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:04:19 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:04:19 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:04:19 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:04:19 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:04:19 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:04:19 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:04:19 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:04:19 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:04:19 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:04:19 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:04:19 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:04:19 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:04:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:04:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:04:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:04:19 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:04:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:04:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:04:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:04:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:04:19 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:04:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:04:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:04:19 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:04:19 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:04:19 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:04:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:04:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:04:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:04:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:04:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:04:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:04:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:04:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:04:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:04:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:04:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:04:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:04:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:04:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:04:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:04:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:04:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:04:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:04:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:04:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:04:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:04:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:04:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:04:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:04:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:04:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:04:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:04:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:04:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:04:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:04:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:04:19 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:04:20 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:04:20 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:04:20 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:04:20 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:04:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:04:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:04:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:04:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:04:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:04:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:04:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:04:20 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:04:20 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:04:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:04:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:04:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:04:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:04:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:04:20 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:04:20 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:04:20 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:04:20 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:04:20 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:04:21 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:04:21 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:04:21 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:04:21 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:04:21 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:04:21 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:04:22 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 04:04:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:04:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:04:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:04:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:04:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:04:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:04:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:04:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:04:22 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:04:22 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:04:22 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:04:22 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:04:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:04:22 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:04:22 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:04:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:04:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:04:22 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 04:04:22 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:04:22 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:04:22 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:04:22 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:04:23 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 04:04:23 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 04:04:23 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:04:23 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:04:23 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:04:23 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:04:24 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 04:04:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:04:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:04:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:04:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:04:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:04:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:04:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:04:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:04:24 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:04:24 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:04:24 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:04:24 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:04:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:04:24 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:04:24 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:04:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:04:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:04:24 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 04:04:24 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:04:24 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:04:24 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:04:24 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:04:25 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 04:04:25 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 04:04:26 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 04:04:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:04:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:04:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:04:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:04:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:04:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:04:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:04:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:04:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:04:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:04:26 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:04:26 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:04:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:04:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:04:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:04:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:04:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:04:26 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 04:04:26 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 04:04:27 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 04:04:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:04:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:04:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:04:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:04:27 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 04:04:27 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:04:27 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:04:27 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:04:27 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:04:27 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:04:27 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:04:27 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:04:27 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:04:27 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:04:27 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:04:27 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:04:27 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1738 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:04:27 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1738 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:04:27 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1738 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:04:27 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1738 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:04:27 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1738 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:04:27 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1738 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:04:32 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:04:32 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:04:32 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:04:32 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:04:32 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:04:32 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:04:32 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:04:32 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:04:32 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:04:32 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:04:32 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:04:32 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:04:32 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:04:32 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:04:32 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:04:32 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:04:32 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:04:32 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:04:32 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:04:32 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:04:32 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:04:32 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:04:32 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:04:32 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:04:32 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:04:32 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:04:32 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:04:32 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:04:32 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:04:32 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:04:32 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:04:32 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:04:32 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:04:32 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:04:32 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:04:32 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:04:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:04:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:04:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:04:32 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:04:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:04:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:04:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:04:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:04:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:04:32 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:04:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:04:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:04:32 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:04:32 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:04:32 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:04:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:04:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:04:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:04:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:04:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:04:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:04:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:04:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:04:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:04:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:04:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:04:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:04:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:04:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:04:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:04:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:04:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:04:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:04:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:04:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:04:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:04:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:04:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:04:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:04:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:04:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:04:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:04:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:04:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:04:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:04:32 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:04:33 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:04:33 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:04:33 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:04:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:04:33 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:04:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:04:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:04:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:04:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:04:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:04:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:04:33 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:04:33 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:04:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:04:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:04:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:04:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:04:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:04:33 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:04:33 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:04:33 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:04:33 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:04:33 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:04:34 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:04:34 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:04:34 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:04:34 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:04:34 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:04:34 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:04:35 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 04:04:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:04:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:04:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:04:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:04:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:04:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:04:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:04:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:04:35 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:04:35 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:04:35 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:04:35 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:04:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:04:35 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:04:35 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:04:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:04:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:04:35 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 04:04:35 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:04:35 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:04:35 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:04:35 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:04:36 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 04:04:36 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 04:04:36 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:04:36 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:04:36 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:04:36 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:04:37 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 04:04:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:04:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:04:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:04:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:04:37 [WARNING] transceiver.py:250 (MS@172.18.127.22:6700) RX TRXD message (fn=992 tn=2 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:04:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:04:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:04:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:04:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:04:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:04:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:04:37 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:04:37 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:04:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:04:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:04:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:04:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:04:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:04:37 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 04:04:37 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:04:37 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:04:37 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:04:37 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:04:38 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 04:04:38 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 04:04:39 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 04:04:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:04:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:04:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:04:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:04:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:04:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:04:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:04:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:04:39 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:04:39 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:04:39 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:04:39 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:04:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:04:39 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:04:39 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:04:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:04:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:04:39 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 04:04:40 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 04:04:40 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 04:04:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:04:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:04:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:04:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:04:41 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 04:04:41 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:04:41 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:04:41 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:04:41 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:04:41 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:04:41 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:04:41 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:04:41 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:04:41 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:04:41 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:04:41 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1738 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:04:41 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:04:41 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1738 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:04:41 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1738 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:04:41 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1738 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:04:41 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1738 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:04:41 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1738 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:04:41 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1738 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:04:41 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1738 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:04:46 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:04:46 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:04:46 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:04:46 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:04:46 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:04:46 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:04:46 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:04:46 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:04:46 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:04:46 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:04:46 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:04:46 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:04:46 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:04:46 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:04:46 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:04:46 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:04:46 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:04:46 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:04:46 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:04:46 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:04:46 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:04:46 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:04:46 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:04:46 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:04:46 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:04:46 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:04:46 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:04:46 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:04:46 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:04:46 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:04:46 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:04:46 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:04:46 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:04:46 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:04:46 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:04:46 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:04:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:04:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:04:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:04:46 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:04:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:04:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:04:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:04:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:04:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:04:46 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:04:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:04:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:04:46 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:04:46 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:04:46 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:04:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:04:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:04:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:04:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:04:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:04:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:04:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:04:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:04:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:04:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:04:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:04:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:04:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:04:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:04:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:04:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:04:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:04:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:04:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:04:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:04:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:04:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:04:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:04:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:04:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:04:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:04:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:04:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:04:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:04:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:04:46 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:04:46 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:04:46 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:04:46 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:04:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:04:46 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:04:46 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:04:46 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:04:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:04:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:04:46 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:04:46 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:04:46 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:04:46 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:04:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:04:46 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:04:46 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:04:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:04:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:04:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:04:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:04:46 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:04:46 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:04:46 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:04:46 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:04:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:04:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:04:46 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:04:46 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:04:46 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:04:46 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:04:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:04:46 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:04:46 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:04:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:04:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:04:47 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:04:47 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:04:47 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:04:47 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:04:47 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:04:47 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:04:47 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:04:48 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:04:48 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:04:48 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:04:48 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:04:48 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 04:04:48 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 04:04:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:04:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:04:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:04:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:04:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:04:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:04:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:04:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:04:49 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:04:49 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:04:49 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:04:49 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:04:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:04:49 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:04:49 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:04:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:04:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:04:49 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:04:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:04:49 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:04:49 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:04:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:04:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:04:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:04:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:04:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:04:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:04:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:04:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:04:49 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:04:49 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:04:49 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:04:49 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:04:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:04:49 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:04:49 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:04:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:04:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:04:49 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 04:04:49 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 04:04:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:04:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:04:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:04:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:04:50 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 04:04:50 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 04:04:51 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:04:51 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:04:51 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:04:51 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:04:51 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 04:04:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:04:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:04:51 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:04:51 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:04:51 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:04:51 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:04:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:04:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:04:51 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:04:51 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:04:51 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:04:51 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:04:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:04:51 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:04:51 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:04:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:04:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:04:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:04:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:04:51 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:04:51 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:04:51 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:04:51 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:04:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:04:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:04:51 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:04:51 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:04:51 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:04:51 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:04:51 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 04:04:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:04:51 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:04:51 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:04:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:04:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:04:52 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 04:04:52 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 04:04:53 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 04:04:53 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 04:04:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:04:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:04:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:04:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:04:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:04:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:04:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:04:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:04:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:04:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:04:54 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:04:54 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:04:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:04:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:04:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:04:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:04:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:04:54 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 04:04:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:04:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:04:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:04:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:04:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:04:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:04:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:04:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:04:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:04:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:04:54 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:04:54 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:04:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:04:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:04:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:04:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:04:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:04:54 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 04:04:55 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 04:04:55 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 04:04:56 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 04:04:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:04:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:04:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:04:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:04:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:04:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:04:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:04:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:04:56 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:04:56 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:04:56 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:04:56 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:04:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:04:56 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 04:04:56 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:04:56 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:04:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:04:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:04:57 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-27 04:04:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:04:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:04:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:04:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:04:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:04:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:04:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:04:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:04:57 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:04:57 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:04:57 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:04:57 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:04:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:04:57 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:04:57 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:04:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:04:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:04:57 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-27 04:04:57 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-27 04:04:58 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-27 04:04:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:04:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:04:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:04:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:04:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:04:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:04:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:04:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:04:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:04:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:04:58 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:04:58 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:04:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:04:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:04:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:04:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:04:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:04:58 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-27 04:04:59 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-27 04:04:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:04:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:04:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:04:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:04:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:04:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:04:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:04:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:04:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:04:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:04:59 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:04:59 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:04:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:04:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:04:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:04:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:04:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:04:59 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-27 04:05:00 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-27 04:05:00 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-27 04:05:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:05:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:05:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:05:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:05:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:05:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:05:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:05:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:05:01 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:05:01 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:05:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:05:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:05:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:05:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:01 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-27 04:05:01 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-27 04:05:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:05:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:05:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:05:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:05:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:05:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:05:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:05:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:05:01 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:05:01 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:05:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:05:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:05:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:05:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:02 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-27 04:05:02 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-27 04:05:03 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-27 04:05:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:05:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:05:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:05:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:05:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:05:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:05:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:05:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:05:03 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:05:03 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:05:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:05:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:05:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:05:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:03 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-27 04:05:04 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-27 04:05:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:05:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:05:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:05:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:05:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:05:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:05:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:05:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:05:04 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:05:04 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:05:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:05:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:05:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:05:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:04 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2025-04-27 04:05:05 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2025-04-27 04:05:05 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2025-04-27 04:05:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:05:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:05:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:05:05 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:05:05 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:05:05 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:05:05 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:05:05 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:05:05 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:05:05 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:05:05 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:05:05 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:05:05 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4271 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:05:05 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:05:05 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:05:05 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4272 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:05:05 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4272 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:05:05 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4272 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:05:05 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4272 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:05:05 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4272 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:05:05 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4272 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:05:05 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4272 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:05:05 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4272 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:05:05 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4273 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:05:05 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4273 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:05:05 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4273 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:05:05 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4273 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:05:05 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4273 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:05:05 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4273 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:05:05 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4273 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:05:05 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4273 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:05:10 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:05:10 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:05:10 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:05:10 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:05:10 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:05:10 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:05:11 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:05:11 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:05:11 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:05:11 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:05:11 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:05:11 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:05:11 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:05:11 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:05:11 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:05:11 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:05:11 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:05:11 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:05:11 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:05:11 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:05:11 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:05:11 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:05:11 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:05:11 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:05:11 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:05:11 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:05:11 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:05:11 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:05:11 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:05:11 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:05:11 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:05:11 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:05:11 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:05:11 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:05:11 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:05:11 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:05:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:05:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:05:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:05:11 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:05:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:05:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:05:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:05:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:05:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:05:11 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:05:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:05:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:05:11 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:05:11 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:05:11 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:05:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:05:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:05:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:05:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:05:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:05:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:05:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:05:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:05:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:05:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:05:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:05:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:05:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:05:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:05:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:05:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:05:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:05:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:05:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:05:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:05:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:05:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:05:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:05:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:05:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:05:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:05:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:05:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:05:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:05:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:05:11 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:05:11 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:05:11 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:05:11 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:05:11 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:05:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:05:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:05:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:05:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:05:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:05:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:05:11 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:05:11 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:05:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:05:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:05:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:05:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:05:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:05:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:05:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:05:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:05:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:05:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:05:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:05:11 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:05:11 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:05:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:05:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:05:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:05:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:05:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:05:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:05:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:05:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:05:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:05:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:05:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:05:11 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:05:11 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:05:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:05:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:05:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:05:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:05:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:05:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:05:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:05:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:05:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:05:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:05:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:05:11 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:05:11 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:05:11 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:05:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:05:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:05:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:05:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:05:12 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:05:12 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:05:12 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:05:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:05:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:05:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:05:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:05:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:05:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:05:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:05:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:05:12 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:05:12 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:05:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:05:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:05:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:05:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:05:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:05:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:05:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:05:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:05:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:05:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:05:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:05:12 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:05:12 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:05:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:05:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:05:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:05:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:12 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:05:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:05:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:05:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:05:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:05:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:05:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:05:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:05:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:05:12 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:05:12 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:05:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:05:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:05:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:05:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:05:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:05:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:05:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:05:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:05:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:05:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:05:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:05:12 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:05:12 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:05:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:05:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:05:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:05:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:12 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:05:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:05:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:05:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:05:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:05:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:05:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:05:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:05:13 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:05:13 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:05:13 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:05:13 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:05:13 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:05:13 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:05:13 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:05:13 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=431 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:05:13 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=431 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:05:13 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=431 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:05:13 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=431 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:05:13 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=431 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:05:13 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=431 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:05:13 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=431 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:05:13 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=432 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:05:13 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=432 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:05:13 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=432 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:05:13 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=432 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:05:13 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=432 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:05:13 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=432 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:05:13 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=432 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:05:13 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=432 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:05:18 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:05:18 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:05:18 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:05:18 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:05:18 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:05:18 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:05:18 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:05:18 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:05:18 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:05:18 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:05:18 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:05:18 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:05:18 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:05:18 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:05:18 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:05:18 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:05:18 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:05:18 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:05:18 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:05:18 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:05:18 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:05:18 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:05:18 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:05:18 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:05:18 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:05:18 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:05:18 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:05:18 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:05:18 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:05:18 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:05:18 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:05:18 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:05:18 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:05:18 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:05:18 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:05:18 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:05:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:05:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:05:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:05:18 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:05:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:05:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:05:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:05:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:05:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:05:18 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:05:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:05:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:05:18 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:05:18 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:05:18 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:05:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:05:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:05:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:05:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:05:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:05:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:05:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:05:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:05:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:05:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:05:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:05:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:05:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:05:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:05:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:05:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:05:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:05:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:05:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:05:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:05:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:05:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:05:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:05:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:05:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:05:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:05:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:05:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:05:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:05:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:05:18 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:05:18 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:05:18 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:05:18 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:05:18 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:05:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:05:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:05:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:05:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:05:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:05:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:05:18 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:05:18 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:05:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:05:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:05:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:05:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:19 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:05:19 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:05:19 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:05:19 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:05:19 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:05:19 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:05:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:05:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:05:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:05:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:05:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:05:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:05:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:19 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:05:19 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:05:19 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:05:19 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:05:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:05:19 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:05:19 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:05:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:19 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:05:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:05:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:05:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:05:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:05:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:05:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:05:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:05:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:05:20 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:05:20 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:05:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:05:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:05:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:05:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:20 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:05:20 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:05:20 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:05:20 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:05:20 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 04:05:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:05:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:05:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:05:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:05:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:05:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:05:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:05:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:05:20 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:05:20 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:05:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:05:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:05:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:05:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:20 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 04:05:21 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:05:21 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:05:21 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:05:21 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:05:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:05:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:05:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:05:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:05:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:05:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:05:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:05:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:05:21 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:05:21 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:05:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:05:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:05:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:05:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:05:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:05:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:05:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:05:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:05:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:05:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:05:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:05:21 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:05:21 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:05:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:05:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:05:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:05:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:21 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 04:05:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:05:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:05:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:05:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:05:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:05:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:05:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:05:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:05:21 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:05:21 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:05:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:05:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:05:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:05:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:21 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 04:05:22 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:05:22 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:05:22 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:05:22 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:05:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:05:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:05:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:05:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:05:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:05:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:05:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:22 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:05:22 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:05:22 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:05:22 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:05:22 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 04:05:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:05:22 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:05:22 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:05:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:05:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:05:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:05:22 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:05:22 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:05:22 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:05:22 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:05:22 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:05:22 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:05:22 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:05:22 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:05:22 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:05:22 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:05:22 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1007 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:05:22 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:05:22 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1007 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:05:22 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1007 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:05:22 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1007 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:05:27 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:05:27 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:05:27 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:05:27 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:05:27 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:05:27 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:05:27 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:05:27 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:05:27 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:05:27 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:05:27 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:05:27 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:05:27 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:05:27 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:05:27 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:05:27 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:05:27 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:05:27 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:05:27 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:05:27 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:05:27 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:05:27 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:05:27 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:05:27 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:05:27 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:05:27 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:05:27 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:05:27 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:05:27 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:05:27 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:05:27 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:05:27 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:05:27 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:05:27 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:05:27 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:05:27 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:05:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:05:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:05:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:05:27 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:05:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:05:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:05:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:05:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:05:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:05:27 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:05:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:05:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:05:27 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:05:27 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:05:27 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:05:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:05:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:05:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:05:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:05:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:05:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:05:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:05:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:05:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:05:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:05:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:05:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:05:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:05:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:05:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:05:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:05:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:05:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:05:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:05:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:05:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:05:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:05:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:05:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:05:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:05:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:05:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:05:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:05:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:05:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:05:27 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:05:28 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:05:28 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:05:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:05:28 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:05:28 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:05:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:05:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:05:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:05:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:05:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:05:28 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:05:28 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:05:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:05:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:05:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:05:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:05:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:05:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:05:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:05:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:05:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:05:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:05:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:05:28 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:05:28 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:05:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:05:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:05:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:05:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:05:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:05:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:05:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:05:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:05:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:05:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:05:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:05:28 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:05:28 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:05:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:05:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:05:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:05:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:05:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:05:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:05:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:05:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:05:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:05:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:05:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:05:28 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:05:28 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:05:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:05:28 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:05:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:05:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:05:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:28 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:05:28 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:05:28 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:05:28 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:05:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:05:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:05:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:05:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:05:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:05:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:05:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:05:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:05:28 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:05:28 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:05:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:05:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:05:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:05:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:05:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:05:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:05:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:05:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:05:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:05:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:05:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:05:28 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:05:28 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:05:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:05:29 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:05:29 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:05:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:05:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:05:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:05:29 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:05:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:05:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:05:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:05:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:29 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:05:29 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:05:29 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:05:29 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:05:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:05:29 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:05:29 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:05:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:05:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:05:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:05:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:05:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:05:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:05:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:29 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:05:29 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:05:29 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:05:29 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:05:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:05:29 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:05:29 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:05:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:05:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:05:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:05:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:05:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:05:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:05:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:05:29 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:05:29 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:05:29 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:05:29 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:05:29 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:05:29 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=395 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:05:29 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:05:29 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:05:29 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=396 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:05:29 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=396 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:05:29 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=396 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:05:29 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=396 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:05:29 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=396 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:05:29 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=396 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:05:29 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=396 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:05:29 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=396 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:05:34 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:05:34 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:05:34 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:05:34 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:05:34 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:05:34 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:05:34 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:05:34 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:05:34 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:05:34 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:05:34 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:05:34 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:05:34 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:05:34 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:05:34 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:05:34 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:05:34 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:05:34 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:05:34 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:05:34 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:05:34 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:05:34 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:05:34 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:05:34 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:05:34 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:05:34 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:05:34 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:05:34 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:05:34 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:05:34 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:05:34 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:05:34 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:05:34 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:05:34 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:05:34 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:05:34 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:05:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:05:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:05:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:05:34 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:05:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:05:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:05:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:05:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:05:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:05:34 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:05:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:05:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:05:34 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:05:34 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:05:34 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:05:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:05:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:05:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:05:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:05:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:05:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:05:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:05:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:05:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:05:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:05:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:05:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:05:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:05:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:05:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:05:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:05:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:05:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:05:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:05:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:05:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:05:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:05:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:05:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:05:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:05:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:05:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:05:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:05:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:05:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:05:34 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:05:35 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:05:35 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:05:35 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:05:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:05:35 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:05:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:05:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:05:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:05:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:35 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:05:35 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:05:35 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:05:35 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:05:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:05:35 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:05:35 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:05:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:35 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:05:35 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:05:35 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:05:35 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:05:35 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:05:36 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:05:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:05:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:36 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:05:36 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:05:36 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:05:36 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:05:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:05:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:36 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:05:36 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:05:36 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:05:36 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:05:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:05:36 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:05:36 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:05:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:36 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:05:36 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:05:36 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:05:36 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:05:36 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:05:37 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 04:05:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:05:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:05:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:05:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:05:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:05:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:05:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:05:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:05:37 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:05:37 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:05:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:05:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:05:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:05:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:37 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 04:05:37 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:05:37 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:05:37 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:05:37 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:05:38 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 04:05:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:05:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:05:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:05:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:05:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:05:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:05:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:38 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:05:38 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:05:38 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:05:38 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:05:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:05:38 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:05:38 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:05:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:38 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 04:05:38 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:05:38 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:05:38 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:05:38 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:05:38 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 04:05:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:05:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:05:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:05:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:05:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:05:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:05:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:39 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:05:39 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:05:39 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:05:39 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:05:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:05:39 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:05:39 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:05:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:39 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 04:05:39 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:05:39 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:05:39 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:05:39 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:05:39 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 04:05:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:05:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:05:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:05:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:05:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:05:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:05:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:39 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:05:39 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:05:39 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:05:39 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:05:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:05:40 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:05:40 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:05:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:40 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 04:05:40 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 04:05:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:05:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:05:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:05:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:05:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:05:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:05:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:40 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:05:40 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:05:40 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:05:40 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:05:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:05:40 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:05:40 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:05:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:41 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 04:05:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:05:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:05:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:05:41 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 04:05:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:05:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:05:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:05:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:05:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:05:41 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:05:41 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:05:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:05:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:05:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:05:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:42 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 04:05:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:05:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:05:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:05:42 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 04:05:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:05:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:05:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:05:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:05:42 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:05:42 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:05:42 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:05:42 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:05:42 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:05:42 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:05:42 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:05:47 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:05:47 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:05:47 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:05:47 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:05:47 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:05:47 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:05:47 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:05:47 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:05:47 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:05:47 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:05:47 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:05:47 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:05:47 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:05:47 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:05:47 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:05:47 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:05:47 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:05:47 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:05:47 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:05:47 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:05:47 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:05:47 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:05:47 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:05:47 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:05:47 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:05:47 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:05:47 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:05:47 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:05:47 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:05:47 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:05:47 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:05:47 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:05:47 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:05:47 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:05:47 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:05:47 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:05:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:05:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:05:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:05:47 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:05:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:05:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:05:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:05:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:05:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:05:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:05:47 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:05:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:05:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:05:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:05:47 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:05:47 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:05:47 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:05:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:05:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:05:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:05:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:05:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:05:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:05:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:05:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:05:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:05:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:05:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:05:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:05:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:05:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:05:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:05:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:05:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:05:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:05:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:05:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:05:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:05:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:05:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:05:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:05:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:05:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:05:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:05:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:05:47 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:05:48 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:05:48 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:05:48 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:05:48 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:05:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:05:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:05:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:05:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:05:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:48 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:05:48 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:05:48 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:05:48 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:05:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:05:48 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:05:48 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:05:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:05:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:05:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:05:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:05:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:05:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:05:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:48 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:05:48 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:05:48 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:05:48 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:05:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:05:48 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:05:48 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:05:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:05:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:05:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:05:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:05:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:05:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:05:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:48 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:05:48 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:05:48 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:05:48 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:05:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:05:48 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:05:48 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:05:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:48 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:05:48 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:05:48 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:05:48 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:05:48 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:05:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:05:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:05:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:05:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:05:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:05:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:05:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:49 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:05:49 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:05:49 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:05:49 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:05:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:05:49 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:05:49 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:05:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:49 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:05:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:05:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:05:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:05:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:05:49 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:05:49 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:05:49 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:05:49 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:05:49 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:05:49 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:05:49 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:05:49 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:05:49 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:05:49 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:05:49 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=344 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:05:49 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=344 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:05:49 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=344 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:05:49 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=344 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:05:49 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=345 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:05:49 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=345 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:05:49 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=345 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:05:49 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=345 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:05:49 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=345 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:05:49 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=345 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:05:49 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=345 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:05:49 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=345 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:05:54 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:05:54 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:05:54 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:05:54 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:05:54 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:05:54 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:05:54 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:05:54 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:05:54 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:05:54 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:05:54 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:05:54 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:05:54 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:05:54 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:05:54 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:05:54 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:05:54 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:05:54 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:05:54 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:05:54 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:05:54 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:05:54 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:05:54 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:05:54 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:05:54 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:05:54 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:05:54 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:05:54 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:05:54 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:05:54 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:05:54 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:05:54 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:05:54 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:05:54 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:05:54 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:05:54 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:05:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:05:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:05:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:05:54 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:05:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:05:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:05:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:05:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:05:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:05:54 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:05:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:05:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:05:54 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:05:54 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:05:54 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:05:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:05:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:05:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:05:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:05:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:05:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:05:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:05:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:05:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:05:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:05:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:05:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:05:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:05:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:05:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:05:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:05:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:05:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:05:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:05:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:05:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:05:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:05:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:05:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:05:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:05:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:05:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:05:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:05:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:05:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:05:54 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:05:54 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:05:54 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:05:54 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:05:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:05:54 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:05:55 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:05:55 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:05:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:05:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:55 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:05:55 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:05:55 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:05:55 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:05:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:05:55 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:05:55 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:05:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:05:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:55 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:05:55 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:05:55 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:05:55 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:05:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:05:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:55 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:05:55 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:05:55 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:05:55 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:05:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:05:55 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:05:55 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:05:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:05:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:55 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:05:55 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:05:55 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:05:55 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:05:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:05:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:55 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:05:55 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:05:55 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:05:55 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:05:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:05:55 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:05:55 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:05:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:55 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:05:55 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:05:55 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:05:55 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:05:55 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:05:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:05:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:55 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:05:55 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:05:55 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:05:55 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:05:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:05:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:55 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:05:55 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:05:55 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:05:55 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:05:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:05:55 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:05:55 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:05:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:55 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:05:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:05:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:05:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:05:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:05:56 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:05:56 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:05:56 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:05:56 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:05:56 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:05:56 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:05:56 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:05:56 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:05:56 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:05:56 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=343 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:05:56 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:05:56 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:05:56 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=343 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:05:56 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=344 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:05:56 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=344 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:05:56 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=344 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:05:56 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=344 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:05:56 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=344 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:05:56 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=344 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:05:56 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=344 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:05:56 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=344 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:06:01 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:06:01 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:06:01 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:06:01 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:06:01 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:06:01 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:06:01 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:06:01 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:06:01 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:06:01 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:06:01 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:06:01 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:06:01 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:06:01 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:06:01 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:06:01 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:06:01 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:06:01 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:06:01 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:06:01 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:06:01 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:06:01 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:06:01 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:06:01 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:06:01 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:06:01 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:06:01 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:06:01 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:06:01 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:06:01 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:06:01 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:06:01 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:06:01 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:06:01 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:06:01 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:06:01 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:06:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:06:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:06:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:06:01 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:06:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:06:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:06:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:06:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:06:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:06:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:06:01 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:06:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:06:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:06:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:06:01 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:06:01 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:06:01 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:06:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:06:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:06:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:06:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:06:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:06:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:06:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:06:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:06:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:06:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:06:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:06:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:06:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:06:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:06:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:06:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:06:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:06:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:06:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:06:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:06:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:06:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:06:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:06:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:06:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:06:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:06:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:06:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:06:01 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:06:01 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:06:01 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:06:01 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:06:01 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:06:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:06:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:06:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:06:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:06:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:06:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:06:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:06:01 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:06:01 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:06:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:06:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:06:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:06:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:06:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:06:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:06:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:06:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:06:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:06:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:06:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:06:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:06:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:06:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:06:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:06:01 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:06:01 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:06:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:06:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:06:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:06:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:06:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:06:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:06:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:06:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:06:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:06:02 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:06:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:06:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:06:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:06:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:06:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:06:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:06:02 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:06:02 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:06:02 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:06:02 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:06:02 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:06:02 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:06:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:06:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:06:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:06:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:06:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:06:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:06:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:06:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:06:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:06:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:06:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:06:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:06:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:06:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:06:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:06:02 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:06:02 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:06:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:06:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:06:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:06:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:06:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:06:02 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:06:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:06:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:06:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:06:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:06:02 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:06:02 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:06:02 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:06:02 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:06:02 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:06:02 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:06:02 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:06:02 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:06:02 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:06:02 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:06:02 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:06:02 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=343 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:06:02 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=343 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:06:02 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=343 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:06:02 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=343 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:06:02 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=343 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:06:02 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=343 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:06:07 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:06:07 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:06:07 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:06:07 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:06:07 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:06:07 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:06:07 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:06:07 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:06:07 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:06:07 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:06:07 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:06:07 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:06:07 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:06:07 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:06:07 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:06:07 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:06:07 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:06:07 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:06:07 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:06:07 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:06:07 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:06:07 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:06:07 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:06:07 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:06:07 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:06:07 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:06:07 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:06:07 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:06:07 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:06:07 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:06:07 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:06:07 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:06:07 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:06:07 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:06:07 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:06:07 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:06:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:06:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:06:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:06:07 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:06:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:06:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:06:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:06:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:06:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:06:07 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:06:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:06:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:06:07 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:06:07 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:06:07 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:06:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:06:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:06:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:06:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:06:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:06:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:06:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:06:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:06:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:06:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:06:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:06:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:06:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:06:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:06:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:06:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:06:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:06:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:06:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:06:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:06:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:06:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:06:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:06:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:06:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:06:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:06:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:06:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:06:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:06:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:06:07 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:06:08 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:06:08 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:06:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:06:08 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:06:08 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:06:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:06:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:06:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:06:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:06:08 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:06:08 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:06:08 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:06:08 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:06:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:06:08 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:06:08 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:06:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:06:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:06:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:06:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:06:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:06:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:06:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:06:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:06:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:06:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:06:08 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:06:08 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:06:08 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:06:08 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:06:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:06:08 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:06:08 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:06:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:06:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:06:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:06:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:06:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:06:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:06:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:06:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:06:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:06:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:06:08 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:06:08 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:06:08 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:06:08 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:06:08 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:06:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:06:08 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:06:08 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:06:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:06:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:06:08 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:06:08 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:06:08 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:06:08 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:06:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:06:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:06:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:06:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:06:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:06:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:06:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:06:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:06:08 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:06:08 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:06:08 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:06:08 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:06:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:06:08 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:06:08 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:06:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:06:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:06:09 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:06:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:06:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:06:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:06:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:06:09 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:06:09 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:06:09 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:06:09 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:06:09 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:06:09 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:06:09 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:06:09 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:06:09 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:06:09 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:06:09 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:06:09 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=344 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:06:09 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=344 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:06:09 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=344 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:06:09 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=344 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:06:09 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=344 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:06:09 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=344 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:06:14 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:06:14 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:06:14 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:06:14 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:06:14 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:06:14 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:06:14 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:06:14 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:06:14 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:06:14 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:06:14 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:06:14 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:06:14 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:06:14 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:06:14 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:06:14 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:06:14 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:06:14 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:06:14 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:06:14 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:06:14 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:06:14 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:06:14 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:06:14 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:06:14 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:06:14 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:06:14 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:06:14 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:06:14 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:06:14 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:06:14 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:06:14 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:06:14 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:06:14 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:06:14 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:06:14 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:06:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:06:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:06:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:06:14 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:06:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:06:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:06:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:06:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:06:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:06:14 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:06:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:06:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:06:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:06:14 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:06:14 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:06:14 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:06:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:06:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:06:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:06:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:06:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:06:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:06:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:06:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:06:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:06:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:06:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:06:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:06:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:06:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:06:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:06:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:06:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:06:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:06:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:06:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:06:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:06:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:06:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:06:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:06:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:06:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:06:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:06:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:06:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:06:14 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:06:14 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:06:14 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:06:14 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:06:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:06:14 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:06:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:06:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:06:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:06:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:06:14 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:06:14 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:06:14 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:06:14 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:06:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:06:14 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:06:14 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:06:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:06:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:06:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:06:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:06:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:06:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:06:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:06:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:06:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:06:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:06:15 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:06:15 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:06:15 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:06:15 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:06:15 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:06:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:06:15 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:06:15 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:06:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:06:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:06:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:06:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:06:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:06:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:06:15 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:06:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:06:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:06:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:06:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:06:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:06:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:06:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:06:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:06:15 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:06:15 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:06:15 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:06:15 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:06:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:06:15 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:06:15 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:06:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:06:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:06:16 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:06:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:06:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:06:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:06:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:06:16 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 04:06:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:06:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:06:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:06:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:06:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:06:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:06:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:06:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:06:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:06:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:06:16 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:06:16 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:06:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:06:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:06:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:06:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:06:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:06:17 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 04:06:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:06:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:06:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:06:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:06:17 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 04:06:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:06:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:06:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:06:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:06:18 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:06:18 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:06:18 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:06:18 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:06:18 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:06:18 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:06:18 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:06:18 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:06:18 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:06:18 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:06:18 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:06:18 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=787 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:06:18 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=787 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:06:18 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=787 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:06:18 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=787 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:06:18 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=787 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:06:18 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=787 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:06:18 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=788 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:06:18 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=788 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:06:18 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=788 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:06:18 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=788 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:06:18 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=788 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:06:18 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=788 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:06:18 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=788 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:06:18 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=788 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:06:23 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:06:23 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:06:23 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:06:23 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:06:23 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:06:23 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:06:23 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:06:23 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:06:23 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:06:23 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:06:23 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:06:23 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:06:23 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:06:23 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:06:23 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:06:23 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:06:23 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:06:23 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:06:23 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:06:23 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:06:23 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:06:23 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:06:23 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:06:23 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:06:23 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:06:23 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:06:23 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:06:23 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:06:23 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:06:23 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:06:23 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:06:23 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:06:23 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:06:23 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:06:23 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:06:23 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:06:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:06:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:06:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:06:23 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:06:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:06:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:06:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:06:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:06:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:06:23 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:06:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:06:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:06:23 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:06:23 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:06:23 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:06:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:06:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:06:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:06:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:06:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:06:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:06:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:06:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:06:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:06:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:06:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:06:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:06:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:06:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:06:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:06:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:06:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:06:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:06:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:06:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:06:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:06:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:06:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:06:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:06:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:06:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:06:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:06:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:06:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:06:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:06:23 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:06:23 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:06:23 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:06:23 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:06:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:06:23 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:06:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:06:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:06:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:06:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:06:23 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:06:23 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:06:23 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:06:23 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:06:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:06:23 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:06:23 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:06:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:06:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:06:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:06:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:06:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:06:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:06:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:06:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:06:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:06:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:06:23 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:06:23 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:06:23 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:06:23 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:06:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:06:24 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:06:24 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:06:24 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:06:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:06:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:06:24 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:06:24 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:06:24 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:06:24 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:06:24 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:06:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:06:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:06:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:06:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:06:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:06:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:06:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:06:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:06:24 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:06:24 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:06:24 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:06:24 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:06:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:06:24 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:06:24 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:06:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:06:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:06:24 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:06:25 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:06:25 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:06:25 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:06:25 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:06:25 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 04:06:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:06:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:06:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:06:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:06:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:06:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:06:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:06:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:06:25 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:06:25 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:06:25 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:06:25 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:06:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:06:25 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:06:25 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:06:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:06:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:06:25 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 04:06:26 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:06:26 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:06:26 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:06:26 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:06:26 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 04:06:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:06:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:06:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:06:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:06:26 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:06:26 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:06:26 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:06:26 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:06:26 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:06:26 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:06:26 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:06:26 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:06:26 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:06:26 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:06:26 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:06:26 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=788 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:06:26 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=788 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:06:26 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=788 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:06:26 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=788 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:06:26 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=788 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:06:26 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=788 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:06:26 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=788 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:06:26 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=789 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:06:26 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=789 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:06:26 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=789 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:06:26 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=789 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:06:26 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=789 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:06:26 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=789 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:06:26 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=789 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:06:26 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=789 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:06:31 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:06:31 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:06:31 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:06:31 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:06:31 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:06:31 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:06:31 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:06:31 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:06:31 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:06:31 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:06:31 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:06:31 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:06:31 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:06:31 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:06:31 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:06:31 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:06:31 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:06:31 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:06:31 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:06:31 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:06:31 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:06:31 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:06:31 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:06:31 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:06:31 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:06:31 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:06:31 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:06:31 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:06:31 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:06:31 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:06:31 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:06:31 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:06:31 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:06:31 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:06:31 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:06:31 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:06:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:06:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:06:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:06:31 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:06:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:06:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:06:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:06:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:06:31 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:06:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:06:31 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:06:31 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:06:31 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:06:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:06:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:06:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:06:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:06:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:06:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:06:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:06:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:06:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:06:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:06:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:06:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:06:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:06:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:06:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:06:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:06:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:06:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:06:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:06:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:06:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:06:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:06:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:06:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:06:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:06:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:06:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:06:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:06:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:06:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:06:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:06:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:06:31 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:06:32 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:06:32 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:06:32 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:06:32 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:06:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:06:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:06:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:06:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:06:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:06:32 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:06:32 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:06:32 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:06:32 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:06:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:06:32 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:06:32 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:06:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:06:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:06:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:06:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:06:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:06:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:06:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:06:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:06:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:06:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:06:32 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:06:32 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:06:32 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:06:32 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:06:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:06:32 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:06:32 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:06:32 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:06:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:06:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:06:32 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:06:32 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:06:32 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:06:32 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:06:33 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:06:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:06:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:06:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:06:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:06:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:06:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:06:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:06:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:06:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:06:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:06:33 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:06:33 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:06:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:06:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:06:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:06:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:06:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:06:33 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:06:33 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:06:33 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:06:33 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:06:33 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:06:34 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 04:06:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:06:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:06:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:06:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:06:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:06:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:06:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:06:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:06:34 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:06:34 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:06:34 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:06:34 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:06:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:06:34 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:06:34 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:06:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:06:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:06:34 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 04:06:34 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:06:34 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:06:34 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:06:34 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:06:35 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 04:06:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:06:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:06:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:06:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:06:35 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:06:35 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:06:35 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:06:35 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:06:35 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:06:35 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:06:35 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:06:35 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:06:35 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:06:35 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:06:35 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:06:35 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=787 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:06:35 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=787 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:06:35 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=787 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:06:35 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=787 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:06:35 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=787 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:06:35 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=787 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:06:35 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=787 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:06:40 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:06:40 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:06:40 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:06:40 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:06:40 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:06:40 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:06:40 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:06:40 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:06:40 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:06:40 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:06:40 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:06:40 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:06:40 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:06:40 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:06:40 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:06:40 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:06:40 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:06:40 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:06:40 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:06:40 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:06:40 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:06:40 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:06:40 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:06:40 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:06:40 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:06:40 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:06:40 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:06:40 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:06:40 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:06:40 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:06:40 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:06:40 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:06:40 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:06:40 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:06:40 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:06:40 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:06:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:06:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:06:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:06:40 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:06:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:06:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:06:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:06:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:06:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:06:40 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:06:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:06:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:06:40 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:06:40 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:06:40 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:06:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:06:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:06:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:06:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:06:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:06:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:06:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:06:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:06:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:06:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:06:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:06:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:06:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:06:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:06:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:06:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:06:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:06:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:06:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:06:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:06:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:06:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:06:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:06:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:06:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:06:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:06:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:06:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:06:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:06:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:06:40 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:06:40 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:06:40 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:06:40 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:06:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:06:40 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:06:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:06:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:06:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:06:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:06:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:06:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:06:41 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:06:41 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:06:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:06:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:06:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:06:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:06:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:06:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:06:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:06:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:06:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:06:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:06:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:06:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:06:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:06:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:06:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:06:41 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:06:41 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:06:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:06:41 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:06:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:06:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:06:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:06:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:06:41 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:06:41 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:06:41 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:06:41 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:06:41 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:06:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:06:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:06:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:06:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:06:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:06:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:06:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:06:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:06:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:06:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:06:41 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:06:41 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:06:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:06:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:06:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:06:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:06:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:06:42 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:06:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:06:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:06:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:06:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:06:42 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 04:06:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:06:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:06:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:06:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:06:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:06:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:06:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:06:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:06:43 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:06:43 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:06:43 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:06:43 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:06:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:06:43 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:06:43 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:06:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:06:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:06:43 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 04:06:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:06:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:06:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:06:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:06:43 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 04:06:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:06:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:06:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:06:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:06:44 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:06:44 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:06:44 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:06:44 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:06:44 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:06:44 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:06:44 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:06:44 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:06:44 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:06:44 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:06:44 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=787 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:06:44 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:06:44 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=787 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:06:44 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=787 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:06:44 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=787 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:06:44 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=787 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:06:44 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=787 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:06:44 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=788 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:06:44 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=788 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:06:44 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=788 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:06:44 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=788 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:06:44 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=788 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:06:44 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=788 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:06:44 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=788 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:06:44 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=788 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:06:49 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:06:49 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:06:49 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:06:49 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:06:49 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:06:49 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:06:49 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:06:49 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:06:49 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:06:49 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:06:49 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:06:49 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:06:49 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:06:49 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:06:49 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:06:49 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:06:49 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:06:49 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:06:49 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:06:49 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:06:49 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:06:49 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:06:49 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:06:49 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:06:49 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:06:49 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:06:49 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:06:49 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:06:49 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:06:49 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:06:49 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:06:49 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:06:49 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:06:49 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:06:49 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:06:49 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:06:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:06:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:06:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:06:49 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:06:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:06:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:06:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:06:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:06:49 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:06:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:06:49 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:06:49 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:06:49 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:06:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:06:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:06:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:06:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:06:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:06:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:06:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:06:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:06:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:06:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:06:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:06:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:06:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:06:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:06:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:06:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:06:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:06:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:06:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:06:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:06:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:06:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:06:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:06:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:06:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:06:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:06:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:06:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:06:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:06:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:06:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:06:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:06:49 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:06:49 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:06:49 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:06:49 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:06:49 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:06:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:06:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:06:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:06:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:06:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:06:49 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:06:49 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:06:49 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:06:49 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:06:49 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:06:49 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:06:49 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:06:49 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:06:49 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=122 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:06:49 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:06:49 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:06:49 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=122 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:06:49 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=122 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:06:49 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=122 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:06:49 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=122 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:06:49 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=122 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:06:49 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=123 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:06:49 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=123 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:06:49 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=123 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:06:49 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=123 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:06:49 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=123 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:06:49 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=123 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:06:49 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=123 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:06:49 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=123 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:06:54 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:06:54 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:06:54 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:06:54 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:06:54 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:06:54 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:06:54 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:06:54 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:06:54 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:06:54 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:06:54 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:06:54 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:06:54 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:06:54 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:06:54 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:06:54 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:06:54 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:06:54 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:06:54 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:06:54 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:06:54 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:06:54 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:06:54 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:06:54 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:06:54 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:06:54 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:06:54 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:06:54 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:06:54 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:06:54 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:06:54 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:06:54 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:06:54 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:06:54 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:06:54 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:06:54 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:06:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:06:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:06:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:06:54 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:06:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:06:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:06:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:06:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:06:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:06:54 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:06:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:06:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:06:54 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:06:54 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:06:54 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:06:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:06:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:06:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:06:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:06:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:06:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:06:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:06:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:06:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:06:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:06:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:06:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:06:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:06:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:06:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:06:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:06:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:06:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:06:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:06:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:06:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:06:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:06:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:06:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:06:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:06:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:06:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:06:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:06:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:06:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:06:54 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:06:55 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:06:55 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:06:55 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:06:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:06:55 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:06:55 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:06:55 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:06:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:06:55 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:06:55 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:06:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:06:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:06:55 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:06:55 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:06:55 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:06:55 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:06:55 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:06:55 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:06:55 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:06:55 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:06:55 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:06:55 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:06:55 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:06:55 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=132 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:06:55 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=132 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:06:55 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=132 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:06:55 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=132 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:06:55 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=132 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:06:55 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=132 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:07:00 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:07:00 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:07:00 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:07:00 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:07:00 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:07:00 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:07:00 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:07:00 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:07:00 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:07:00 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:07:00 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:07:00 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:07:00 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:07:00 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:07:00 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:07:00 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:07:00 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:07:00 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:07:00 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:07:00 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:07:00 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:07:00 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:07:00 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:07:00 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:07:00 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:07:00 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:07:00 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:07:00 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:07:00 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:07:00 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:07:00 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:07:00 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:07:00 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:07:00 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:07:00 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:07:00 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:07:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:07:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:07:00 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:07:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:07:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:07:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:07:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:07:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:07:00 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:07:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:07:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:07:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:07:00 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:07:00 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:07:00 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:07:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:07:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:07:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:07:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:07:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:07:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:07:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:07:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:07:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:07:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:07:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:07:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:07:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:07:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:07:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:07:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:07:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:07:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:07:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:07:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:07:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:07:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:07:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:07:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:07:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:07:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:07:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:07:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:07:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:07:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:07:00 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:07:00 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:07:00 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:07:00 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:07:00 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:07:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:07:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:07:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:07:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:07:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:07:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:07:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:07:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:07:01 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:07:01 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:07:01 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:07:01 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:07:01 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:07:01 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:07:01 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:07:01 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=123 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:07:01 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=123 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:07:01 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=123 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:07:01 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=123 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:07:01 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=123 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:07:01 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=123 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:07:01 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=124 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:07:01 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=124 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:07:01 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=124 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:07:01 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=124 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:07:01 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=124 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:07:01 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=124 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:07:01 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=124 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:07:01 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=124 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:07:06 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:07:06 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:07:06 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:07:06 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:07:06 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:07:06 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:07:06 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:07:06 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:07:06 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:07:06 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:07:06 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:07:06 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:07:06 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:07:06 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:07:06 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:07:06 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:07:06 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:07:06 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:07:06 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:07:06 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:07:06 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:07:06 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:07:06 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:07:06 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:07:06 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:07:06 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:07:06 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:07:06 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:07:06 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:07:06 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:07:06 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:07:06 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:07:06 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:07:06 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:07:06 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:07:06 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:07:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:07:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:07:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:07:06 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:07:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:07:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:07:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:07:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:07:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:07:06 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:07:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:07:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:07:06 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:07:06 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:07:06 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:07:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:07:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:07:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:07:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:07:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:07:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:07:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:07:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:07:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:07:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:07:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:07:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:07:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:07:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:07:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:07:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:07:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:07:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:07:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:07:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:07:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:07:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:07:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:07:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:07:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:07:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:07:06 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:07:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:07:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:07:06 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:07:06 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:07:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:07:06 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:07:06 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:07:06 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:07:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:07:11 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:07:11 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:07:11 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:07:11 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:07:11 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:07:11 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:07:11 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:07:11 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:07:11 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:07:11 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:07:11 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:07:11 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:07:11 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:07:11 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:07:11 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:07:11 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:07:11 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:07:11 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:07:11 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:07:11 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:07:11 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:07:11 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:07:11 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:07:11 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:07:11 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:07:11 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:07:11 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:07:11 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:07:11 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:07:11 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:07:11 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:07:11 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:07:11 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:07:11 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:07:11 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:07:11 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:07:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:07:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:07:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:07:11 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:07:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:07:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:07:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:07:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:07:11 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:07:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:07:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:07:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:07:11 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:07:11 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:07:11 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:07:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:07:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:07:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:07:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:07:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:07:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:07:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:07:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:07:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:07:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:07:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:07:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:07:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:07:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:07:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:07:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:07:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:07:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:07:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:07:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:07:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:07:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:07:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:07:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:07:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:07:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:07:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:07:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:07:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:07:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:07:11 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:07:11 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:07:11 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:07:11 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:07:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:07:11 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:07:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:07:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:07:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:07:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:07:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:07:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:07:11 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:07:11 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:07:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:07:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:07:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:07:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:07:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:07:12 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:07:12 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:07:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:07:12 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:07:12 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:07:12 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:07:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:07:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:07:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:07:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:07:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:07:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:07:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:07:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:07:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:07:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:07:12 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:07:12 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:07:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:07:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:07:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:07:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:07:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:07:13 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:07:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:07:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:07:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:07:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:07:13 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 04:07:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:07:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:07:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:07:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:07:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:07:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:07:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:07:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:07:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:07:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:07:13 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:07:13 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:07:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:07:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:07:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:07:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:07:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:07:13 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 04:07:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:07:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:07:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:07:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:07:14 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 04:07:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:07:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:07:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:07:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:07:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:07:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:07:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:07:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:07:14 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:07:14 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:07:14 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:07:14 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:07:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:07:14 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:07:14 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:07:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:07:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:07:14 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 04:07:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:07:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:07:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:07:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:07:15 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 04:07:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:07:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:07:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:07:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:07:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:07:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:07:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:07:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:07:15 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:07:15 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:07:15 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:07:15 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:07:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:07:15 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:07:15 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:07:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:07:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:07:15 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 04:07:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:07:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:07:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:07:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:07:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:07:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:07:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:07:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:07:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:07:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:07:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:07:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:07:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:07:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:07:16 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:07:16 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:07:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:07:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:07:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:07:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:07:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:07:16 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 04:07:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:07:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:07:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:07:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:07:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:07:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:07:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:07:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:07:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:07:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:07:16 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:07:16 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:07:16 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 04:07:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:07:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:07:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:07:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:07:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:07:17 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 04:07:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:07:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:07:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:07:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:07:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:07:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:07:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:07:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:07:17 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:07:17 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:07:17 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:07:17 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:07:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:07:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:07:17 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:07:17 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:07:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:07:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:07:17 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 04:07:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:07:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:07:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:07:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:07:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:07:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:07:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:07:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:07:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:07:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:07:18 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:07:18 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:07:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:07:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:07:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:07:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:07:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:07:18 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 04:07:18 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 04:07:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:07:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:07:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:07:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:07:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:07:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:07:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:07:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:07:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:07:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:07:18 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:07:18 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:07:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:07:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:07:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:07:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:07:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:07:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:07:19 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 04:07:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:07:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:07:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:07:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:07:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:07:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:07:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:07:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:07:19 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:07:19 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:07:19 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:07:19 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:07:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:07:19 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:07:19 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:07:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:07:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:07:19 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 04:07:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:07:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:07:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:07:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:07:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:07:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:07:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:07:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:07:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:07:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:07:20 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:07:20 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:07:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:07:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:07:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:07:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:07:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:07:20 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 04:07:20 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 04:07:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:07:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:07:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:07:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:07:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:07:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:07:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:07:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:07:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:07:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:07:20 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:07:20 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:07:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:07:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:07:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:07:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:07:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:07:21 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 04:07:21 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 04:07:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:07:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:07:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:07:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:07:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:07:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:07:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:07:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:07:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:07:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:07:21 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:07:21 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:07:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:07:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:07:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:07:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:07:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:07:22 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-27 04:07:22 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-27 04:07:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:07:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:07:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:07:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:07:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:07:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:07:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:07:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:07:22 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:07:22 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:07:22 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:07:22 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:07:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:07:22 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:07:22 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:07:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:07:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:07:23 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-27 04:07:23 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-27 04:07:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:07:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:07:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:07:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:07:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:07:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:07:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:07:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:07:23 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:07:23 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:07:23 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:07:23 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:07:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:07:23 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:07:23 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:07:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:07:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:07:23 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-27 04:07:24 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-27 04:07:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:07:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:07:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:07:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:07:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:07:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:07:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:07:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:07:24 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:07:24 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:07:24 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:07:24 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:07:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:07:24 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:07:24 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:07:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:07:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:07:24 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-27 04:07:25 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-27 04:07:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:07:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:07:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:07:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:07:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:07:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:07:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:07:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:07:25 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:07:25 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:07:25 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:07:25 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:07:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:07:25 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:07:25 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:07:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:07:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:07:25 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-27 04:07:26 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-27 04:07:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:07:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:07:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:07:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:07:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:07:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:07:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:07:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:07:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:07:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:07:26 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:07:26 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:07:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:07:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:07:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:07:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:07:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:07:26 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-27 04:07:27 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-27 04:07:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:07:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:07:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:07:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:07:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:07:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:07:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:07:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:07:27 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:07:27 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:07:27 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:07:27 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:07:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:07:27 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:07:27 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:07:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:07:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:07:27 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-27 04:07:28 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-27 04:07:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:07:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:07:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:07:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:07:28 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:07:28 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:07:28 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:07:28 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:07:28 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:07:28 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:07:28 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:07:28 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:07:28 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:07:28 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:07:28 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:07:28 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3710 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:07:28 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3710 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:07:28 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3710 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:07:28 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3710 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:07:28 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3710 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:07:28 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3710 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:07:28 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3710 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:07:28 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3710 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:07:33 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:07:33 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:07:33 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:07:33 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:07:33 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:07:33 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:07:33 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:07:33 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:07:33 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:07:33 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:07:33 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:07:33 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:07:33 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:07:33 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:07:33 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:07:33 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:07:33 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:07:33 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:07:33 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:07:33 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:07:33 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:07:33 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:07:33 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:07:33 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:07:33 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:07:33 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:07:33 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:07:33 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:07:33 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:07:33 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:07:33 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:07:33 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:07:33 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:07:33 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:07:33 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:07:33 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:07:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:07:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:07:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:07:33 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:07:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:07:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:07:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:07:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:07:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:07:33 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:07:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:07:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:07:33 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:07:33 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:07:33 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:07:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:07:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:07:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:07:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:07:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:07:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:07:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:07:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:07:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:07:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:07:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:07:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:07:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:07:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:07:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:07:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:07:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:07:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:07:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:07:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:07:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:07:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:07:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:07:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:07:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:07:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:07:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:07:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:07:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:07:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:07:33 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:07:33 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:07:33 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:07:33 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:07:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:07:33 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:07:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:07:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:07:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:07:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:07:34 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:07:34 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:07:34 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:07:34 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:07:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:07:34 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:07:34 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:07:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:07:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:07:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:07:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:07:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:07:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:07:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:07:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:07:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:07:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:07:34 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:07:34 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:07:34 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:07:34 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:07:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:07:34 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:07:34 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:07:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:07:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:07:34 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:07:34 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:07:34 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:07:34 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:07:34 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:07:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:07:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:07:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:07:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:07:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:07:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:07:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:07:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:07:34 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:07:34 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:07:34 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:07:34 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:07:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:07:34 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:07:34 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:07:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:07:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:07:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:07:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:07:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:07:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:07:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:07:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:07:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:07:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:07:34 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:07:34 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:07:34 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:07:34 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:07:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:07:34 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:07:34 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:07:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:07:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:07:34 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:07:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:07:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:07:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:07:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:07:35 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:07:35 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:07:35 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:07:35 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:07:35 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:07:35 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:07:35 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:07:35 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:07:35 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:07:35 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:07:35 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:07:40 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:07:40 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:07:40 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:07:40 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:07:40 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:07:40 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:07:40 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:07:40 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:07:40 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:07:40 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:07:40 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:07:40 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:07:40 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:07:40 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:07:40 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:07:40 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:07:40 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:07:40 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:07:40 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:07:40 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:07:40 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:07:40 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:07:40 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:07:40 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:07:40 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:07:40 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:07:40 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:07:40 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:07:40 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:07:40 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:07:40 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:07:40 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:07:40 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:07:40 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:07:40 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:07:40 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:07:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:07:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:07:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:07:40 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:07:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:07:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:07:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:07:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:07:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:07:40 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:07:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:07:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:07:40 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:07:40 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:07:40 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:07:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:07:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:07:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:07:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:07:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:07:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:07:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:07:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:07:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:07:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:07:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:07:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:07:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:07:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:07:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:07:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:07:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:07:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:07:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:07:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:07:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:07:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:07:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:07:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:07:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:07:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:07:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:07:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:07:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:07:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:07:40 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:07:40 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:07:41 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:07:41 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:07:42 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:07:42 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 04:07:43 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 04:07:43 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 04:07:43 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 04:07:44 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 04:07:44 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 04:07:45 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 04:07:45 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 04:07:46 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 04:07:46 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 04:07:47 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 04:07:47 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 04:07:48 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 04:07:48 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 04:07:49 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 04:07:49 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 04:07:50 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 04:07:50 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 04:07:51 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-27 04:07:51 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-27 04:07:52 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-27 04:07:52 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-27 04:07:53 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-27 04:07:53 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-27 04:07:53 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-27 04:07:54 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-27 04:07:54 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-27 04:07:55 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-27 04:07:55 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-27 04:07:56 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-27 04:07:56 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-27 04:07:57 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-27 04:07:57 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-27 04:07:58 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-27 04:07:58 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2025-04-27 04:07:59 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2025-04-27 04:07:59 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2025-04-27 04:08:00 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2025-04-27 04:08:00 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2025-04-27 04:08:01 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2025-04-27 04:08:01 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2025-04-27 04:08:02 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2025-04-27 04:08:02 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2025-04-27 04:08:03 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2025-04-27 04:08:03 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2025-04-27 04:08:04 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2025-04-27 04:08:04 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:08:04 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:08:04 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:08:04 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:08:04 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:08:04 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:08:04 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:08:04 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=5133 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:08:04 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=5133 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:08:04 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=5133 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:08:04 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=5133 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:08:04 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=5133 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:08:04 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=5133 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:08:04 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=5133 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:08:04 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=5133 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:08:09 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:08:09 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:08:09 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:08:09 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:08:09 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:08:09 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:08:09 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:08:09 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:08:09 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:08:09 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:08:09 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:08:09 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:08:09 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:08:09 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:08:09 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:08:09 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:08:09 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:08:09 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:08:09 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:08:09 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:08:09 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:08:09 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:08:09 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:08:09 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:08:09 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:08:09 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:08:09 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:08:09 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:08:09 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:08:09 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:08:09 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:08:09 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:08:09 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:08:09 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:08:09 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:08:09 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:08:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:08:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:08:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:08:09 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:08:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:08:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:08:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:08:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:08:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:08:09 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:08:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:08:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:08:09 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:08:09 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:08:09 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:08:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:08:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:08:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:08:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:08:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:08:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:08:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:08:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:08:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:08:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:08:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:08:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:08:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:08:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:08:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:08:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:08:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:08:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:08:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:08:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:08:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:08:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:08:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:08:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:08:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:08:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:08:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:08:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:08:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:08:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:08:09 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:08:09 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:08:10 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:08:10 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:08:11 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:08:11 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 04:08:12 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 04:08:12 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 04:08:13 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 04:08:13 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 04:08:14 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 04:08:14 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 04:08:14 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 04:08:15 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 04:08:15 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 04:08:16 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 04:08:16 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 04:08:17 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 04:08:17 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 04:08:18 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 04:08:18 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 04:08:19 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 04:08:19 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 04:08:20 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-27 04:08:20 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-27 04:08:21 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-27 04:08:21 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-27 04:08:22 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-27 04:08:22 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-27 04:08:23 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-27 04:08:23 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-27 04:08:24 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-27 04:08:24 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-27 04:08:25 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-27 04:08:25 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-27 04:08:25 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-27 04:08:26 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-27 04:08:26 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-27 04:08:27 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-27 04:08:27 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2025-04-27 04:08:28 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2025-04-27 04:08:28 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2025-04-27 04:08:29 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2025-04-27 04:08:29 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2025-04-27 04:08:30 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2025-04-27 04:08:30 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2025-04-27 04:08:31 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2025-04-27 04:08:31 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2025-04-27 04:08:32 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2025-04-27 04:08:32 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2025-04-27 04:08:33 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2025-04-27 04:08:33 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2025-04-27 04:08:34 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2025-04-27 04:08:34 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2025-04-27 04:08:35 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2025-04-27 04:08:35 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2025-04-27 04:08:36 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2025-04-27 04:08:36 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2025-04-27 04:08:36 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2025-04-27 04:08:37 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2025-04-27 04:08:37 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2025-04-27 04:08:38 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2025-04-27 04:08:38 [DEBUG] clck_gen.py:102 IND CLOCK 6324
2025-04-27 04:08:39 [DEBUG] clck_gen.py:102 IND CLOCK 6426
2025-04-27 04:08:39 [DEBUG] clck_gen.py:102 IND CLOCK 6528
2025-04-27 04:08:40 [DEBUG] clck_gen.py:102 IND CLOCK 6630
2025-04-27 04:08:40 [DEBUG] clck_gen.py:102 IND CLOCK 6732
2025-04-27 04:08:41 [DEBUG] clck_gen.py:102 IND CLOCK 6834
2025-04-27 04:08:41 [DEBUG] clck_gen.py:102 IND CLOCK 6936
2025-04-27 04:08:42 [DEBUG] clck_gen.py:102 IND CLOCK 7038
2025-04-27 04:08:42 [DEBUG] clck_gen.py:102 IND CLOCK 7140
2025-04-27 04:08:43 [DEBUG] clck_gen.py:102 IND CLOCK 7242
2025-04-27 04:08:43 [DEBUG] clck_gen.py:102 IND CLOCK 7344
2025-04-27 04:08:44 [DEBUG] clck_gen.py:102 IND CLOCK 7446
2025-04-27 04:08:44 [DEBUG] clck_gen.py:102 IND CLOCK 7548
2025-04-27 04:08:45 [DEBUG] clck_gen.py:102 IND CLOCK 7650
2025-04-27 04:08:45 [DEBUG] clck_gen.py:102 IND CLOCK 7752
2025-04-27 04:08:46 [DEBUG] clck_gen.py:102 IND CLOCK 7854
2025-04-27 04:08:46 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:08:46 [DEBUG] clck_gen.py:102 IND CLOCK 7956
2025-04-27 04:08:47 [DEBUG] clck_gen.py:102 IND CLOCK 8058
2025-04-27 04:08:47 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:08:47 [DEBUG] clck_gen.py:102 IND CLOCK 8160
2025-04-27 04:08:47 [DEBUG] clck_gen.py:102 IND CLOCK 8262
2025-04-27 04:08:48 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:08:48 [DEBUG] clck_gen.py:102 IND CLOCK 8364
2025-04-27 04:08:48 [DEBUG] clck_gen.py:102 IND CLOCK 8466
2025-04-27 04:08:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:08:49 [DEBUG] clck_gen.py:102 IND CLOCK 8568
2025-04-27 04:08:49 [DEBUG] clck_gen.py:102 IND CLOCK 8670
2025-04-27 04:08:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:08:50 [DEBUG] clck_gen.py:102 IND CLOCK 8772
2025-04-27 04:08:50 [DEBUG] clck_gen.py:102 IND CLOCK 8874
2025-04-27 04:08:51 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:08:51 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:08:51 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:08:51 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:08:51 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:08:51 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:08:51 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:08:51 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:08:56 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:08:56 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:08:56 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:08:56 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:08:56 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:08:56 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:08:56 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:08:56 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:08:56 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:08:56 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:08:56 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:08:56 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:08:56 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:08:56 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:08:56 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:08:56 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:08:56 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:08:56 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:08:56 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:08:56 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:08:56 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:08:56 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:08:56 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:08:56 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:08:56 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:08:56 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:08:56 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:08:56 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:08:56 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:08:56 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:08:56 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:08:56 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:08:56 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:08:56 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:08:56 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:08:56 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:08:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:08:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:08:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:08:56 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:08:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:08:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:08:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:08:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:08:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:08:56 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:08:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:08:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:08:56 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:08:56 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:08:56 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:08:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:08:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:08:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:08:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:08:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:08:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:08:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:08:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:08:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:08:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:08:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:08:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:08:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:08:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:08:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:08:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:08:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:08:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:08:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:08:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:08:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:08:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:08:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:08:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:08:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:08:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:08:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:08:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:08:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:08:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:08:56 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:08:56 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:08:56 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:08:56 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:08:56 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:08:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:08:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:08:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:08:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:08:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:08:56 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:08:56 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:08:56 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:08:56 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:08:56 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:08:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:08:56 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:08:56 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:08:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:08:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:08:57 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:08:57 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:08:57 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:08:57 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:08:57 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:08:57 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:08:58 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:08:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:08:58 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:08:58 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:08:58 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:08:58 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 04:08:59 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 04:08:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:08:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:08:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:08:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:08:59 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 04:09:00 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 04:09:00 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:09:00 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:09:00 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:09:00 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:09:00 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 04:09:01 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 04:09:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:09:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:09:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:09:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:09:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:09:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:09:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:09:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:09:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:09:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:09:01 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:09:01 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:09:01 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:09:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:09:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:09:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:09:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:09:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:09:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:09:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:09:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:09:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:09:01 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 04:09:01 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 04:09:02 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 04:09:02 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 04:09:03 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 04:09:03 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 04:09:04 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 04:09:04 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 04:09:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:09:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:09:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:09:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:09:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:09:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:09:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:09:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:09:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:09:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:09:05 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:09:05 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:09:05 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:09:05 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 04:09:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:09:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:09:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:09:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:09:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:09:05 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 04:09:06 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 04:09:06 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 04:09:07 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-27 04:09:07 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-27 04:09:08 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-27 04:09:08 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-27 04:09:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:09:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:09:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:09:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:09:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:09:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:09:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:09:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:09:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:09:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:09:09 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:09:09 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:09:09 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:09:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:09:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:09:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:09:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:09:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:09:09 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-27 04:09:09 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-27 04:09:10 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-27 04:09:10 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-27 04:09:10 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-27 04:09:11 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-27 04:09:11 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-27 04:09:12 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-27 04:09:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:09:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:09:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:09:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:09:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:09:12 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:09:12 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:09:12 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:09:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:09:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:09:12 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:09:12 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:09:12 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:09:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:09:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:09:12 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3558 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:09:12 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3558 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:09:12 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3558 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:09:12 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3558 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:09:12 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3558 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:09:12 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3559 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:09:12 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3559 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:09:12 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3559 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:09:12 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3559 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:09:12 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3559 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:09:12 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3559 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:09:12 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3559 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:09:12 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3559 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:09:17 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:09:17 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:09:17 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:09:17 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:09:17 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:09:17 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:09:17 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:09:17 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:09:17 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:09:17 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:09:17 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:09:17 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:09:17 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:09:17 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:09:17 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:09:17 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:09:17 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:09:17 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:09:17 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:09:17 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:09:17 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:09:17 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:09:17 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:09:17 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:09:17 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:09:17 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:09:17 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:09:17 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:09:17 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:09:17 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:09:17 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:09:17 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:09:17 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:09:17 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:09:17 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:09:17 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:09:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:09:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:09:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:09:17 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:09:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:09:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:09:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:09:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:09:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:09:17 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:09:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:09:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:09:17 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:09:17 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:09:17 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:09:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:09:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:09:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:09:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:09:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:09:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:09:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:09:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:09:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:09:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:09:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:09:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:09:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:09:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:09:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:09:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:09:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:09:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:09:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:09:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:09:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:09:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:09:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:09:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:09:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:09:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:09:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:09:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:09:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:09:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:09:17 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:09:18 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:09:18 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:09:18 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:09:18 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:09:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:09:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:09:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:09:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:09:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:09:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:09:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:09:18 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:09:18 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:09:18 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:09:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:09:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:09:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:09:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:09:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:09:18 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:09:18 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:09:18 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:09:18 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:09:18 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:09:19 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:09:19 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:09:19 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:09:19 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:09:19 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:09:19 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:09:19 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:09:19 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:09:20 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 04:09:20 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:09:20 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 04:09:20 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:09:20 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:09:20 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:09:20 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:09:20 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:09:21 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 04:09:21 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:09:21 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 04:09:21 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:09:21 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:09:21 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:09:21 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:09:21 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:09:22 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 04:09:22 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:09:22 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 04:09:22 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:09:22 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:09:22 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:09:22 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:09:22 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:09:23 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 04:09:23 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:09:23 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 04:09:23 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:09:24 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 04:09:24 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:09:24 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 04:09:24 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:09:24 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 04:09:25 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:09:25 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 04:09:25 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:09:25 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 04:09:26 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:09:26 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 04:09:26 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:09:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:09:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:09:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:09:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:09:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:09:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:09:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:09:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:09:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:09:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:09:26 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:09:26 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:09:26 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:09:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:09:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:09:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:09:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:09:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:09:26 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 04:09:27 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:09:27 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 04:09:27 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:09:27 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 04:09:28 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:09:28 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 04:09:28 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:09:28 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-27 04:09:29 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:09:29 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-27 04:09:29 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:09:29 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-27 04:09:30 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:09:30 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-27 04:09:30 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:09:30 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-27 04:09:31 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-27 04:09:31 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:09:31 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-27 04:09:31 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:09:32 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-27 04:09:32 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:09:32 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-27 04:09:32 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:09:33 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-27 04:09:33 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:09:33 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-27 04:09:33 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:09:34 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-27 04:09:34 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:09:34 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-27 04:09:34 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:09:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:09:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:09:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:09:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:09:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:09:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:09:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:09:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:09:34 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:09:34 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:09:34 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:09:34 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:09:34 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:09:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:09:34 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:09:34 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:09:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:09:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:09:34 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:09:35 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-27 04:09:35 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:09:35 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-27 04:09:35 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:09:35 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-27 04:09:36 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:09:36 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2025-04-27 04:09:36 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:09:36 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2025-04-27 04:09:37 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:09:37 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2025-04-27 04:09:37 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:09:37 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2025-04-27 04:09:38 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:09:38 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2025-04-27 04:09:38 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:09:38 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2025-04-27 04:09:39 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:09:39 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2025-04-27 04:09:39 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:09:39 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2025-04-27 04:09:40 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:09:40 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2025-04-27 04:09:40 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:09:40 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2025-04-27 04:09:41 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:09:41 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2025-04-27 04:09:41 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:09:41 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2025-04-27 04:09:42 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:09:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:09:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:09:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:09:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:09:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:09:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:09:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:09:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:09:42 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:09:42 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:09:42 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:09:42 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:09:42 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:09:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:09:42 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:09:42 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:09:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:09:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:09:42 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2025-04-27 04:09:42 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:09:42 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2025-04-27 04:09:42 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:09:43 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2025-04-27 04:09:43 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:09:43 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2025-04-27 04:09:43 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:09:44 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2025-04-27 04:09:44 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:09:44 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2025-04-27 04:09:44 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:09:44 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2025-04-27 04:09:45 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:09:45 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2025-04-27 04:09:45 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:09:45 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2025-04-27 04:09:46 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:09:46 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2025-04-27 04:09:46 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:09:46 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2025-04-27 04:09:47 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:09:47 [DEBUG] clck_gen.py:102 IND CLOCK 6324
2025-04-27 04:09:47 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:09:47 [DEBUG] clck_gen.py:102 IND CLOCK 6426
2025-04-27 04:09:48 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:09:48 [DEBUG] clck_gen.py:102 IND CLOCK 6528
2025-04-27 04:09:48 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:09:48 [DEBUG] clck_gen.py:102 IND CLOCK 6630
2025-04-27 04:09:49 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:09:49 [DEBUG] clck_gen.py:102 IND CLOCK 6732
2025-04-27 04:09:49 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:09:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:09:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:09:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:09:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:09:49 [WARNING] transceiver.py:250 (MS@172.18.127.22:6700) RX TRXD message (fn=6820 tn=1 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:09:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:09:49 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:09:49 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:09:49 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:09:49 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:09:49 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:09:49 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:09:49 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:09:49 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=6822 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:09:49 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:09:49 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:09:49 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:09:49 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=6822 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:09:49 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=6822 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:09:49 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=6822 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:09:49 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=6822 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:09:49 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=6822 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:09:49 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=6822 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:09:49 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=6823 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:09:49 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=6823 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:09:49 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=6823 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:09:49 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=6823 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:09:49 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=6823 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:09:49 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=6823 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:09:49 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=6823 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:09:49 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=6823 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:09:54 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:09:54 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:09:54 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:09:54 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:09:54 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:09:54 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:09:54 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:09:54 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:09:54 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:09:54 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:09:54 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:09:54 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:09:54 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:09:54 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:09:54 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:09:54 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:09:54 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:09:54 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:09:54 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:09:54 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:09:54 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:09:54 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:09:54 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:09:54 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:09:54 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:09:54 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:09:54 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:09:54 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:09:54 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:09:54 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:09:54 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:09:54 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:09:54 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:09:54 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:09:54 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:09:54 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:09:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:09:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:09:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:09:54 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:09:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:09:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:09:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:09:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:09:54 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:09:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:09:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:09:54 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:09:54 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:09:54 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:09:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:09:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:09:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:09:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:09:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:09:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:09:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:09:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:09:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:09:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:09:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:09:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:09:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:09:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:09:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:09:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:09:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:09:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:09:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:09:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:09:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:09:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:09:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:09:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:09:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:09:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:09:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:09:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:09:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:09:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:09:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:09:54 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:09:55 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:09:55 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:09:55 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:09:55 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:09:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:09:55 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:09:55 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:09:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:09:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:09:55 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:09:55 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:09:55 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:09:55 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:09:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:09:55 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:09:55 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:09:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:09:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:09:55 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:09:55 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:09:55 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:09:55 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:09:55 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:09:56 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:09:56 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:09:56 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:09:56 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:09:56 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:09:56 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:09:57 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 04:09:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:09:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:09:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:09:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:09:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:09:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:09:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:09:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:09:57 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:09:57 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:09:57 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:09:57 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:09:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:09:57 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:09:57 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:09:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:09:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:09:57 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 04:09:57 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:09:57 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:09:57 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:09:57 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:09:58 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 04:09:58 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 04:09:58 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:09:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:09:58 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:09:58 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:09:59 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 04:09:59 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 04:09:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:09:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:09:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:09:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:09:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:09:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:09:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:09:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:09:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:09:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:09:59 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:09:59 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:09:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:09:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:09:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:09:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:09:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:09:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:09:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:09:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:09:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:09:59 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 04:10:00 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 04:10:00 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 04:10:01 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 04:10:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:10:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:10:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:10:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:10:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:10:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:10:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:10:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:10:01 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:10:01 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:10:01 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:10:01 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:10:01 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:10:01 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:10:01 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:10:01 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1494 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:10:01 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1494 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:10:01 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1494 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:10:01 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1494 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:10:01 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1494 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:10:06 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:10:06 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:10:06 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:10:06 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:10:06 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:10:06 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:10:06 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:10:06 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:10:06 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:10:06 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:10:06 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:10:06 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:10:06 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:10:06 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:10:06 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:10:06 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:10:06 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:10:06 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:10:06 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:10:06 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:10:06 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:10:06 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:10:06 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:10:06 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:10:06 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:10:06 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:10:06 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:10:06 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:10:06 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:10:06 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:10:06 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:10:06 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:10:06 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:10:06 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:10:06 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:10:06 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:10:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:10:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:10:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:10:06 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:10:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:10:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:10:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:10:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:10:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:10:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:10:06 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:10:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:10:06 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:10:06 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:10:06 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:10:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:10:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:10:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:10:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:10:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:10:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:10:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:10:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:10:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:10:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:10:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:10:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:10:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:10:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:10:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:10:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:10:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:10:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:10:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:10:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:10:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:10:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:10:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:10:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:10:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:10:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:10:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:10:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:10:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:10:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:10:06 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:10:07 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:10:07 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:10:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:10:07 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:10:07 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:10:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:10:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:10:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:10:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:10:07 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:10:07 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:10:07 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:10:07 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:10:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:10:07 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:10:07 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:10:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:10:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:10:07 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:10:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:10:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:10:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:10:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:10:08 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:10:08 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:10:08 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:10:08 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:10:08 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:10:08 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:10:09 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 04:10:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:10:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:10:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:10:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:10:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:10:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:10:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:10:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:10:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:10:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:10:09 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:10:09 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:10:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:10:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:10:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:10:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:10:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:10:09 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 04:10:09 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:10:09 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:10:09 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:10:09 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:10:10 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 04:10:10 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 04:10:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:10:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:10:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:10:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:10:11 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 04:10:11 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 04:10:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:10:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:10:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:10:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:10:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:10:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:10:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:10:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:10:11 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:10:11 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:10:11 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:10:11 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:10:11 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:10:11 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:10:11 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1038 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:10:11 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:10:11 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1038 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:10:11 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1039 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:10:11 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1039 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:10:11 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1039 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:10:11 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1039 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:10:11 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1039 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:10:11 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1039 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:10:11 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1039 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:10:11 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1039 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:10:16 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:10:16 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:10:16 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:10:16 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:10:16 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:10:16 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:10:16 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:10:16 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:10:16 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:10:16 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:10:16 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:10:16 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:10:16 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:10:16 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:10:16 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:10:16 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:10:16 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:10:16 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:10:16 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:10:16 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:10:16 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:10:16 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:10:16 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:10:16 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:10:16 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:10:16 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:10:16 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:10:16 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:10:16 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:10:16 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:10:16 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:10:16 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:10:16 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:10:16 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:10:16 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:10:16 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:10:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:10:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:10:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:10:16 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:10:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:10:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:10:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:10:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:10:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:10:16 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:10:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:10:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:10:16 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:10:16 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:10:16 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:10:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:10:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:10:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:10:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:10:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:10:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:10:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:10:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:10:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:10:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:10:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:10:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:10:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:10:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:10:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:10:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:10:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:10:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:10:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:10:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:10:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:10:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:10:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:10:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:10:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:10:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:10:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:10:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:10:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:10:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:10:16 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:10:17 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:10:17 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:10:17 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:10:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:10:17 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:10:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:10:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:10:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:10:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:10:17 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:10:17 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:10:17 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:10:17 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:10:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:10:17 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:10:17 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:10:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:10:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:10:17 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:10:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:10:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:10:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:10:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:10:18 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:10:18 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:10:18 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:10:18 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:10:18 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:10:18 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:10:19 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 04:10:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:10:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:10:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:10:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:10:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:10:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:10:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:10:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:10:19 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:10:19 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:10:19 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:10:19 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:10:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:10:19 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:10:19 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:10:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:10:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:10:19 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 04:10:19 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:10:19 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:10:19 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:10:19 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:10:19 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 04:10:20 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 04:10:20 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:10:20 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:10:20 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:10:20 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:10:20 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 04:10:21 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 04:10:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:10:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:10:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:10:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:10:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:10:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:10:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:10:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:10:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:10:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:10:21 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:10:21 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:10:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:10:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:10:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:10:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:10:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:10:21 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:10:21 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:10:21 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:10:21 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:10:21 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 04:10:22 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 04:10:22 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 04:10:23 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 04:10:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:10:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:10:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:10:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:10:23 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:10:23 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:10:23 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:10:23 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:10:23 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:10:23 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:10:23 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:10:23 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:10:23 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:10:23 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:10:23 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:10:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1498 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:10:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1498 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:10:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1498 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:10:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1498 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:10:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1498 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:10:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1498 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:10:28 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:10:28 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:10:28 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:10:28 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:10:28 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:10:28 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:10:28 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:10:28 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:10:28 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:10:28 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:10:28 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:10:28 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:10:28 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:10:28 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:10:28 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:10:28 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:10:28 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:10:28 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:10:28 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:10:28 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:10:28 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:10:28 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:10:28 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:10:28 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:10:28 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:10:28 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:10:28 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:10:28 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:10:28 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:10:28 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:10:28 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:10:28 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:10:28 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:10:28 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:10:28 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:10:28 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:10:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:10:28 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:10:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:10:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:10:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:10:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:10:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:10:28 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:10:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:10:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:10:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:10:28 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:10:28 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:10:28 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:10:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:10:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:10:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:10:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:10:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:10:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:10:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:10:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:10:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:10:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:10:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:10:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:10:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:10:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:10:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:10:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:10:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:10:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:10:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:10:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:10:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:10:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:10:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:10:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:10:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:10:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:10:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:10:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:10:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:10:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:10:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:10:28 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:10:29 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:10:29 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:10:29 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:10:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:10:29 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:10:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:10:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:10:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:10:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:10:29 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:10:29 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:10:29 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:10:29 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:10:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:10:29 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:10:29 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:10:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:10:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:10:29 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:10:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:10:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:10:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:10:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:10:30 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:10:30 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:10:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:10:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:10:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:10:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:10:31 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 04:10:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:10:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:10:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:10:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:10:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:10:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:10:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:10:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:10:31 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:10:31 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:10:31 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:10:31 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:10:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:10:31 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:10:31 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:10:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:10:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:10:31 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 04:10:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:10:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:10:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:10:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:10:31 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 04:10:32 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 04:10:32 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:10:32 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:10:32 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:10:32 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:10:32 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 04:10:33 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 04:10:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:10:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:10:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:10:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:10:33 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:10:33 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:10:33 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:10:33 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:10:33 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:10:33 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:10:33 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:10:33 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:10:33 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:10:33 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:10:33 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:10:38 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:10:38 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:10:38 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:10:38 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:10:38 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:10:38 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:10:38 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:10:38 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:10:38 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:10:38 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:10:38 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:10:38 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:10:38 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:10:38 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:10:38 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:10:38 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:10:38 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:10:38 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:10:38 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:10:38 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:10:38 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:10:38 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:10:38 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:10:38 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:10:38 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:10:38 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:10:38 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:10:38 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:10:38 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:10:38 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:10:38 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:10:38 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:10:38 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:10:38 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:10:38 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:10:38 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:10:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:10:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:10:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:10:38 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:10:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:10:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:10:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:10:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:10:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:10:38 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:10:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:10:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:10:38 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:10:38 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:10:38 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:10:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:10:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:10:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:10:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:10:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:10:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:10:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:10:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:10:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:10:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:10:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:10:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:10:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:10:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:10:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:10:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:10:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:10:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:10:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:10:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:10:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:10:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:10:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:10:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:10:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:10:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:10:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:10:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:10:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:10:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:10:38 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:10:38 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:10:38 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:10:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:10:38 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:10:38 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:10:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:10:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:10:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:10:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:10:39 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:10:39 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:10:39 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:10:39 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:10:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:10:39 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:10:39 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:10:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:10:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:10:39 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:10:39 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:10:39 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:10:39 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:10:39 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:10:39 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:10:40 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:10:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:10:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:10:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:10:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:10:40 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 04:10:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:10:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:10:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:10:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:10:41 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:10:41 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:10:41 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:10:41 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:10:41 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:10:41 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:10:41 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:10:41 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:10:41 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:10:41 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:10:41 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:10:41 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=591 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:10:41 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=591 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:10:41 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=591 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:10:41 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=591 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:10:41 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=591 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:10:41 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=591 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:10:41 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=592 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:10:41 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=592 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:10:41 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=592 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:10:41 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=592 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:10:41 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=592 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:10:41 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=592 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:10:41 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=592 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:10:41 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=592 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:10:46 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:10:46 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:10:46 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:10:46 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:10:46 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:10:46 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:10:46 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:10:46 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:10:46 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:10:46 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:10:46 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:10:46 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:10:46 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:10:46 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:10:46 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:10:46 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:10:46 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:10:46 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:10:46 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:10:46 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:10:46 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:10:46 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:10:46 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:10:46 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:10:46 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:10:46 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:10:46 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:10:46 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:10:46 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:10:46 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:10:46 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:10:46 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:10:46 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:10:46 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:10:46 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:10:46 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:10:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:10:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:10:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:10:46 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:10:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:10:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:10:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:10:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:10:46 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:10:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:10:46 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:10:46 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:10:46 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:10:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:10:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:10:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:10:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:10:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:10:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:10:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:10:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:10:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:10:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:10:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:10:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:10:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:10:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:10:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:10:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:10:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:10:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:10:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:10:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:10:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:10:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:10:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:10:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:10:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:10:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:10:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:10:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:10:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:10:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:10:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:10:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:10:46 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:10:46 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:10:46 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:10:46 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:10:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:10:46 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:10:46 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:10:46 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:10:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:10:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:10:46 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:10:46 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:10:46 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:10:46 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:10:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:10:46 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:10:46 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:10:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:10:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:10:47 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:10:47 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:10:47 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:10:47 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:10:47 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:10:47 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:10:48 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:10:48 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:10:48 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:10:48 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:10:48 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:10:48 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 04:10:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:10:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:10:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:10:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:10:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:10:49 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:10:49 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:10:49 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:10:49 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:10:49 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:10:49 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:10:49 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:10:49 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:10:49 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:10:49 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:10:54 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:10:54 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:10:54 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:10:54 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:10:54 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:10:54 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:10:54 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:10:54 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:10:54 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:10:54 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:10:54 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:10:54 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:10:54 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:10:54 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:10:54 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:10:54 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:10:54 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:10:54 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:10:54 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:10:54 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:10:54 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:10:54 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:10:54 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:10:54 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:10:54 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:10:54 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:10:54 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:10:54 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:10:54 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:10:54 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:10:54 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:10:54 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:10:54 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:10:54 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:10:54 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:10:54 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:10:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:10:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:10:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:10:54 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:10:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:10:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:10:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:10:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:10:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:10:54 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:10:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:10:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:10:54 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:10:54 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:10:54 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:10:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:10:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:10:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:10:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:10:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:10:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:10:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:10:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:10:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:10:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:10:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:10:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:10:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:10:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:10:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:10:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:10:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:10:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:10:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:10:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:10:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:10:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:10:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:10:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:10:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:10:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:10:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:10:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:10:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:10:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:10:54 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:10:54 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:10:54 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:10:54 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:10:54 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:10:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:10:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:10:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:10:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:10:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:10:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:10:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:10:54 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:10:54 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:10:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:10:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:10:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:10:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:10:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:10:55 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:10:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:10:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:10:55 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:10:55 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:10:55 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:10:55 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:10:55 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:10:55 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:10:55 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:10:55 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:10:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:10:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:10:55 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:10:55 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:10:55 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:10:55 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:10:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:10:55 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:10:55 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:10:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:10:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:10:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:10:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:10:55 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:10:55 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:10:55 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:10:55 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:10:55 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:10:55 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:10:55 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:10:55 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:10:55 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:10:55 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:10:55 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:10:55 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=310 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:10:55 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:10:55 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:10:55 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:10:55 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=310 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:10:55 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=310 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:11:00 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:11:00 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:11:00 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:11:00 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:11:00 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:11:00 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:11:00 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:11:00 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:11:00 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:11:00 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:11:00 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:11:00 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:11:00 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:11:00 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:11:00 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:11:00 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:11:00 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:11:00 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:11:00 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:11:00 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:11:00 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:11:00 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:11:00 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:11:00 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:11:00 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:11:00 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:11:00 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:11:00 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:11:00 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:11:00 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:11:00 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:11:00 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:11:00 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:11:00 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:11:00 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:11:00 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:11:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:11:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:11:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:11:00 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:11:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:11:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:11:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:11:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:11:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:11:00 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:11:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:11:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:11:00 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:11:00 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:11:00 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:11:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:11:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:11:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:11:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:11:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:11:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:11:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:11:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:11:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:11:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:11:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:11:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:11:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:11:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:11:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:11:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:11:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:11:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:11:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:11:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:11:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:11:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:11:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:11:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:11:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:11:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:11:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:11:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:11:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:11:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:11:00 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:11:01 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:11:01 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:11:01 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:11:01 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:11:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:11:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:11:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:11:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:11:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:11:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:11:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:11:01 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:11:01 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:11:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:11:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:11:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:11:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:11:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:11:01 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:11:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:11:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:11:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:11:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:11:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:11:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:11:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:11:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:11:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:11:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:11:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:11:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:11:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:11:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:11:01 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:11:01 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:11:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:11:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:11:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:11:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:11:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:11:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:11:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:11:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:11:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:11:01 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:11:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:11:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:11:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:11:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:11:01 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:11:01 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:11:02 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:11:02 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:11:02 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:11:02 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:11:02 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:11:07 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:11:07 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:11:07 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:11:07 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:11:07 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:11:07 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:11:07 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:11:07 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:11:07 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:11:07 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:11:07 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:11:07 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:11:07 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:11:07 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:11:07 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:11:07 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:11:07 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:11:07 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:11:07 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:11:07 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:11:07 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:11:07 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:11:07 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:11:07 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:11:07 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:11:07 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:11:07 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:11:07 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:11:07 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:11:07 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:11:07 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:11:07 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:11:07 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:11:07 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:11:07 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:11:07 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:11:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:11:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:11:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:11:07 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:11:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:11:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:11:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:11:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:11:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:11:07 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:11:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:11:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:11:07 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:11:07 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:11:07 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:11:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:11:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:11:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:11:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:11:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:11:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:11:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:11:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:11:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:11:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:11:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:11:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:11:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:11:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:11:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:11:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:11:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:11:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:11:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:11:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:11:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:11:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:11:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:11:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:11:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:11:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:11:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:11:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:11:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:11:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:11:07 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:11:07 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:11:07 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:11:07 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:11:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:11:07 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:11:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:11:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:11:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:11:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:11:07 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:11:07 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:11:07 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:11:07 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:11:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:11:07 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:11:07 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:11:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:11:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:11:08 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:11:08 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:11:08 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:11:08 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:11:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:11:08 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:11:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:11:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:11:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:11:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:11:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:11:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:11:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:11:08 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:11:08 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:11:08 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:11:08 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:11:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:11:08 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:11:08 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:11:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:11:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:11:08 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:11:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:11:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:11:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:11:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:11:08 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:11:08 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:11:08 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:11:08 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:11:08 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:11:08 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:11:08 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:11:08 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:11:08 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:11:08 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:11:08 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:11:08 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=319 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:11:08 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=319 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:11:08 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=319 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:11:08 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=319 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:11:08 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=319 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:11:08 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=319 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:11:08 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=319 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:11:08 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=319 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:11:13 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:11:13 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:11:13 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:11:13 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:11:13 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:11:13 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:11:13 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:11:13 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:11:13 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:11:13 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:11:13 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:11:13 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:11:13 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:11:13 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:11:13 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:11:13 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:11:13 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:11:13 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:11:13 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:11:13 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:11:13 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:11:13 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:11:13 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:11:13 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:11:13 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:11:13 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:11:13 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:11:13 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:11:13 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:11:13 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:11:13 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:11:13 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:11:13 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:11:13 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:11:13 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:11:13 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:11:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:11:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:11:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:11:13 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:11:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:11:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:11:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:11:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:11:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:11:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:11:13 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:11:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:11:13 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:11:13 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:11:13 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:11:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:11:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:11:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:11:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:11:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:11:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:11:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:11:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:11:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:11:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:11:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:11:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:11:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:11:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:11:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:11:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:11:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:11:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:11:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:11:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:11:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:11:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:11:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:11:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:11:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:11:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:11:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:11:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:11:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:11:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:11:13 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:11:14 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:11:14 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:11:14 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:11:14 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:11:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:11:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:11:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:11:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:11:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:11:14 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:11:14 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:11:14 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:11:14 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:11:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:11:14 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:11:14 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:11:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:11:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:11:14 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:11:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:11:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:11:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:11:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:11:14 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:11:15 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:11:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:11:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:11:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:11:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:11:15 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 04:11:16 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 04:11:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:11:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:11:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:11:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:11:16 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 04:11:17 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 04:11:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:11:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:11:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:11:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:11:17 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 04:11:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:11:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:11:18 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:11:18 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:11:18 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:11:18 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:11:18 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:11:18 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:11:18 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:11:18 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:11:18 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:11:18 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:11:18 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:11:23 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:11:23 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:11:23 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:11:23 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:11:23 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:11:23 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:11:23 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:11:23 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:11:23 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:11:23 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:11:23 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:11:23 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:11:23 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:11:23 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:11:23 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:11:23 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:11:23 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:11:23 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:11:23 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:11:23 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:11:23 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:11:23 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:11:23 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:11:23 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:11:23 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:11:23 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:11:23 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:11:23 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:11:23 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:11:23 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:11:23 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:11:23 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:11:23 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:11:23 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:11:23 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:11:23 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:11:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:11:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:11:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:11:23 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:11:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:11:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:11:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:11:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:11:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:11:23 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:11:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:11:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:11:23 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:11:23 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:11:23 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:11:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:11:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:11:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:11:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:11:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:11:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:11:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:11:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:11:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:11:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:11:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:11:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:11:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:11:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:11:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:11:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:11:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:11:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:11:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:11:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:11:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:11:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:11:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:11:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:11:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:11:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:11:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:11:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:11:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:11:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:11:23 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:11:23 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:11:23 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:11:23 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:11:23 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:11:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:11:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:11:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:11:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:11:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:11:23 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:11:23 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:11:23 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:11:23 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:11:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:11:23 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:11:23 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:11:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:11:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:11:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:11:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:11:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:11:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:11:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:11:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:11:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:11:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:11:24 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:11:24 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:11:24 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:11:24 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:11:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:11:24 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:11:24 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:11:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:11:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:11:24 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:11:24 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:11:24 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:11:24 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:11:24 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:11:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:11:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:11:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:11:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:11:24 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:11:24 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:11:24 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:11:24 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:11:24 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:11:24 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:11:24 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:11:24 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:11:24 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:11:24 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:11:24 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:11:29 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:11:29 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:11:29 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:11:29 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:11:29 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:11:29 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:11:29 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:11:29 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:11:29 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:11:29 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:11:29 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:11:29 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:11:29 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:11:29 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:11:29 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:11:29 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:11:29 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:11:29 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:11:29 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:11:29 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:11:29 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:11:29 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:11:29 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:11:29 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:11:29 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:11:29 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:11:29 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:11:29 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:11:29 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:11:29 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:11:29 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:11:29 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:11:29 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:11:29 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:11:29 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:11:29 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:11:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:11:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:11:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:11:29 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:11:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:11:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:11:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:11:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:11:29 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:11:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:11:29 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:11:29 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:11:29 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:11:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:11:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:11:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:11:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:11:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:11:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:11:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:11:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:11:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:11:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:11:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:11:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:11:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:11:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:11:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:11:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:11:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:11:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:11:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:11:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:11:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:11:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:11:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:11:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:11:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:11:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:11:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:11:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:11:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:11:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:11:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:11:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:11:29 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:11:29 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:11:29 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:11:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:11:29 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:11:29 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:11:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:11:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:11:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:11:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:11:29 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:11:29 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:11:29 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:11:29 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:11:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:11:29 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:11:29 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:11:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:11:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:11:30 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:11:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:11:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:11:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:11:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:11:30 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:11:31 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:11:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:11:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:11:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:11:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:11:31 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 04:11:32 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 04:11:32 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:11:32 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:11:32 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:11:32 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:11:32 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 04:11:33 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 04:11:33 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:11:33 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:11:33 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:11:33 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:11:33 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 04:11:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:11:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:11:33 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:11:33 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:11:33 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:11:33 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:11:33 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:11:33 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:11:33 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:11:33 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:11:33 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:11:33 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:11:33 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:11:33 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=998 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:11:33 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=998 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:11:33 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=998 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:11:33 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=998 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:11:33 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=998 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:11:33 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=998 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:11:33 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=999 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:11:33 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=999 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:11:33 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=999 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:11:33 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=999 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:11:33 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=999 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:11:33 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=999 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:11:33 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=999 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:11:33 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=999 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:11:38 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:11:38 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:11:38 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:11:38 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:11:38 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:11:38 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:11:38 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:11:38 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:11:38 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:11:38 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:11:38 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:11:38 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:11:38 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:11:38 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:11:38 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:11:38 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:11:38 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:11:38 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:11:38 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:11:38 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:11:38 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:11:38 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:11:38 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:11:38 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:11:38 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:11:38 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:11:38 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:11:38 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:11:38 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:11:38 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:11:38 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:11:38 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:11:38 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:11:38 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:11:38 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:11:38 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:11:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:11:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:11:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:11:38 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:11:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:11:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:11:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:11:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:11:38 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:11:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:11:38 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:11:38 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:11:38 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:11:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:11:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:11:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:11:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:11:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:11:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:11:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:11:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:11:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:11:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:11:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:11:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:11:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:11:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:11:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:11:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:11:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:11:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:11:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:11:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:11:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:11:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:11:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:11:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:11:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:11:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:11:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:11:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:11:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:11:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:11:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:11:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:11:38 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:11:39 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:11:39 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:11:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:11:39 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:11:39 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:11:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:11:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:11:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:11:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:11:39 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:11:39 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:11:39 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:11:39 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:11:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:11:39 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:11:39 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:11:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:11:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:11:39 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:11:39 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:11:39 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:11:39 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:11:39 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:11:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:11:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:11:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:11:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:11:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:11:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:11:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:11:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:11:40 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:11:40 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:11:40 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:11:40 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:11:40 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:11:40 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:11:40 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:11:40 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=294 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:11:40 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=294 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:11:40 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=294 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:11:40 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=294 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:11:40 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=294 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:11:40 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=294 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:11:40 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=295 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:11:40 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=295 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:11:40 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=295 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:11:40 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=295 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:11:40 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=295 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:11:40 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=295 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:11:40 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=295 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:11:40 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=295 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:11:45 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:11:45 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:11:45 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:11:45 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:11:45 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:11:45 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:11:45 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:11:45 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:11:45 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:11:45 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:11:45 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:11:45 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:11:45 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:11:45 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:11:45 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:11:45 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:11:45 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:11:45 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:11:45 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:11:45 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:11:45 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:11:45 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:11:45 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:11:45 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:11:45 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:11:45 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:11:45 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:11:45 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:11:45 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:11:45 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:11:45 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:11:45 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:11:45 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:11:45 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:11:45 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:11:45 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:11:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:11:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:11:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:11:45 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:11:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:11:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:11:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:11:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:11:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:11:45 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:11:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:11:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:11:45 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:11:45 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:11:45 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:11:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:11:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:11:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:11:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:11:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:11:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:11:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:11:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:11:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:11:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:11:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:11:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:11:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:11:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:11:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:11:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:11:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:11:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:11:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:11:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:11:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:11:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:11:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:11:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:11:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:11:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:11:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:11:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:11:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:11:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:11:45 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:11:45 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:11:45 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:11:45 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:11:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:11:45 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:11:45 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:11:45 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:11:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:11:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:11:45 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:11:45 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:11:45 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:11:45 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:11:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:11:46 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:11:46 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:11:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:11:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:11:46 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:11:46 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:11:46 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:11:46 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:11:46 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:11:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:11:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:11:46 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:11:46 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:11:46 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:11:46 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:11:46 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:11:46 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:11:46 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:11:46 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:11:46 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:11:46 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:11:46 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:11:46 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:11:46 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:11:46 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=293 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:11:46 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=293 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:11:46 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=293 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:11:46 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=293 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:11:46 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=293 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:11:46 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=293 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:11:51 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:11:51 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:11:51 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:11:51 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:11:51 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:11:51 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:11:51 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:11:51 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:11:51 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:11:51 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:11:51 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:11:51 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:11:51 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:11:51 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:11:51 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:11:51 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:11:51 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:11:51 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:11:51 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:11:51 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:11:51 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:11:51 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:11:51 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:11:51 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:11:51 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:11:51 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:11:51 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:11:51 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:11:51 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:11:51 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:11:51 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:11:51 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:11:51 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:11:51 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:11:51 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:11:51 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:11:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:11:51 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:11:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:11:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:11:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:11:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:11:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:11:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:11:51 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:11:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:11:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:11:51 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:11:51 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:11:51 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:11:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:11:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:11:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:11:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:11:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:11:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:11:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:11:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:11:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:11:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:11:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:11:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:11:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:11:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:11:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:11:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:11:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:11:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:11:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:11:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:11:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:11:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:11:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:11:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:11:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:11:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:11:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:11:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:11:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:11:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:11:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:11:51 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:11:52 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:11:52 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:11:52 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:11:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:11:52 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:11:52 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:11:52 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:11:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:11:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:11:52 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:11:52 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:11:52 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:11:52 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:11:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:11:52 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:11:52 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:11:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:11:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:11:52 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:11:52 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:11:52 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:11:52 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:11:52 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:11:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:11:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:11:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:11:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:11:53 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:11:53 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:11:53 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:11:53 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:11:53 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:11:53 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:11:53 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:11:53 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:11:53 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:11:53 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:11:53 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=293 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:11:53 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:11:53 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=293 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:11:53 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=293 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:11:53 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=294 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:11:53 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=294 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:11:53 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=294 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:11:53 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=294 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:11:53 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=294 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:11:53 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=294 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:11:53 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=294 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:11:53 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=294 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:11:58 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:11:58 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:11:58 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:11:58 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:11:58 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:11:58 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:11:58 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:11:58 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:11:58 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:11:58 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:11:58 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:11:58 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:11:58 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:11:58 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:11:58 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:11:58 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:11:58 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:11:58 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:11:58 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:11:58 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:11:58 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:11:58 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:11:58 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:11:58 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:11:58 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:11:58 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:11:58 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:11:58 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:11:58 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:11:58 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:11:58 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:11:58 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:11:58 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:11:58 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:11:58 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:11:58 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:11:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:11:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:11:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:11:58 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:11:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:11:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:11:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:11:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:11:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:11:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:11:58 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:11:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:11:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:11:58 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:11:58 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:11:58 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:11:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:11:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:11:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:11:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:11:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:11:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:11:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:11:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:11:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:11:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:11:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:11:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:11:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:11:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:11:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:11:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:11:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:11:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:11:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:11:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:11:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:11:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:11:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:11:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:11:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:11:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:11:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:11:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:11:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:11:58 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:11:58 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:11:58 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:11:58 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:11:58 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:11:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:11:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:11:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:11:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:11:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:11:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:11:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:11:58 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:11:58 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:11:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:11:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:11:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:11:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:11:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:11:59 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:11:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:11:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:11:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:11:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:11:59 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:11:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:11:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:11:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:11:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:11:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:11:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:11:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:11:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:11:59 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:11:59 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:11:59 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:11:59 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:11:59 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:11:59 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=322 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:11:59 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:11:59 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:11:59 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=322 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:11:59 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=322 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:11:59 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=323 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:11:59 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=323 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:11:59 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=323 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:11:59 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=323 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:11:59 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=323 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:11:59 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=323 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:11:59 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=323 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:11:59 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=323 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:11:59 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=324 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:11:59 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=324 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:11:59 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=324 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:11:59 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=324 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:11:59 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=324 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:11:59 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=324 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:11:59 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=324 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:11:59 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=324 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:12:04 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:12:04 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:12:04 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:12:04 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:12:04 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:12:04 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:12:04 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:12:04 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:12:04 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:12:04 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:12:04 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:12:04 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:12:04 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:12:04 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:12:04 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:12:04 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:12:04 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:12:04 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:12:04 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:12:04 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:12:04 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:12:04 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:12:04 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:12:04 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:12:04 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:12:04 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:12:04 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:12:04 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:12:04 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:12:04 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:12:04 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:12:04 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:12:04 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:12:04 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:12:04 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:12:04 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:12:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:12:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:12:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:12:04 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:12:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:12:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:12:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:12:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:12:04 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:12:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:12:04 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:12:04 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:12:04 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:12:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:12:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:12:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:12:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:12:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:12:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:12:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:12:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:12:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:12:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:12:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:12:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:12:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:12:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:12:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:12:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:12:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:12:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:12:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:12:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:12:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:12:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:12:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:12:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:12:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:12:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:12:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:12:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:12:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:12:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:12:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:12:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:12:04 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:12:05 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:12:05 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:12:05 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:12:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:12:05 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:12:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:12:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:12:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:12:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:12:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:12:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:12:05 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:12:05 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:12:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:12:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:12:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:12:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:12:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:12:05 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:12:05 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:12:05 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:12:05 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:12:05 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:12:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:12:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:12:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:12:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:12:06 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:12:06 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:12:06 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:12:06 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:12:06 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:12:06 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:12:06 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:12:06 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:12:06 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:12:06 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:12:06 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:12:06 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=294 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:12:06 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=294 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:12:06 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=294 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:12:06 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=294 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:12:06 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=294 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:12:06 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=294 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:12:06 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=294 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:12:11 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:12:11 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:12:11 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:12:11 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:12:11 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:12:11 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:12:11 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:12:11 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:12:11 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:12:11 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:12:11 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:12:11 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:12:11 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:12:11 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:12:11 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:12:11 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:12:11 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:12:11 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:12:11 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:12:11 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:12:11 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:12:11 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:12:11 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:12:11 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:12:11 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:12:11 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:12:11 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:12:11 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:12:11 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:12:11 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:12:11 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:12:11 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:12:11 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:12:11 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:12:11 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:12:11 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:12:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:12:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:12:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:12:11 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:12:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:12:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:12:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:12:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:12:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:12:11 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:12:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:12:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:12:11 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:12:11 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:12:11 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:12:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:12:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:12:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:12:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:12:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:12:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:12:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:12:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:12:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:12:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:12:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:12:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:12:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:12:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:12:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:12:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:12:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:12:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:12:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:12:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:12:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:12:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:12:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:12:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:12:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:12:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:12:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:12:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:12:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:12:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:12:11 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:12:11 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:12:11 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:12:11 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:12:11 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:12:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:12:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:12:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:12:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:12:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:12:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:12:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:12:11 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:12:11 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:12:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:12:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:12:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:12:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:12:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:12:12 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:12:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:12:12 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:12:12 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:12:12 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:12:12 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:12:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:12:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:12:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:12:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:12:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:12:12 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:12:12 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:12:12 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:12:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:12:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:12:12 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:12:12 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:12:12 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:12:12 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=322 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:12:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:12:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:12:12 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=322 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:12:12 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=322 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:12:12 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=322 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:12:12 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=322 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:12:12 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=323 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:12:12 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=323 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:12:12 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=323 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:12:12 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=323 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:12:12 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=323 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:12:12 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=323 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:12:12 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=323 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:12:12 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=323 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:12:17 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:12:17 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:12:17 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:12:17 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:12:17 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:12:17 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:12:17 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:12:17 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:12:17 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:12:17 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:12:17 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:12:17 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:12:17 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:12:17 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:12:17 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:12:17 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:12:17 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:12:17 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:12:17 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:12:17 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:12:17 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:12:17 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:12:17 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:12:17 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:12:17 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:12:17 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:12:17 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:12:17 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:12:17 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:12:17 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:12:17 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:12:17 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:12:17 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:12:17 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:12:17 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:12:17 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:12:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:12:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:12:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:12:17 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:12:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:12:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:12:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:12:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:12:17 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:12:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:12:17 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:12:17 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:12:17 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:12:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:12:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:12:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:12:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:12:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:12:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:12:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:12:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:12:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:12:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:12:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:12:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:12:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:12:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:12:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:12:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:12:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:12:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:12:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:12:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:12:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:12:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:12:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:12:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:12:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:12:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:12:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:12:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:12:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:12:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:12:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:12:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:12:17 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:12:18 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:12:18 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:12:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:12:18 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:12:18 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:12:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:12:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:12:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:12:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:12:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:12:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:12:18 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:12:18 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:12:18 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:12:18 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:12:18 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:12:18 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:12:18 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:12:19 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:12:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:12:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:12:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:12:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:12:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:12:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:12:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:12:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:12:19 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:12:19 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:12:19 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:12:19 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:12:19 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:12:19 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:12:19 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:12:19 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:12:19 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:12:20 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 04:12:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD NOHANDOVER
2025-04-27 04:12:20 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 04:12:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD NOHANDOVER
2025-04-27 04:12:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:12:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:12:20 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:12:20 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:12:20 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:12:20 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:12:20 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:12:20 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:12:20 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:12:20 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:12:20 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:12:20 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=625 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:12:20 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:12:20 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:12:20 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=625 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:12:20 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=625 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:12:20 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=625 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:12:20 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=625 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:12:20 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=625 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:12:20 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=625 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:12:20 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=626 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:12:20 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=626 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:12:20 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=626 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:12:20 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=626 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:12:20 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=626 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:12:20 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=626 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:12:20 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=626 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:12:20 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=626 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:12:25 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:12:25 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:12:25 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:12:25 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:12:25 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:12:25 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:12:25 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:12:25 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:12:25 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:12:25 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:12:25 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:12:25 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:12:25 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:12:25 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:12:25 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:12:25 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:12:25 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:12:25 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:12:25 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:12:25 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:12:25 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:12:25 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:12:25 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:12:25 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:12:25 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:12:25 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:12:25 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:12:25 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:12:25 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:12:25 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:12:25 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:12:25 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:12:25 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:12:25 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:12:25 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:12:25 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:12:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:12:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:12:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:12:25 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:12:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:12:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:12:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:12:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:12:25 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:12:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:12:25 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:12:25 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:12:25 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:12:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:12:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:12:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:12:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:12:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:12:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:12:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:12:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:12:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:12:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:12:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:12:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:12:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:12:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:12:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:12:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:12:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:12:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:12:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:12:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:12:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:12:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:12:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:12:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:12:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:12:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:12:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:12:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:12:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:12:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:12:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:12:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:12:25 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:12:26 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:12:26 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:12:26 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:12:26 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:12:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:12:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:12:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:12:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:12:26 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:12:26 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:12:26 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:12:26 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:12:26 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:12:27 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:12:27 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:12:27 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:12:27 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:12:27 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:12:27 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:12:28 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 04:12:28 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 04:12:28 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:12:28 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:12:28 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:12:28 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:12:29 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 04:12:29 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 04:12:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:12:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:12:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:12:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:12:29 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 04:12:30 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 04:12:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:12:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:12:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:12:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:12:30 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 04:12:31 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 04:12:31 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 04:12:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:12:32 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:12:32 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:12:32 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:12:32 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:12:32 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 04:12:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD NOHANDOVER
2025-04-27 04:12:32 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:12:32 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:12:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:12:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:12:32 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 04:12:33 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 04:12:33 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 04:12:34 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 04:12:34 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 04:12:35 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 04:12:35 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 04:12:36 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 04:12:36 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-27 04:12:37 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-27 04:12:37 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-27 04:12:38 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-27 04:12:38 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-27 04:12:39 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-27 04:12:39 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-27 04:12:40 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-27 04:12:40 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-27 04:12:41 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-27 04:12:41 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-27 04:12:41 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-27 04:12:42 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-27 04:12:42 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-27 04:12:43 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-27 04:12:43 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-27 04:12:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD NOHANDOVER
2025-04-27 04:12:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:12:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:12:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:12:44 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:12:44 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:12:44 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:12:44 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:12:44 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:12:44 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:12:44 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:12:44 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:12:44 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:12:44 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:12:44 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:12:49 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:12:49 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:12:49 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:12:49 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:12:49 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:12:49 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:12:49 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:12:49 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:12:49 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:12:49 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:12:49 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:12:49 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:12:49 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:12:49 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:12:49 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:12:49 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:12:49 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:12:49 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:12:49 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:12:49 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:12:49 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:12:49 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:12:49 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:12:49 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:12:49 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:12:49 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:12:49 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:12:49 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:12:49 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:12:49 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:12:49 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:12:49 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:12:49 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:12:49 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:12:49 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:12:49 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:12:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:12:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:12:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:12:49 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:12:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:12:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:12:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:12:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:12:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:12:49 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:12:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:12:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:12:49 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:12:49 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:12:49 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:12:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:12:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:12:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:12:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:12:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:12:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:12:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:12:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:12:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:12:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:12:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:12:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:12:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:12:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:12:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:12:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:12:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:12:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:12:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:12:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:12:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:12:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:12:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:12:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:12:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:12:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:12:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:12:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:12:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:12:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:12:49 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:12:49 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:12:49 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:12:49 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:12:49 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:12:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:12:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:12:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:12:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:12:50 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:12:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:12:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:12:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:12:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:12:50 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:12:51 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:12:51 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:12:51 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:12:51 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:12:51 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:12:51 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 04:12:52 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 04:12:52 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:12:52 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:12:52 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:12:52 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:12:52 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 04:12:53 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 04:12:53 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:12:53 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:12:53 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:12:53 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:12:53 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 04:12:54 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 04:12:54 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:12:54 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:12:54 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:12:54 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:12:54 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 04:12:54 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 04:12:55 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 04:12:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:12:55 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:12:55 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:12:55 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:12:55 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:12:55 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 04:12:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD NOHANDOVER
2025-04-27 04:12:55 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:12:55 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:12:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:12:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:12:56 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 04:12:56 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 04:12:57 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 04:12:57 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 04:12:58 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 04:12:58 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 04:12:59 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 04:12:59 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 04:13:00 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-27 04:13:00 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-27 04:13:01 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-27 04:13:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD NOHANDOVER
2025-04-27 04:13:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:13:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:13:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:13:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:13:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:13:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:13:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:13:01 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:13:01 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:13:01 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:13:01 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:13:01 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:13:01 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:13:01 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:13:01 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2590 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:13:01 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2590 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:13:01 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2590 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:13:01 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2590 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:13:01 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2590 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:13:01 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2590 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:13:01 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2590 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:13:06 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:13:06 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:13:06 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:13:06 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:13:06 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:13:06 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:13:06 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:13:06 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:13:06 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:13:06 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:13:06 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:13:06 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:13:06 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:13:06 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:13:06 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:13:06 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:13:06 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:13:06 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:13:06 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:13:06 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:13:06 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:13:06 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:13:06 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:13:06 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:13:06 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:13:06 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:13:06 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:13:06 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:13:06 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:13:06 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:13:06 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:13:06 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:13:06 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:13:06 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:13:06 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:13:06 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:13:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:13:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:13:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:13:06 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:13:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:13:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:13:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:13:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:13:06 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:13:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:13:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:13:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:13:06 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:13:06 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:13:06 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:13:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:13:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:13:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:13:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:13:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:13:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:13:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:13:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:13:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:13:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:13:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:13:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:13:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:13:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:13:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:13:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:13:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:13:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:13:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:13:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:13:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:13:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:13:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:13:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:13:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:13:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:13:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:13:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:13:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:13:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:13:06 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:13:06 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:13:06 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:13:06 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:13:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:13:06 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:13:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:13:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:13:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:13:07 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:13:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:13:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:13:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:13:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:13:07 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:13:08 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:13:08 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:13:08 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:13:08 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:13:08 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:13:08 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 04:13:09 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 04:13:09 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:13:09 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:13:09 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:13:09 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:13:09 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 04:13:10 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 04:13:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:13:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:13:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:13:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:13:10 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 04:13:11 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 04:13:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:13:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:13:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:13:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:13:11 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 04:13:12 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 04:13:12 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 04:13:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:13:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:13:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:13:12 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:13:12 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:13:13 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 04:13:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD NOHANDOVER
2025-04-27 04:13:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:13:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:13:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:13:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:13:13 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 04:13:14 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 04:13:14 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 04:13:14 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 04:13:15 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 04:13:15 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 04:13:16 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 04:13:16 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 04:13:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD NOHANDOVER
2025-04-27 04:13:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:13:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:13:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:13:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:13:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:13:17 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:13:17 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:13:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:13:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:13:17 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:13:17 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:13:17 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:13:17 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:13:17 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:13:17 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2277 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:13:17 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2277 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:13:17 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2277 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:13:17 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2277 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:13:17 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2277 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:13:17 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2277 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:13:17 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2278 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:13:17 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2278 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:13:17 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2278 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:13:17 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2278 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:13:17 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2278 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:13:17 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2278 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:13:17 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2278 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:13:17 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2278 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:13:22 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:13:22 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:13:22 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:13:22 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:13:22 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:13:22 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:13:22 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:13:22 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:13:22 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:13:22 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:13:22 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:13:22 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:13:22 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:13:22 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:13:22 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:13:22 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:13:22 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:13:22 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:13:22 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:13:22 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:13:22 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:13:22 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:13:22 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:13:22 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:13:22 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:13:22 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:13:22 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:13:22 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:13:22 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:13:22 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:13:22 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:13:22 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:13:22 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:13:22 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:13:22 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:13:22 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:13:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:13:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:13:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:13:22 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:13:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:13:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:13:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:13:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:13:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:13:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:13:22 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:13:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:13:22 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:13:22 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:13:22 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:13:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:13:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:13:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:13:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:13:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:13:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:13:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:13:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:13:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:13:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:13:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:13:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:13:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:13:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:13:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:13:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:13:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:13:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:13:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:13:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:13:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:13:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:13:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:13:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:13:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:13:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:13:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:13:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:13:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:13:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:13:22 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:13:22 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:13:22 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:13:22 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:13:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:13:22 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:13:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:13:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:13:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:13:23 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:13:23 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:13:23 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:13:23 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:13:23 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:13:23 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:13:24 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:13:24 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:13:24 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:13:24 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:13:24 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:13:24 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 04:13:24 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 04:13:25 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:13:25 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:13:25 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:13:25 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:13:25 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 04:13:25 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 04:13:26 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:13:26 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:13:26 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:13:26 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:13:26 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 04:13:26 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 04:13:27 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:13:27 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:13:27 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:13:27 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:13:27 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 04:13:27 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 04:13:28 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 04:13:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:13:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:13:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:13:28 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:13:28 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:13:28 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 04:13:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD NOHANDOVER
2025-04-27 04:13:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:13:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:13:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:13:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:13:29 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 04:13:29 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 04:13:30 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 04:13:30 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 04:13:31 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 04:13:31 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 04:13:32 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 04:13:32 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 04:13:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD NOHANDOVER
2025-04-27 04:13:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:13:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:13:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:13:32 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:13:32 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:13:32 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:13:32 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:13:32 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:13:32 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:13:32 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:13:32 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:13:32 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:13:32 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:13:32 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:13:32 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2277 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:13:32 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2277 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:13:32 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2277 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:13:32 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2277 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:13:32 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2277 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:13:32 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2277 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:13:32 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2277 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:13:37 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:13:37 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:13:37 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:13:37 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:13:37 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:13:37 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:13:37 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:13:37 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:13:37 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:13:37 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:13:37 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:13:37 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:13:37 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:13:37 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:13:37 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:13:37 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:13:37 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:13:37 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:13:37 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:13:37 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:13:37 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:13:37 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:13:37 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:13:37 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:13:37 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:13:37 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:13:37 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:13:37 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:13:37 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:13:37 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:13:37 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:13:37 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:13:37 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:13:37 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:13:37 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:13:37 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:13:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:13:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:13:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:13:37 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:13:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:13:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:13:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:13:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:13:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:13:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:13:37 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:13:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:13:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:13:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:13:37 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:13:37 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:13:37 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:13:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:13:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:13:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:13:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:13:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:13:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:13:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:13:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:13:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:13:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:13:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:13:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:13:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:13:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:13:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:13:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:13:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:13:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:13:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:13:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:13:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:13:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:13:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:13:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:13:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:13:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:13:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:13:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:13:37 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:13:38 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:13:38 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:13:38 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:13:38 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:13:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:13:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:13:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:13:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:13:38 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:13:38 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:13:38 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:13:38 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:13:38 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:13:39 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:13:39 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:13:39 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:13:39 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:13:39 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:13:39 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:13:40 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 04:13:40 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 04:13:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:13:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:13:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:13:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:13:41 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 04:13:41 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 04:13:41 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:13:41 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:13:41 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:13:41 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:13:42 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 04:13:42 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 04:13:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:13:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:13:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:13:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:13:43 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 04:13:43 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 04:13:44 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 04:13:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:13:44 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:13:44 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:13:44 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:13:44 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:13:44 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 04:13:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD NOHANDOVER
2025-04-27 04:13:44 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:13:44 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:13:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:13:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:13:45 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 04:13:45 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 04:13:45 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 04:13:46 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 04:13:46 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 04:13:47 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 04:13:47 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 04:13:48 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 04:13:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD NOHANDOVER
2025-04-27 04:13:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:13:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:13:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:13:48 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:13:48 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:13:48 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:13:48 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:13:48 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:13:48 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:13:48 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:13:48 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:13:48 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:13:48 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:13:48 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:13:48 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2277 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:13:48 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2277 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:13:48 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2277 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:13:48 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2277 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:13:48 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2277 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:13:48 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2277 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:13:48 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2278 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:13:48 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2278 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:13:48 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2278 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:13:48 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2278 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:13:48 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2278 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:13:48 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2278 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:13:48 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2278 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:13:48 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2278 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:13:53 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:13:53 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:13:53 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:13:53 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:13:53 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:13:53 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:13:53 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:13:53 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:13:53 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:13:53 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:13:53 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:13:53 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:13:53 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:13:53 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:13:53 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:13:53 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:13:53 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:13:53 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:13:53 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:13:53 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:13:53 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:13:53 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:13:53 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:13:53 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:13:53 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:13:53 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:13:53 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:13:53 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:13:53 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:13:53 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:13:53 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:13:53 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:13:53 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:13:53 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:13:53 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:13:53 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:13:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:13:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:13:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:13:53 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:13:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:13:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:13:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:13:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:13:53 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:13:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:13:53 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:13:53 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:13:53 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:13:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:13:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:13:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:13:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:13:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:13:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:13:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:13:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:13:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:13:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:13:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:13:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:13:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:13:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:13:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:13:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:13:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:13:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:13:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:13:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:13:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:13:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:13:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:13:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:13:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:13:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:13:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:13:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:13:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:13:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:13:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:13:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:13:53 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:13:54 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:13:54 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:13:54 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:13:54 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:13:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:13:54 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:13:54 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:13:54 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:13:54 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:13:54 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:13:55 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:13:55 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:13:55 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:13:55 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:13:55 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:13:55 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:13:55 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 04:13:56 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 04:13:56 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:13:56 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:13:56 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:13:56 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:13:56 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 04:13:57 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 04:13:57 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:13:57 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:13:57 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:13:57 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:13:57 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 04:13:58 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 04:13:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:13:58 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:13:58 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:13:58 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:13:58 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 04:13:59 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 04:13:59 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 04:14:00 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 04:14:00 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 04:14:01 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 04:14:01 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 04:14:02 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 04:14:02 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 04:14:03 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 04:14:03 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 04:14:04 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 04:14:04 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:14:04 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:14:04 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:14:04 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:14:04 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:14:04 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:14:04 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:14:04 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:14:04 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2261 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:14:04 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:14:04 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:14:04 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:14:04 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2261 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:14:04 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2261 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:14:04 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2261 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:14:04 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2261 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:14:09 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:14:09 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:14:09 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:14:09 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:14:09 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:14:09 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:14:09 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:14:09 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:14:09 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:14:09 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:14:09 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:14:09 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:14:09 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:14:09 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:14:09 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:14:09 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:14:09 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:14:09 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:14:09 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:14:09 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:14:09 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:14:09 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:14:09 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:14:09 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:14:09 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:14:09 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:14:09 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:14:09 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:14:09 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:14:09 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:14:09 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:14:09 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:14:09 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:14:09 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:14:09 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:14:09 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:14:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:14:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:14:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:14:09 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:14:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:14:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:14:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:14:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:14:09 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:14:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:14:09 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:14:09 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:14:09 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:14:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:14:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:14:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:14:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:14:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:14:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:14:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:14:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:14:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:14:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:14:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:14:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:14:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:14:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:14:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:14:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:14:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:14:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:14:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:14:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:14:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:14:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:14:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:14:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:14:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:14:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:14:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:14:09 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:14:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:14:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:14:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:14:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:14:09 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:14:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:14:09 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:14:09 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:14:09 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:14:09 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:14:09 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:14:14 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:14:14 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:14:14 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:14:14 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:14:14 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:14:14 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:14:14 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:14:14 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:14:14 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:14:14 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:14:14 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:14:14 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:14:14 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:14:14 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:14:14 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:14:14 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:14:14 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:14:14 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:14:14 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:14:14 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:14:14 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:14:14 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:14:14 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:14:14 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:14:14 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:14:14 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:14:14 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:14:14 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:14:14 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:14:14 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:14:14 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:14:14 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:14:14 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:14:14 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:14:14 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:14:14 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:14:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:14:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:14:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:14:14 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:14:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:14:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:14:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:14:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:14:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:14:14 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:14:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:14:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:14:14 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:14:14 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:14:14 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:14:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:14:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:14:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:14:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:14:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:14:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:14:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:14:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:14:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:14:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:14:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:14:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:14:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:14:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:14:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:14:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:14:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:14:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:14:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:14:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:14:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:14:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:14:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:14:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:14:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:14:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:14:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:14:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:14:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:14:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:14:14 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:14:14 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:14:14 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:14:14 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:14:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:14:14 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:14:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:14:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:14:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:14:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:14:14 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:14:14 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:14:14 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:14:14 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:14:15 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:14:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:14:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:14:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:14:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:14:15 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:14:16 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:14:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:14:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:14:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:14:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:14:16 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 04:14:17 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 04:14:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:14:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:14:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:14:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:14:17 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 04:14:17 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 04:14:18 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:14:18 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:14:18 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:14:18 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:14:18 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 04:14:18 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 04:14:19 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:14:19 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:14:19 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:14:19 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:14:19 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 04:14:19 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 04:14:20 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 04:14:20 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 04:14:21 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 04:14:21 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 04:14:22 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 04:14:22 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:14:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:14:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:14:22 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:14:22 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:14:22 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:14:22 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:14:22 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:14:22 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:14:22 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:14:22 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1833 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:14:22 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:14:22 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:14:22 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:14:22 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1833 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:14:22 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1833 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:14:22 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1833 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:14:22 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1834 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:14:22 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1834 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:14:22 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1834 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:14:22 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1834 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:14:22 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1834 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:14:22 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1834 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:14:22 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1834 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:14:22 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1834 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:14:27 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:14:27 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:14:27 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:14:27 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:14:27 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:14:27 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:14:27 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:14:27 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:14:27 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:14:27 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:14:27 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:14:27 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:14:27 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:14:27 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:14:27 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:14:27 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:14:27 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:14:27 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:14:27 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:14:27 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:14:27 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:14:27 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:14:27 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:14:27 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:14:27 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:14:27 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:14:27 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:14:27 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:14:27 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:14:27 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:14:27 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:14:27 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:14:27 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:14:27 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:14:27 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:14:27 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:14:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:14:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:14:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:14:27 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:14:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:14:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:14:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:14:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:14:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:14:27 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:14:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:14:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:14:27 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:14:27 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:14:27 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:14:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:14:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:14:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:14:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:14:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:14:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:14:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:14:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:14:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:14:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:14:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:14:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:14:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:14:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:14:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:14:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:14:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:14:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:14:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:14:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:14:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:14:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:14:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:14:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:14:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:14:27 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:14:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:14:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:14:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:14:27 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:14:27 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:14:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:14:27 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:14:27 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:14:27 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:14:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:14:32 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:14:32 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:14:32 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:14:32 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:14:32 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:14:32 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:14:32 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:14:32 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:14:32 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:14:32 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:14:32 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:14:32 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:14:32 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:14:32 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:14:32 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:14:32 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:14:32 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:14:32 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:14:32 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:14:32 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:14:32 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:14:32 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:14:32 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:14:32 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:14:32 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:14:32 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:14:32 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:14:32 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:14:32 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:14:32 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:14:32 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:14:32 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:14:32 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:14:32 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:14:32 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:14:32 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:14:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:14:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:14:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:14:32 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:14:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:14:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:14:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:14:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:14:32 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:14:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:14:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:14:32 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:14:32 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:14:32 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:14:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:14:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:14:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:14:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:14:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:14:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:14:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:14:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:14:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:14:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:14:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:14:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:14:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:14:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:14:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:14:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:14:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:14:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:14:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:14:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:14:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:14:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:14:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:14:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:14:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:14:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:14:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:14:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:14:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:14:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:14:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:14:32 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:14:33 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:14:33 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:14:33 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:14:33 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:14:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:14:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:14:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:14:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:14:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:14:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:14:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:14:33 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:14:33 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:14:33 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:14:33 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:14:33 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:14:33 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:14:33 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:14:34 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:14:34 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:14:34 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:14:34 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:14:34 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:14:34 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:14:35 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 04:14:35 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 04:14:35 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:14:35 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:14:35 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:14:35 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:14:36 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 04:14:36 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 04:14:36 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:14:36 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:14:36 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:14:36 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:14:37 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 04:14:37 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 04:14:37 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:14:37 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:14:37 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:14:37 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:14:38 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 04:14:38 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 04:14:39 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 04:14:39 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 04:14:39 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 04:14:40 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 04:14:40 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 04:14:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:14:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:14:41 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:14:41 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:14:41 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:14:41 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:14:41 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:14:41 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:14:41 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:14:41 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:14:41 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:14:41 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1824 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:14:41 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:14:41 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:14:41 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1824 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:14:41 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1824 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:14:41 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1824 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:14:41 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1824 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:14:41 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1824 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:14:46 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:14:46 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:14:46 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:14:46 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:14:46 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:14:46 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:14:46 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:14:46 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:14:46 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:14:46 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:14:46 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:14:46 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:14:46 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:14:46 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:14:46 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:14:46 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:14:46 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:14:46 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:14:46 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:14:46 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:14:46 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:14:46 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:14:46 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:14:46 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:14:46 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:14:46 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:14:46 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:14:46 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:14:46 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:14:46 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:14:46 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:14:46 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:14:46 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:14:46 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:14:46 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:14:46 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:14:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:14:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:14:46 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:14:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:14:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:14:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:14:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:14:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:14:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:14:46 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:14:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:14:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:14:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:14:46 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:14:46 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:14:46 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:14:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:14:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:14:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:14:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:14:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:14:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:14:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:14:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:14:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:14:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:14:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:14:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:14:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:14:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:14:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:14:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:14:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:14:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:14:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:14:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:14:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:14:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:14:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:14:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:14:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:14:46 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:14:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:14:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:14:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:14:46 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:14:46 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:14:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:14:46 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:14:46 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:14:46 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:14:46 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:14:51 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:14:51 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:14:51 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:14:51 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:14:51 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:14:51 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:14:51 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:14:51 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:14:51 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:14:51 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:14:51 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:14:51 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:14:51 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:14:51 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:14:51 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:14:51 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:14:51 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:14:51 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:14:51 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:14:51 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:14:51 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:14:51 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:14:51 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:14:51 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:14:51 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:14:51 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:14:51 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:14:51 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:14:51 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:14:51 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:14:51 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:14:51 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:14:51 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:14:51 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:14:51 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:14:51 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:14:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:14:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:14:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:14:51 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:14:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:14:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:14:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:14:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:14:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:14:51 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:14:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:14:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:14:51 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:14:51 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:14:51 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:14:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:14:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:14:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:14:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:14:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:14:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:14:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:14:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:14:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:14:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:14:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:14:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:14:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:14:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:14:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:14:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:14:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:14:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:14:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:14:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:14:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:14:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:14:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:14:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:14:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:14:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:14:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:14:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:14:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:14:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:14:51 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:14:51 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:14:51 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:14:51 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:14:51 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:14:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:14:51 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:14:51 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:14:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:14:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:14:51 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:14:51 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:14:51 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:14:51 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:14:52 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:14:52 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:14:52 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:14:52 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:14:52 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:14:52 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:14:53 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:14:53 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:14:53 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:14:53 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:14:53 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:14:53 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 04:14:54 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 04:14:54 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:14:54 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:14:54 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:14:54 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:14:54 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 04:14:55 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 04:14:55 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:14:55 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:14:55 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:14:55 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:14:55 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 04:14:56 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 04:14:56 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:14:56 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:14:56 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:14:56 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:14:56 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 04:14:57 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 04:14:57 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 04:14:58 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 04:14:58 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 04:14:59 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 04:14:59 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 04:14:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:14:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:14:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:14:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:14:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:14:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:14:59 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:14:59 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:14:59 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:14:59 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:14:59 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:14:59 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:14:59 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:14:59 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1838 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:14:59 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1838 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:14:59 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1838 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:14:59 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1838 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:14:59 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1838 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:14:59 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1838 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:15:04 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:15:04 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:15:04 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:15:04 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:15:04 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:15:04 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:15:04 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:15:04 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:15:04 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:15:04 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:15:04 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:15:04 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:15:04 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:15:04 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:15:04 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:15:04 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:15:04 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:15:04 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:15:04 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:15:04 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:15:04 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:15:04 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:15:04 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:15:04 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:15:04 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:15:04 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:15:04 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:15:04 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:15:04 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:15:04 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:15:04 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:15:05 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:15:05 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:15:05 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:15:05 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:15:05 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:15:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:15:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:15:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:15:05 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:15:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:15:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:15:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:15:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:15:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:15:05 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:15:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:15:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:15:05 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:15:05 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:15:05 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:15:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:15:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:15:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:15:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:15:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:15:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:15:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:15:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:15:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:15:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:15:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:15:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:15:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:15:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:15:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:15:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:15:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:15:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:15:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:15:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:15:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:15:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:15:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:15:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:15:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:15:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:15:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:15:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:15:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:15:05 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:15:05 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:15:05 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:15:05 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:15:05 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:15:05 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:15:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:15:10 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:15:10 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:15:10 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:15:10 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:15:10 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:15:10 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:15:10 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:15:10 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:15:10 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:15:10 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:15:10 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:15:10 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:15:10 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:15:10 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:15:10 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:15:10 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:15:10 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:15:10 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:15:10 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:15:10 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:15:10 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:15:10 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:15:10 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:15:10 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:15:10 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:15:10 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:15:10 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:15:10 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:15:10 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:15:10 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:15:10 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:15:10 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:15:10 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:15:10 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:15:10 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:15:10 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:15:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:15:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:15:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:15:10 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:15:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:15:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:15:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:15:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:15:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:15:10 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:15:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:15:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:15:10 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:15:10 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:15:10 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:15:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:15:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:15:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:15:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:15:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:15:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:15:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:15:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:15:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:15:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:15:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:15:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:15:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:15:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:15:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:15:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:15:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:15:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:15:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:15:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:15:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:15:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:15:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:15:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:15:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:15:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:15:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:15:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:15:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:15:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:15:10 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:15:10 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:15:10 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:15:10 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:15:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:15:10 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:15:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:15:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:15:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:15:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:15:10 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:15:10 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:15:10 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:15:10 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:15:11 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:15:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:15:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:15:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:15:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:15:11 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:15:11 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:15:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:15:12 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:15:12 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:15:12 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:15:12 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 04:15:12 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 04:15:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:15:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:15:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:15:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:15:13 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 04:15:13 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 04:15:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:15:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:15:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:15:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:15:14 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 04:15:14 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 04:15:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:15:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:15:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:15:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:15:15 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 04:15:15 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 04:15:16 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 04:15:16 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 04:15:17 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 04:15:17 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 04:15:18 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 04:15:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:15:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:15:18 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:15:18 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:15:18 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:15:18 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:15:18 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:15:18 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:15:18 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:15:18 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:15:18 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:15:18 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:15:18 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:15:18 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1835 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:15:18 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1835 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:15:18 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1835 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:15:18 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1835 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:15:18 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1835 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:15:18 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1835 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:15:23 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:15:23 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:15:23 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:15:23 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:15:23 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:15:23 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:15:23 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:15:23 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:15:23 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:15:23 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:15:23 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:15:23 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:15:23 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:15:23 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:15:23 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:15:23 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:15:23 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:15:23 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:15:23 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:15:23 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:15:23 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:15:23 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:15:23 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:15:23 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:15:23 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:15:23 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:15:23 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:15:23 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:15:23 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:15:23 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:15:23 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:15:23 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:15:23 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:15:23 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:15:23 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:15:23 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:15:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:15:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:15:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:15:23 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:15:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:15:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:15:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:15:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:15:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:15:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:15:23 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:15:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:15:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:15:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:15:23 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:15:23 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:15:23 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:15:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:15:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:15:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:15:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:15:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:15:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:15:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:15:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:15:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:15:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:15:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:15:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:15:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:15:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:15:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:15:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:15:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:15:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:15:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:15:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:15:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:15:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:15:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:15:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:15:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:15:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:15:23 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:15:23 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:15:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:15:23 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:15:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:15:23 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:15:23 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:15:23 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:15:23 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:15:28 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:15:28 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:15:28 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:15:28 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:15:28 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:15:28 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:15:28 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:15:28 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:15:28 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:15:28 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:15:28 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:15:28 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:15:28 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:15:28 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:15:28 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:15:28 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:15:28 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:15:28 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:15:28 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:15:28 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:15:28 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:15:28 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:15:28 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:15:28 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:15:28 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:15:28 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:15:28 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:15:28 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:15:28 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:15:28 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:15:28 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:15:28 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:15:28 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:15:28 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:15:28 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:15:28 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:15:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:15:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:15:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:15:28 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:15:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:15:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:15:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:15:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:15:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:15:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:15:28 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:15:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:15:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:15:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:15:28 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:15:28 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:15:28 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:15:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:15:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:15:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:15:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:15:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:15:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:15:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:15:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:15:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:15:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:15:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:15:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:15:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:15:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:15:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:15:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:15:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:15:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:15:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:15:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:15:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:15:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:15:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:15:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:15:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:15:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:15:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:15:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:15:28 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:15:29 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:15:29 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:15:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:15:29 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:15:29 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:15:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:15:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:15:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:15:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:15:29 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:15:29 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:15:29 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:15:29 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:15:29 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:15:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:15:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:15:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:15:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:15:30 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:15:30 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:15:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:15:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:15:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:15:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:15:31 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 04:15:31 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 04:15:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:15:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:15:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:15:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:15:32 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 04:15:32 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 04:15:32 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:15:32 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:15:32 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:15:32 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:15:32 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 04:15:33 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 04:15:33 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:15:33 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:15:33 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:15:33 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:15:33 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 04:15:34 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 04:15:34 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 04:15:35 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 04:15:35 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 04:15:36 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 04:15:36 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 04:15:37 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 04:15:37 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 04:15:38 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 04:15:38 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 04:15:39 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 04:15:39 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-27 04:15:40 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-27 04:15:40 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-27 04:15:41 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-27 04:15:41 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-27 04:15:42 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-27 04:15:42 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-27 04:15:42 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-27 04:15:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:15:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:15:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:15:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:15:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:15:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:15:43 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:15:43 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:15:43 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:15:43 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:15:43 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:15:43 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:15:43 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:15:48 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:15:48 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:15:48 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:15:48 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:15:48 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:15:48 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:15:48 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:15:48 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:15:48 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:15:48 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:15:48 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:15:48 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:15:48 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:15:48 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:15:48 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:15:48 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:15:48 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:15:48 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:15:48 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:15:48 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:15:48 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:15:48 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:15:48 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:15:48 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:15:48 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:15:48 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:15:48 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:15:48 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:15:48 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:15:48 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:15:48 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:15:48 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:15:48 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:15:48 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:15:48 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:15:48 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:15:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:15:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:15:48 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:15:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:15:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:15:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:15:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:15:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:15:48 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:15:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:15:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:15:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:15:48 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:15:48 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:15:48 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:15:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:15:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:15:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:15:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:15:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:15:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:15:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:15:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:15:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:15:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:15:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:15:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:15:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:15:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:15:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:15:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:15:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:15:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:15:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:15:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:15:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:15:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:15:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:15:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:15:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:15:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:15:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:15:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:15:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:15:48 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:15:48 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:15:48 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:15:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:15:48 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:15:48 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:15:48 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:15:48 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:15:53 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:15:53 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:15:53 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:15:53 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:15:53 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:15:53 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:15:53 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:15:53 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:15:53 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:15:53 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:15:53 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:15:53 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:15:53 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:15:53 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:15:53 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:15:53 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:15:53 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:15:53 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:15:53 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:15:53 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:15:53 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:15:53 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:15:53 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:15:53 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:15:53 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:15:53 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:15:53 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:15:53 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:15:53 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:15:53 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:15:53 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:15:53 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:15:53 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:15:53 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:15:53 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:15:53 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:15:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:15:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:15:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:15:53 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:15:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:15:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:15:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:15:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:15:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:15:53 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:15:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:15:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:15:53 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:15:53 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:15:53 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:15:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:15:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:15:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:15:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:15:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:15:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:15:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:15:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:15:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:15:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:15:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:15:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:15:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:15:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:15:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:15:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:15:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:15:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:15:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:15:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:15:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:15:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:15:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:15:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:15:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:15:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:15:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:15:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:15:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:15:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:15:53 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:15:53 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:15:53 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:15:53 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:15:53 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:15:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:15:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:15:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:15:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:15:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:15:53 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:15:53 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:15:53 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:15:53 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:15:54 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:15:54 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:15:54 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:15:54 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:15:54 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:15:54 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:15:55 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:15:55 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:15:55 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:15:55 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:15:55 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:15:55 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 04:15:56 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 04:15:56 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:15:56 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:15:56 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:15:56 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:15:56 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 04:15:57 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 04:15:57 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:15:57 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:15:57 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:15:57 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:15:57 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 04:15:58 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 04:15:58 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:15:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:15:58 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:15:58 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:15:58 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 04:15:59 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 04:15:59 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 04:16:00 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 04:16:00 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 04:16:00 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 04:16:01 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 04:16:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:16:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:16:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:16:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:16:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:16:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:16:01 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:16:01 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:16:01 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:16:01 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:16:01 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:16:01 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:16:01 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:16:01 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1827 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:16:01 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1827 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:16:01 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1827 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:16:01 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1827 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:16:01 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1827 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:16:01 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1827 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:16:01 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1828 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:16:01 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1828 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:16:01 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1828 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:16:01 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1828 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:16:01 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1828 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:16:01 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1828 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:16:01 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1828 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:16:01 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1828 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:16:06 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:16:06 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:16:06 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:16:06 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:16:06 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:16:06 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:16:06 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:16:06 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:16:06 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:16:06 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:16:06 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:16:06 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:16:06 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:16:06 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:16:06 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:16:06 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:16:06 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:16:06 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:16:06 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:16:06 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:16:06 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:16:06 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:16:06 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:16:06 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:16:06 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:16:06 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:16:06 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:16:06 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:16:06 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:16:06 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:16:06 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:16:06 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:16:06 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:16:06 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:16:06 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:16:06 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:16:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:16:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:16:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:16:06 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:16:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:16:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:16:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:16:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:16:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:16:06 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:16:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:16:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:16:06 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:16:06 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:16:06 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:16:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:16:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:16:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:16:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:16:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:16:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:16:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:16:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:16:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:16:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:16:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:16:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:16:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:16:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:16:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:16:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:16:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:16:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:16:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:16:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:16:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:16:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:16:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:16:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:16:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:16:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:16:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:16:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:16:06 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:16:06 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:16:06 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:16:06 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:16:06 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:16:06 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:16:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:16:11 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:16:11 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:16:11 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:16:11 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:16:11 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:16:11 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:16:11 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:16:11 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:16:11 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:16:11 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:16:11 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:16:11 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:16:11 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:16:11 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:16:11 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:16:11 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:16:11 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:16:11 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:16:11 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:16:11 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:16:11 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:16:11 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:16:11 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:16:11 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:16:11 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:16:11 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:16:11 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:16:11 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:16:11 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:16:11 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:16:11 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:16:11 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:16:11 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:16:11 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:16:11 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:16:11 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:16:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:16:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:16:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:16:11 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:16:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:16:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:16:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:16:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:16:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:16:11 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:16:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:16:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:16:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:16:11 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:16:11 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:16:11 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:16:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:16:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:16:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:16:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:16:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:16:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:16:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:16:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:16:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:16:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:16:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:16:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:16:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:16:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:16:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:16:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:16:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:16:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:16:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:16:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:16:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:16:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:16:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:16:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:16:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:16:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:16:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:16:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:16:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:16:11 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:16:12 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:16:12 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:16:12 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:16:12 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:16:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:16:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:16:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:16:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:16:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:16:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:16:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:16:12 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:16:12 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:16:12 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:16:12 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:16:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:16:12 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:16:12 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:16:13 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:16:13 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:16:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:16:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:16:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:16:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:16:14 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 04:16:14 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 04:16:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:16:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:16:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:16:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:16:15 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 04:16:15 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 04:16:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:16:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:16:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:16:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:16:16 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 04:16:16 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 04:16:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:16:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:16:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:16:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:16:17 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 04:16:17 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 04:16:18 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 04:16:18 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 04:16:19 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 04:16:19 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 04:16:19 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 04:16:20 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 04:16:20 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 04:16:21 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 04:16:21 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 04:16:22 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 04:16:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:16:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:16:22 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:16:22 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:16:22 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:16:22 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:16:22 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:16:22 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:16:22 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:16:22 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:16:22 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:16:22 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:16:22 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:16:22 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2270 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:16:22 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2270 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:16:22 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2270 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:16:22 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2270 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:16:22 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2270 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:16:22 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2270 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:16:27 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:16:27 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:16:27 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:16:27 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:16:27 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:16:27 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:16:27 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:16:27 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:16:27 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:16:27 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:16:27 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:16:27 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:16:27 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:16:27 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:16:27 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:16:27 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:16:27 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:16:27 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:16:27 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:16:27 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:16:27 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:16:27 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:16:27 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:16:27 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:16:27 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:16:27 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:16:27 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:16:27 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:16:27 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:16:27 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:16:27 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:16:27 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:16:27 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:16:27 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:16:27 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:16:27 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:16:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:16:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:16:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:16:27 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:16:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:16:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:16:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:16:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:16:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:16:27 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:16:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:16:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:16:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:16:27 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:16:27 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:16:27 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:16:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:16:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:16:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:16:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:16:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:16:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:16:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:16:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:16:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:16:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:16:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:16:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:16:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:16:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:16:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:16:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:16:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:16:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:16:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:16:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:16:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:16:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:16:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:16:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:16:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:16:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:16:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:16:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:16:27 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:16:27 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:16:27 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:16:27 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:16:27 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:16:27 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:16:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:16:32 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:16:32 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:16:32 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:16:32 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:16:32 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:16:32 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:16:32 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:16:32 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:16:32 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:16:32 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:16:32 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:16:32 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:16:32 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:16:32 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:16:32 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:16:32 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:16:32 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:16:32 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:16:32 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:16:32 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:16:32 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:16:32 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:16:32 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:16:32 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:16:32 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:16:32 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:16:32 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:16:32 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:16:32 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:16:32 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:16:32 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:16:32 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:16:32 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:16:32 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:16:32 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:16:32 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:16:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:16:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:16:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:16:32 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:16:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:16:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:16:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:16:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:16:32 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:16:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:16:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:16:32 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:16:32 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:16:32 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:16:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:16:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:16:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:16:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:16:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:16:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:16:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:16:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:16:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:16:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:16:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:16:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:16:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:16:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:16:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:16:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:16:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:16:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:16:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:16:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:16:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:16:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:16:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:16:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:16:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:16:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:16:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:16:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:16:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:16:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:16:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:16:32 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:16:32 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:16:33 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:16:33 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:16:33 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:16:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:16:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:16:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:16:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:16:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:16:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:16:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:16:33 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:16:33 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:16:33 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:16:33 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:16:33 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:16:33 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:16:33 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:16:33 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:16:34 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:16:34 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:16:34 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:16:34 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:16:34 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:16:34 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 04:16:35 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 04:16:35 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:16:35 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:16:35 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:16:35 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:16:35 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 04:16:36 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 04:16:36 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:16:36 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:16:36 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:16:36 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:16:36 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 04:16:37 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 04:16:37 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:16:37 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:16:37 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:16:37 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:16:37 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 04:16:38 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 04:16:38 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 04:16:39 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 04:16:39 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 04:16:40 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 04:16:40 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 04:16:41 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 04:16:41 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 04:16:41 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 04:16:42 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 04:16:42 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 04:16:43 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-27 04:16:43 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-27 04:16:44 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:16:44 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:16:44 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:16:44 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:16:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:16:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:16:44 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:16:44 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:16:44 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:16:44 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:16:44 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:16:44 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:16:44 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:16:44 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2489 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:16:44 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2489 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:16:44 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2489 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:16:44 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2489 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:16:44 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2489 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:16:44 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2489 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:16:44 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2490 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:16:44 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2490 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:16:44 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2490 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:16:44 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2490 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:16:44 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2490 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:16:44 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2490 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:16:44 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2490 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:16:44 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2490 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:16:49 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:16:49 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:16:49 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:16:49 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:16:49 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:16:49 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:16:49 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:16:49 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:16:49 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:16:49 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:16:49 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:16:49 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:16:49 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:16:49 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:16:49 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:16:49 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:16:49 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:16:49 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:16:49 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:16:49 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:16:49 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:16:49 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:16:49 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:16:49 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:16:49 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:16:49 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:16:49 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:16:49 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:16:49 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:16:49 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:16:49 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:16:49 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:16:49 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:16:49 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:16:49 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:16:49 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:16:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:16:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:16:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:16:49 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:16:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:16:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:16:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:16:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:16:49 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:16:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:16:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:16:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:16:49 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:16:49 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:16:49 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:16:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:16:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:16:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:16:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:16:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:16:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:16:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:16:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:16:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:16:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:16:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:16:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:16:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:16:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:16:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:16:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:16:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:16:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:16:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:16:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:16:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:16:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:16:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:16:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:16:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:16:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:16:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:16:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:16:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:16:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:16:49 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:16:49 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:16:49 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:16:49 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:16:49 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:16:49 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:16:49 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:16:49 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:16:54 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:16:54 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:16:54 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:16:54 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:16:54 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:16:54 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:16:54 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:16:54 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:16:54 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:16:54 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:16:54 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:16:54 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:16:54 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:16:54 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:16:54 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:16:54 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:16:54 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:16:54 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:16:54 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:16:54 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:16:54 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:16:54 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:16:54 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:16:54 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:16:54 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:16:54 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:16:54 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:16:54 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:16:54 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:16:54 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:16:54 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:16:54 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:16:54 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:16:54 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:16:54 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:16:54 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:16:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:16:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:16:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:16:54 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:16:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:16:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:16:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:16:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:16:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:16:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:16:54 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:16:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:16:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:16:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:16:54 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:16:54 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:16:54 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:16:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:16:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:16:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:16:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:16:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:16:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:16:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:16:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:16:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:16:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:16:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:16:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:16:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:16:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:16:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:16:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:16:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:16:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:16:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:16:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:16:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:16:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:16:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:16:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:16:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:16:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:16:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:16:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:16:54 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:16:54 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:16:54 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:16:54 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:16:54 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:16:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:16:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:16:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:16:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:16:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:16:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:16:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:16:54 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:16:54 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:16:55 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:16:55 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:16:55 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:16:55 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:16:55 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:16:55 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:16:56 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:16:56 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:16:56 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:16:56 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:16:56 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:16:56 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 04:16:56 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 04:16:57 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:16:57 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:16:57 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:16:57 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:16:57 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 04:16:57 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 04:16:58 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:16:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:16:58 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:16:58 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:16:58 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 04:16:58 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 04:16:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:16:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:16:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:16:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:16:59 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 04:16:59 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 04:17:00 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 04:17:00 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 04:17:01 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 04:17:01 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 04:17:02 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 04:17:02 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 04:17:03 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 04:17:03 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 04:17:04 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 04:17:04 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 04:17:05 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-27 04:17:05 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-27 04:17:06 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-27 04:17:06 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-27 04:17:06 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-27 04:17:07 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-27 04:17:07 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-27 04:17:08 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-27 04:17:08 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-27 04:17:09 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-27 04:17:09 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-27 04:17:10 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-27 04:17:10 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-27 04:17:11 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-27 04:17:11 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-27 04:17:12 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-27 04:17:12 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2025-04-27 04:17:13 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2025-04-27 04:17:13 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2025-04-27 04:17:14 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2025-04-27 04:17:14 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2025-04-27 04:17:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:17:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:17:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:17:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:17:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:17:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:17:14 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:17:14 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:17:14 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:17:14 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:17:14 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:17:14 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:17:14 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4417 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:17:14 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:17:14 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4417 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:17:14 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4418 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:17:14 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4418 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:17:14 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4418 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:17:14 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4418 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:17:14 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4418 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:17:14 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4418 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:17:14 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4418 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:17:14 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4418 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:17:19 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:17:19 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:17:19 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:17:19 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:17:19 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:17:19 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:17:19 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:17:19 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:17:19 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:17:19 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:17:19 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:17:19 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:17:19 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:17:19 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:17:19 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:17:19 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:17:19 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:17:19 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:17:19 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:17:19 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:17:19 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:17:19 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:17:19 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:17:19 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:17:19 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:17:19 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:17:19 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:17:19 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:17:19 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:17:19 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:17:19 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:17:19 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:17:19 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:17:19 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:17:19 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:17:19 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:17:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:17:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:17:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:17:19 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:17:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:17:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:17:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:17:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:17:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:17:19 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:17:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:17:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:17:19 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:17:19 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:17:19 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:17:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:17:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:17:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:17:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:17:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:17:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:17:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:17:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:17:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:17:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:17:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:17:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:17:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:17:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:17:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:17:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:17:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:17:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:17:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:17:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:17:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:17:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:17:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:17:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:17:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:17:19 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:17:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:17:19 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:17:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:17:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:17:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:17:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:17:19 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:17:19 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:17:19 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:17:19 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:17:19 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:17:24 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:17:24 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:17:24 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:17:24 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:17:24 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:17:24 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:17:24 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:17:24 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:17:24 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:17:24 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:17:24 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:17:24 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:17:24 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:17:24 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:17:24 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:17:24 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:17:24 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:17:24 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:17:24 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:17:24 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:17:24 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:17:24 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:17:24 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:17:24 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:17:24 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:17:24 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:17:24 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:17:24 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:17:24 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:17:24 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:17:24 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:17:24 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:17:24 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:17:24 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:17:24 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:17:24 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:17:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:17:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:17:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:17:24 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:17:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:17:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:17:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:17:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:17:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:17:24 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:17:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:17:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:17:24 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:17:24 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:17:24 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:17:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:17:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:17:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:17:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:17:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:17:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:17:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:17:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:17:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:17:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:17:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:17:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:17:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:17:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:17:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:17:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:17:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:17:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:17:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:17:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:17:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:17:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:17:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:17:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:17:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:17:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:17:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:17:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:17:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:17:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:17:24 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:17:25 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:17:25 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:17:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:17:25 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:17:25 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:17:25 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:17:25 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:17:25 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:17:25 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:17:25 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:17:26 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:17:26 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:17:26 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:17:26 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:17:26 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:17:26 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:17:27 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 04:17:27 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 04:17:27 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:17:27 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:17:27 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:17:27 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:17:28 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 04:17:28 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 04:17:28 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:17:28 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:17:28 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:17:28 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:17:28 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 04:17:29 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 04:17:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:17:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:17:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:17:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:17:29 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 04:17:30 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 04:17:30 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 04:17:31 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 04:17:31 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 04:17:32 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 04:17:32 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 04:17:33 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 04:17:33 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 04:17:34 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 04:17:34 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 04:17:35 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 04:17:35 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:17:35 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:17:35 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:17:35 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:17:35 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:17:35 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:17:35 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:17:35 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:17:35 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:17:35 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:17:35 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:17:40 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:17:40 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:17:40 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:17:40 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:17:40 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:17:40 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:17:40 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:17:40 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:17:40 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:17:40 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:17:40 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:17:40 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:17:40 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:17:40 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:17:40 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:17:40 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:17:40 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:17:40 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:17:40 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:17:40 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:17:40 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:17:40 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:17:40 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:17:40 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:17:40 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:17:40 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:17:40 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:17:40 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:17:40 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:17:40 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:17:40 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:17:40 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:17:40 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:17:40 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:17:40 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:17:40 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:17:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:17:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:17:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:17:40 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:17:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:17:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:17:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:17:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:17:40 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:17:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:17:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:17:40 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:17:40 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:17:40 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:17:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:17:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:17:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:17:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:17:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:17:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:17:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:17:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:17:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:17:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:17:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:17:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:17:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:17:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:17:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:17:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:17:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:17:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:17:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:17:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:17:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:17:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:17:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:17:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:17:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:17:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:17:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:17:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:17:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:17:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:17:40 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:17:40 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:17:40 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:17:40 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:17:40 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:17:40 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:17:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:17:45 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:17:45 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:17:45 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:17:45 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:17:45 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:17:45 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:17:45 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:17:45 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:17:45 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:17:45 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:17:45 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:17:45 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:17:45 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:17:45 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:17:45 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:17:45 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:17:45 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:17:45 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:17:45 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:17:45 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:17:45 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:17:45 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:17:45 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:17:45 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:17:45 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:17:45 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:17:45 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:17:45 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:17:45 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:17:45 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:17:45 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:17:45 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:17:45 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:17:45 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:17:45 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:17:45 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:17:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:17:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:17:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:17:45 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:17:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:17:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:17:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:17:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:17:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:17:45 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:17:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:17:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:17:45 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:17:45 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:17:45 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:17:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:17:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:17:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:17:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:17:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:17:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:17:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:17:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:17:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:17:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:17:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:17:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:17:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:17:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:17:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:17:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:17:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:17:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:17:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:17:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:17:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:17:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:17:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:17:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:17:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:17:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:17:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:17:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:17:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:17:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:17:45 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:17:45 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:17:45 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:17:45 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:17:45 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:17:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:17:46 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:17:46 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:17:46 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:17:46 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:17:46 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:17:46 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:17:47 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:17:47 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:17:47 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:17:47 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:17:47 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:17:47 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 04:17:48 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 04:17:48 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:17:48 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:17:48 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:17:48 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:17:48 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 04:17:49 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 04:17:49 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:17:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:17:49 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:17:49 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:17:49 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 04:17:50 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 04:17:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:17:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:17:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:17:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:17:50 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 04:17:50 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 04:17:51 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 04:17:51 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 04:17:52 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 04:17:52 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 04:17:53 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 04:17:53 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 04:17:54 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 04:17:54 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 04:17:55 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 04:17:55 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 04:17:56 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-27 04:17:56 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-27 04:17:57 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-27 04:17:57 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-27 04:17:57 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:17:57 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:17:57 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:17:57 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:17:57 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:17:57 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:17:57 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:17:57 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:17:57 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:17:57 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:17:57 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:18:02 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:18:02 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:18:02 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:18:02 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:18:02 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:18:02 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:18:02 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:18:02 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:18:02 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:18:02 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:18:02 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:18:02 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:18:02 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:18:02 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:18:02 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:18:02 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:18:02 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:18:02 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:18:02 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:18:02 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:18:02 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:18:02 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:18:02 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:18:02 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:18:02 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:18:02 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:18:02 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:18:02 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:18:02 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:18:02 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:18:02 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:18:02 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:18:02 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:18:02 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:18:02 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:18:02 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:18:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:18:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:18:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:18:02 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:18:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:18:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:18:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:18:02 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:18:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:18:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:18:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:18:02 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:18:02 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:18:02 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:18:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:18:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:18:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:18:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:18:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:18:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:18:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:18:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:18:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:18:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:18:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:18:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:18:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:18:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:18:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:18:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:18:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:18:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:18:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:18:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:18:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:18:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:18:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:18:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:18:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:18:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:18:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:18:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:18:02 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:18:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:18:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:18:02 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:18:02 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:18:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:18:02 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:18:02 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:18:02 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:18:02 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:18:07 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:18:07 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:18:07 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:18:07 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:18:07 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:18:07 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:18:07 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:18:07 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:18:07 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:18:07 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:18:07 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:18:07 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:18:07 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:18:07 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:18:07 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:18:07 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:18:07 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:18:07 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:18:07 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:18:07 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:18:07 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:18:07 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:18:07 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:18:07 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:18:07 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:18:07 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:18:07 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:18:07 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:18:07 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:18:07 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:18:07 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:18:07 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:18:07 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:18:07 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:18:07 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:18:07 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:18:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:18:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:18:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:18:07 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:18:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:18:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:18:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:18:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:18:07 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:18:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:18:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:18:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:18:07 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:18:07 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:18:07 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:18:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:18:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:18:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:18:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:18:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:18:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:18:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:18:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:18:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:18:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:18:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:18:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:18:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:18:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:18:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:18:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:18:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:18:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:18:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:18:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:18:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:18:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:18:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:18:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:18:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:18:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:18:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:18:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:18:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:18:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:18:07 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:18:08 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:18:08 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:18:08 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:18:08 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:18:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:18:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:18:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:18:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:18:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:18:08 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:18:08 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:18:08 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:18:08 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:18:08 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:18:08 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:18:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:18:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:18:08 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:18:08 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:18:08 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:18:08 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:18:08 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:18:09 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:18:09 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:18:09 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:18:09 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:18:09 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:18:09 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:18:10 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 04:18:10 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 04:18:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:18:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:18:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:18:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:18:11 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 04:18:11 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 04:18:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:18:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:18:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:18:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:18:12 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 04:18:12 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 04:18:12 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:18:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:18:12 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:18:12 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:18:13 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 04:18:13 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 04:18:13 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 04:18:14 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 04:18:14 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 04:18:15 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 04:18:15 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 04:18:16 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 04:18:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:18:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:18:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:18:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:18:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:18:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:18:16 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:18:16 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:18:16 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:18:16 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:18:16 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:18:16 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:18:16 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:18:21 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:18:21 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:18:21 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:18:21 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:18:21 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:18:21 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:18:21 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:18:21 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:18:21 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:18:21 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:18:21 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:18:21 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:18:21 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:18:21 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:18:21 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:18:21 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:18:21 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:18:21 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:18:21 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:18:21 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:18:21 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:18:21 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:18:21 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:18:21 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:18:21 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:18:21 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:18:21 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:18:21 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:18:21 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:18:21 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:18:21 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:18:21 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:18:21 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:18:21 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:18:21 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:18:21 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:18:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:18:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:18:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:18:21 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:18:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:18:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:18:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:18:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:18:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:18:21 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:18:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:18:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:18:21 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:18:21 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:18:21 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:18:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:18:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:18:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:18:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:18:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:18:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:18:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:18:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:18:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:18:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:18:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:18:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:18:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:18:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:18:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:18:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:18:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:18:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:18:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:18:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:18:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:18:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:18:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:18:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:18:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:18:21 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:18:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:18:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:18:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:18:21 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:18:21 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:18:21 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:18:21 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:18:21 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:18:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:18:26 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:18:26 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:18:26 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:18:26 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:18:26 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:18:26 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:18:26 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:18:26 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:18:26 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:18:26 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:18:26 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:18:26 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:18:26 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:18:26 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:18:26 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:18:26 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:18:26 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:18:26 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:18:26 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:18:26 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:18:26 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:18:26 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:18:26 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:18:26 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:18:26 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:18:26 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:18:26 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:18:26 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:18:26 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:18:26 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:18:26 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:18:26 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:18:26 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:18:26 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:18:26 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:18:26 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:18:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:18:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:18:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:18:26 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:18:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:18:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:18:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:18:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:18:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:18:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:18:26 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:18:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:18:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:18:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:18:26 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:18:26 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:18:26 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:18:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:18:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:18:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:18:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:18:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:18:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:18:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:18:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:18:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:18:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:18:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:18:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:18:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:18:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:18:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:18:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:18:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:18:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:18:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:18:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:18:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:18:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:18:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:18:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:18:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:18:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:18:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:18:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:18:26 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:18:26 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:18:26 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:18:26 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:18:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:18:26 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:18:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:18:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:18:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:18:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:18:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:18:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:18:26 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:18:26 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:18:27 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:18:27 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:18:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:18:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:18:27 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:18:27 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:18:27 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:18:27 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:18:27 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:18:27 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:18:28 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:18:28 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:18:28 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:18:28 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:18:28 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:18:28 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 04:18:29 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 04:18:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:18:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:18:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:18:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:18:29 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 04:18:30 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 04:18:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:18:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:18:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:18:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:18:30 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 04:18:31 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 04:18:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:18:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:18:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:18:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:18:31 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 04:18:32 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 04:18:32 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 04:18:33 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 04:18:33 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 04:18:34 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 04:18:34 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 04:18:35 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 04:18:35 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:18:35 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:18:35 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:18:35 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:18:35 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:18:35 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:18:35 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:18:35 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:18:35 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:18:35 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:18:35 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1841 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:18:35 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1841 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:18:35 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1841 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:18:35 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1841 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:18:35 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1841 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:18:35 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1841 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:18:35 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1841 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:18:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:18:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:18:35 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:18:40 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:18:40 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:18:40 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:18:40 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:18:40 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:18:40 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:18:40 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:18:40 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:18:40 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:18:40 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:18:40 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:18:40 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:18:40 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:18:40 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:18:40 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:18:40 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:18:40 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:18:40 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:18:40 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:18:40 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:18:40 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:18:40 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:18:40 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:18:40 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:18:40 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:18:40 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:18:40 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:18:40 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:18:40 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:18:40 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:18:40 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:18:40 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:18:40 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:18:40 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:18:40 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:18:40 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:18:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:18:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:18:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:18:40 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:18:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:18:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:18:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:18:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:18:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:18:40 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:18:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:18:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:18:40 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:18:40 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:18:40 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:18:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:18:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:18:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:18:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:18:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:18:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:18:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:18:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:18:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:18:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:18:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:18:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:18:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:18:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:18:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:18:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:18:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:18:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:18:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:18:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:18:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:18:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:18:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:18:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:18:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:18:40 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:18:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:18:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:18:40 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:18:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:18:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:18:40 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:18:40 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:18:40 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:18:40 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:18:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:18:45 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:18:45 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:18:45 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:18:45 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:18:45 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:18:45 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:18:45 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:18:45 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:18:45 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:18:45 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:18:45 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:18:45 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:18:45 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:18:45 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:18:45 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:18:45 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:18:45 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:18:45 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:18:45 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:18:45 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:18:45 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:18:45 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:18:45 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:18:45 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:18:45 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:18:45 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:18:45 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:18:45 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:18:45 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:18:45 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:18:45 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:18:45 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:18:45 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:18:45 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:18:45 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:18:45 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:18:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:18:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:18:45 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:18:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:18:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:18:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:18:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:18:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:18:45 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:18:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:18:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:18:45 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:18:45 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:18:45 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:18:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:18:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:18:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:18:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:18:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:18:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:18:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:18:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:18:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:18:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:18:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:18:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:18:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:18:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:18:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:18:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:18:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:18:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:18:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:18:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:18:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:18:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:18:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:18:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:18:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:18:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:18:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:18:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:18:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:18:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:18:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:18:45 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:18:45 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:18:45 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:18:45 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:18:45 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:18:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:18:45 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:18:45 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:18:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:18:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:18:45 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:18:45 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:18:45 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:18:45 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:18:45 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:18:45 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:18:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:18:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:18:46 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:18:46 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:18:46 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:18:46 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:18:46 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:18:46 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:18:47 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:18:47 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:18:47 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:18:47 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:18:47 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:18:47 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 04:18:48 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 04:18:48 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:18:48 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:18:48 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:18:48 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:18:48 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 04:18:48 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 04:18:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:18:49 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:18:49 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:18:49 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:18:49 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 04:18:49 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 04:18:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:18:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:18:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:18:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:18:50 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 04:18:50 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 04:18:51 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 04:18:51 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 04:18:52 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 04:18:52 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 04:18:53 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 04:18:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:18:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:18:53 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:18:53 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:18:53 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:18:53 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:18:53 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:18:53 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:18:53 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:18:53 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:18:53 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:18:53 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:18:53 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:18:53 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1825 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:18:53 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1825 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:18:53 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1825 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:18:53 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1825 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:18:53 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1825 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:18:58 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:18:58 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:18:58 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:18:58 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:18:58 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:18:58 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:18:58 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:18:58 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:18:58 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:18:58 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:18:58 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:18:58 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:18:58 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:18:58 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:18:58 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:18:58 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:18:58 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:18:58 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:18:58 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:18:58 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:18:58 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:18:58 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:18:58 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:18:58 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:18:58 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:18:58 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:18:58 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:18:58 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:18:58 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:18:58 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:18:58 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:18:58 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:18:58 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:18:58 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:18:58 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:18:58 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:18:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:18:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:18:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:18:58 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:18:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:18:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:18:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:18:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:18:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:18:58 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:18:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:18:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:18:58 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:18:58 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:18:58 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:18:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:18:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:18:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:18:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:18:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:18:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:18:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:18:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:18:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:18:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:18:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:18:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:18:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:18:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:18:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:18:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:18:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:18:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:18:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:18:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:18:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:18:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:18:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:18:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:18:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:18:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:18:58 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:18:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:18:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:18:58 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:18:58 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:18:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:18:58 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:18:58 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:18:58 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:18:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:19:03 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:19:03 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:19:03 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:19:03 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:19:03 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:19:03 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:19:03 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:19:03 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:19:03 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:19:03 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:19:03 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:19:03 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:19:03 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:19:03 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:19:03 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:19:03 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:19:03 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:19:03 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:19:03 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:19:03 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:19:03 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:19:03 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:19:03 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:19:03 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:19:03 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:19:03 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:19:03 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:19:03 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:19:03 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:19:03 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:19:03 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:19:03 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:19:03 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:19:03 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:19:03 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:19:03 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:19:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:19:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:19:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:19:03 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:19:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:19:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:19:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:19:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:19:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:19:03 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:19:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:19:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:19:03 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:19:03 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:19:03 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:19:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:19:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:19:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:19:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:19:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:19:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:19:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:19:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:19:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:19:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:19:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:19:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:19:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:19:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:19:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:19:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:19:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:19:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:19:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:19:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:19:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:19:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:19:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:19:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:19:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:19:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:19:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:19:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:19:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:19:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:19:03 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:19:04 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:19:04 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:19:04 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:19:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:19:04 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:19:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:19:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:19:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:19:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:19:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:19:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:19:04 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:19:04 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:19:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:19:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:19:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:19:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:19:04 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:19:04 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:19:04 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:19:04 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:19:04 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:19:05 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:19:05 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:19:05 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:19:05 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:19:05 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:19:05 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:19:06 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 04:19:06 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 04:19:06 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:19:06 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:19:06 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:19:06 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:19:07 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 04:19:07 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 04:19:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:19:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:19:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:19:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:19:08 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 04:19:08 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 04:19:08 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:19:08 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:19:08 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:19:08 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:19:09 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 04:19:09 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 04:19:09 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 04:19:10 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 04:19:10 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 04:19:11 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 04:19:11 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 04:19:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:19:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:19:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:19:12 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:19:12 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:19:12 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:19:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:19:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:19:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:19:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:19:12 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:19:12 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:19:12 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:19:12 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1836 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:19:12 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1836 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:19:12 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1836 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:19:12 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1836 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:19:12 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1836 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:19:12 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1836 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:19:17 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:19:17 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:19:17 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:19:17 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:19:17 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:19:17 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:19:17 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:19:17 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:19:17 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:19:17 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:19:17 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:19:17 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:19:17 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:19:17 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:19:17 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:19:17 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:19:17 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:19:17 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:19:17 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:19:17 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:19:17 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:19:17 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:19:17 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:19:17 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:19:17 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:19:17 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:19:17 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:19:17 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:19:17 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:19:17 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:19:17 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:19:17 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:19:17 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:19:17 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:19:17 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:19:17 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:19:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:19:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:19:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:19:17 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:19:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:19:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:19:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:19:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:19:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:19:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:19:17 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:19:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:19:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:19:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:19:17 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:19:17 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:19:17 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:19:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:19:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:19:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:19:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:19:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:19:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:19:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:19:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:19:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:19:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:19:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:19:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:19:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:19:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:19:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:19:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:19:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:19:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:19:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:19:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:19:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:19:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:19:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:19:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:19:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:19:17 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:19:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:19:17 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:19:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:19:17 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:19:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:19:17 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:19:17 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:19:17 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:19:17 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:19:22 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:19:22 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:19:22 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:19:22 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:19:22 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:19:22 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:19:22 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:19:22 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:19:22 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:19:22 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:19:22 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:19:22 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:19:22 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:19:22 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:19:22 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:19:22 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:19:22 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:19:22 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:19:22 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:19:22 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:19:22 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:19:22 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:19:22 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:19:22 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:19:22 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:19:22 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:19:22 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:19:22 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:19:22 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:19:22 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:19:22 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:19:22 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:19:22 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:19:22 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:19:22 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:19:22 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:19:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:19:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:19:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:19:22 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:19:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:19:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:19:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:19:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:19:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:19:22 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:19:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:19:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:19:22 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:19:22 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:19:22 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:19:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:19:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:19:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:19:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:19:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:19:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:19:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:19:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:19:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:19:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:19:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:19:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:19:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:19:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:19:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:19:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:19:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:19:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:19:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:19:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:19:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:19:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:19:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:19:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:19:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:19:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:19:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:19:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:19:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:19:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:19:22 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:19:22 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:19:22 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:19:22 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:19:22 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:19:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:19:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:19:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:19:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:19:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:19:22 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:19:22 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:19:22 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:19:22 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:19:22 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:19:22 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:19:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:19:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:19:23 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:19:23 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:19:23 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:19:23 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:19:23 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:19:23 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:19:24 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:19:24 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:19:24 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:19:24 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:19:24 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:19:24 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 04:19:25 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 04:19:25 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:19:25 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:19:25 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:19:25 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:19:25 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 04:19:26 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 04:19:26 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:19:26 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:19:26 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:19:26 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:19:26 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 04:19:27 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 04:19:27 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:19:27 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:19:27 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:19:27 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:19:27 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 04:19:28 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 04:19:28 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 04:19:29 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 04:19:29 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 04:19:30 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 04:19:30 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 04:19:30 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 04:19:31 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 04:19:31 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 04:19:32 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 04:19:32 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 04:19:33 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-27 04:19:33 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-27 04:19:34 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-27 04:19:34 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-27 04:19:35 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-27 04:19:35 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-27 04:19:36 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-27 04:19:36 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-27 04:19:36 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:19:36 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:19:36 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:19:36 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:19:36 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:19:36 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:19:36 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:19:36 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:19:36 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:19:36 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:19:36 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:19:36 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:19:36 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:19:36 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3125 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:19:36 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3125 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:19:36 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3125 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:19:36 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3125 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:19:36 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3125 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:19:36 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3125 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:19:36 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3125 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:19:36 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3126 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:19:36 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3126 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:19:36 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3126 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:19:36 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3126 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:19:36 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3126 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:19:36 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3126 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:19:36 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3126 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:19:36 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3126 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:19:41 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:19:41 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:19:41 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:19:41 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:19:41 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:19:41 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:19:42 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:19:42 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:19:42 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:19:42 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:19:42 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:19:42 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:19:42 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:19:42 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:19:42 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:19:42 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:19:42 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:19:42 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:19:42 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:19:42 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:19:42 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:19:42 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:19:42 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:19:42 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:19:42 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:19:42 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:19:42 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:19:42 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:19:42 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:19:42 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:19:42 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:19:42 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:19:42 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:19:42 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:19:42 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:19:42 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:19:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:19:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:19:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:19:42 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:19:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:19:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:19:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:19:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:19:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:19:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:19:42 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:19:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:19:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:19:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:19:42 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:19:42 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:19:42 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:19:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:19:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:19:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:19:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:19:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:19:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:19:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:19:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:19:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:19:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:19:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:19:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:19:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:19:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:19:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:19:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:19:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:19:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:19:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:19:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:19:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:19:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:19:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:19:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:19:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:19:42 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:19:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:19:42 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:19:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:19:42 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:19:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:19:42 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:19:42 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:19:42 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:19:42 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:19:47 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:19:47 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:19:47 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:19:47 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:19:47 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:19:47 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:19:47 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:19:47 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:19:47 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:19:47 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:19:47 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:19:47 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:19:47 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:19:47 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:19:47 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:19:47 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:19:47 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:19:47 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:19:47 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:19:47 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:19:47 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:19:47 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:19:47 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:19:47 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:19:47 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:19:47 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:19:47 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:19:47 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:19:47 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:19:47 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:19:47 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:19:47 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:19:47 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:19:47 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:19:47 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:19:47 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:19:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:19:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:19:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:19:47 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:19:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:19:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:19:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:19:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:19:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:19:47 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:19:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:19:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:19:47 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:19:47 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:19:47 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:19:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:19:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:19:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:19:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:19:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:19:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:19:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:19:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:19:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:19:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:19:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:19:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:19:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:19:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:19:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:19:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:19:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:19:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:19:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:19:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:19:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:19:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:19:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:19:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:19:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:19:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:19:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:19:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:19:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:19:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:19:47 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:19:47 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:19:47 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:19:47 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:19:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:19:47 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:19:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:19:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:19:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:19:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:19:47 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:19:47 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:19:47 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:19:47 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:19:47 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:19:47 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:19:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:19:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:19:48 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:19:48 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:19:48 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:19:48 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:19:48 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:19:48 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:19:48 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:19:49 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:19:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:19:49 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:19:49 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:19:49 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 04:19:49 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 04:19:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:19:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:19:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:19:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:19:50 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 04:19:50 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 04:19:51 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:19:51 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:19:51 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:19:51 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:19:51 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 04:19:51 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 04:19:52 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:19:52 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:19:52 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:19:52 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:19:52 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 04:19:52 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 04:19:53 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 04:19:53 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 04:19:54 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 04:19:54 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 04:19:55 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 04:19:55 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:19:55 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:19:55 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:19:55 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:19:55 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:19:55 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:19:55 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:19:55 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:19:55 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:19:55 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:19:55 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:19:55 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:19:55 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:19:55 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1828 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:19:55 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1828 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:19:55 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1828 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:19:55 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1828 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:19:55 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1828 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:19:55 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1828 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:19:55 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1828 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:20:00 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:20:00 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:20:00 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:20:00 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:20:00 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:20:00 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:20:00 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:20:00 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:20:00 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:20:00 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:20:00 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:20:00 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:20:00 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:20:00 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:20:00 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:20:00 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:20:00 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:20:00 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:20:00 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:20:00 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:20:00 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:20:00 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:20:00 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:20:00 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:20:00 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:20:00 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:20:00 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:20:00 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:20:00 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:20:00 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:20:00 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:20:00 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:20:00 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:20:00 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:20:00 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:20:00 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:20:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:20:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:20:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:20:00 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:20:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:20:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:20:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:20:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:20:00 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:20:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:20:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:20:00 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:20:00 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:20:00 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:20:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:20:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:20:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:20:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:20:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:20:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:20:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:20:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:20:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:20:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:20:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:20:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:20:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:20:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:20:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:20:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:20:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:20:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:20:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:20:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:20:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:20:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:20:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:20:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:20:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:20:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:20:00 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:20:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:20:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:20:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:20:00 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:20:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:20:00 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:20:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:20:00 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:20:00 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:20:00 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:20:00 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:20:05 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:20:05 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:20:05 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:20:05 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:20:05 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:20:05 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:20:05 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:20:05 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:20:05 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:20:05 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:20:05 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:20:05 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:20:05 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:20:05 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:20:05 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:20:05 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:20:05 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:20:05 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:20:05 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:20:05 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:20:05 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:20:05 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:20:05 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:20:05 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:20:05 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:20:05 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:20:05 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:20:05 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:20:05 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:20:05 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:20:05 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:20:05 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:20:05 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:20:05 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:20:05 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:20:05 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:20:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:20:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:20:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:20:05 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:20:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:20:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:20:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:20:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:20:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:20:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:20:05 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:20:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:20:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:20:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:20:05 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:20:05 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:20:05 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:20:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:20:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:20:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:20:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:20:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:20:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:20:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:20:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:20:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:20:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:20:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:20:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:20:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:20:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:20:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:20:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:20:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:20:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:20:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:20:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:20:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:20:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:20:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:20:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:20:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:20:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:20:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:20:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:20:05 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:20:06 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:20:06 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:20:06 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:20:06 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:20:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:20:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:20:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:20:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:20:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:20:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:20:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:20:06 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:20:06 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:20:06 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:20:06 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:20:06 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:20:06 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:20:06 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:20:07 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:20:07 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:20:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:20:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:20:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:20:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:20:08 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 04:20:08 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 04:20:08 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:20:08 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:20:08 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:20:08 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:20:09 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 04:20:09 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 04:20:09 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:20:09 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:20:09 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:20:09 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:20:09 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 04:20:10 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 04:20:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:20:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:20:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:20:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:20:10 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 04:20:11 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 04:20:11 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 04:20:12 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 04:20:12 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 04:20:13 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 04:20:13 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 04:20:14 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 04:20:14 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 04:20:15 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 04:20:15 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 04:20:16 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 04:20:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:20:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:20:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:20:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:20:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:20:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:20:16 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:20:16 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:20:16 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:20:16 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:20:16 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2256 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:20:16 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:20:16 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:20:16 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:20:16 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2256 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:20:16 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2256 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:20:16 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2256 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:20:16 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2256 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:20:16 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2256 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:20:21 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:20:21 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:20:21 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:20:21 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:20:21 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:20:21 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:20:21 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:20:21 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:20:21 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:20:21 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:20:21 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:20:21 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:20:21 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:20:21 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:20:21 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:20:21 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:20:21 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:20:21 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:20:21 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:20:21 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:20:21 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:20:21 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:20:21 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:20:21 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:20:21 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:20:21 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:20:21 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:20:21 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:20:21 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:20:21 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:20:21 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:20:21 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:20:21 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:20:21 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:20:21 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:20:21 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:20:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:20:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:20:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:20:21 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:20:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:20:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:20:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:20:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:20:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:20:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:20:21 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:20:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:20:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:20:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:20:21 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:20:21 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:20:21 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:20:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:20:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:20:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:20:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:20:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:20:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:20:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:20:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:20:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:20:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:20:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:20:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:20:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:20:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:20:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:20:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:20:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:20:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:20:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:20:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:20:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:20:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:20:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:20:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:20:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:20:21 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:20:21 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:20:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:20:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:20:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:20:21 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:20:21 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:20:21 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:20:21 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:20:21 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:20:26 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:20:26 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:20:26 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:20:26 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:20:26 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:20:26 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:20:26 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:20:26 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:20:26 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:20:26 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:20:26 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:20:26 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:20:26 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:20:26 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:20:26 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:20:26 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:20:26 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:20:26 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:20:26 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:20:26 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:20:26 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:20:26 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:20:26 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:20:26 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:20:26 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:20:26 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:20:26 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:20:26 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:20:26 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:20:26 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:20:26 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:20:26 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:20:26 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:20:26 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:20:26 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:20:26 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:20:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:20:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:20:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:20:26 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:20:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:20:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:20:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:20:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:20:26 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:20:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:20:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:20:26 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:20:26 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:20:26 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:20:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:20:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:20:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:20:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:20:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:20:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:20:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:20:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:20:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:20:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:20:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:20:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:20:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:20:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:20:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:20:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:20:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:20:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:20:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:20:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:20:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:20:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:20:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:20:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:20:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:20:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:20:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:20:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:20:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:20:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:20:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:20:26 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:20:26 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:20:26 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:20:26 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:20:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:20:26 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:20:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:20:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:20:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:20:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:20:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:20:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:20:26 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:20:26 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:20:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:20:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:20:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:20:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:20:27 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:20:27 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:20:27 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:20:27 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:20:27 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:20:27 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:20:28 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:20:28 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:20:28 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:20:28 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:20:28 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:20:28 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 04:20:29 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 04:20:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:20:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:20:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:20:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:20:29 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 04:20:30 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 04:20:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:20:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:20:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:20:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:20:30 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 04:20:31 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 04:20:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:20:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:20:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:20:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:20:31 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 04:20:32 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 04:20:32 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 04:20:32 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 04:20:33 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 04:20:33 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 04:20:34 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 04:20:34 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 04:20:35 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 04:20:35 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 04:20:36 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 04:20:36 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 04:20:37 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-27 04:20:37 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-27 04:20:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:20:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:20:37 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:20:37 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:20:37 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:20:37 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:20:37 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:20:37 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:20:37 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:20:37 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:20:37 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2479 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:20:37 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:20:37 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:20:37 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:20:37 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2479 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:20:37 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2480 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:20:37 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2480 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:20:37 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2480 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:20:37 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2480 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:20:37 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2480 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:20:37 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2480 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:20:37 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2480 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:20:37 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2480 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:20:42 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:20:42 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:20:42 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:20:42 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:20:42 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:20:42 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:20:42 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:20:42 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:20:42 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:20:42 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:20:42 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:20:42 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:20:42 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:20:42 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:20:42 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:20:42 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:20:42 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:20:42 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:20:42 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:20:42 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:20:42 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:20:42 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:20:42 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:20:42 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:20:42 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:20:42 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:20:42 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:20:42 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:20:42 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:20:42 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:20:42 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:20:42 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:20:42 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:20:42 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:20:42 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:20:42 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:20:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:20:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:20:42 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:20:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:20:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:20:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:20:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:20:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:20:42 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:20:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:20:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:20:42 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:20:42 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:20:42 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:20:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:20:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:20:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:20:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:20:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:20:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:20:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:20:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:20:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:20:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:20:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:20:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:20:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:20:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:20:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:20:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:20:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:20:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:20:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:20:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:20:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:20:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:20:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:20:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:20:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:20:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:20:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:20:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:20:42 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:20:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:20:42 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:20:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:20:42 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:20:42 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:20:42 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:20:42 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:20:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:20:47 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:20:47 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:20:47 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:20:47 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:20:47 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:20:47 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:20:47 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:20:47 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:20:47 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:20:47 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:20:47 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:20:47 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:20:47 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:20:47 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:20:47 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:20:47 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:20:47 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:20:47 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:20:47 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:20:47 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:20:47 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:20:47 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:20:47 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:20:47 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:20:47 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:20:47 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:20:47 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:20:47 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:20:47 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:20:47 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:20:47 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:20:47 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:20:47 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:20:47 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:20:47 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:20:47 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:20:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:20:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:20:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:20:47 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:20:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:20:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:20:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:20:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:20:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:20:47 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:20:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:20:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:20:47 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:20:47 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:20:47 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:20:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:20:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:20:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:20:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:20:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:20:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:20:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:20:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:20:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:20:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:20:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:20:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:20:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:20:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:20:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:20:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:20:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:20:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:20:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:20:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:20:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:20:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:20:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:20:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:20:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:20:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:20:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:20:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:20:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:20:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:20:47 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:20:48 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:20:48 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:20:48 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:20:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:20:48 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:20:48 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:20:48 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:20:48 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:20:48 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:20:48 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:20:49 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:20:49 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:20:49 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:20:49 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:20:49 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:20:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:20:50 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 04:20:50 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 04:20:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:20:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:20:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:20:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:20:51 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 04:20:51 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 04:20:51 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:20:51 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:20:51 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:20:51 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:20:52 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 04:20:52 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 04:20:52 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:20:52 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:20:52 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:20:52 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:20:53 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 04:20:53 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 04:20:54 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 04:20:54 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 04:20:55 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 04:20:55 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 04:20:56 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 04:20:56 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 04:20:57 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 04:20:57 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 04:20:57 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 04:20:58 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 04:20:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:20:58 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:20:58 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:20:58 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:20:58 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:20:58 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:20:58 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:20:58 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:20:58 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:20:58 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:20:58 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:20:58 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2251 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:20:58 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2251 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:20:58 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2251 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:20:58 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2251 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:20:58 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2251 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:20:58 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2251 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:21:03 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:21:03 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:21:03 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:21:03 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:21:03 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:21:03 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:21:03 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:21:03 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:21:03 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:21:03 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:21:03 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:21:03 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:21:03 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:21:03 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:21:03 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:21:03 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:21:03 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:21:03 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:21:03 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:21:03 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:21:03 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:21:03 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:21:03 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:21:03 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:21:03 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:21:03 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:21:03 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:21:03 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:21:03 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:21:03 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:21:03 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:21:03 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:21:03 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:21:03 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:21:03 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:21:03 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:21:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:21:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:21:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:21:03 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:21:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:21:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:21:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:21:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:21:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:21:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:21:03 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:21:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:21:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:21:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:21:03 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:21:03 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:21:03 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:21:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:21:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:21:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:21:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:21:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:21:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:21:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:21:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:21:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:21:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:21:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:21:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:21:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:21:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:21:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:21:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:21:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:21:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:21:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:21:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:21:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:21:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:21:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:21:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:21:03 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:21:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:21:03 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:21:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:21:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:21:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:21:03 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:21:03 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:21:03 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:21:03 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:21:03 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:21:08 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:21:08 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:21:08 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:21:08 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:21:08 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:21:08 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:21:08 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:21:08 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:21:08 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:21:08 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:21:08 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:21:08 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:21:08 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:21:08 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:21:08 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:21:08 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:21:08 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:21:08 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:21:08 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:21:08 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:21:08 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:21:08 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:21:08 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:21:08 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:21:08 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:21:08 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:21:08 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:21:08 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:21:08 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:21:08 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:21:08 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:21:08 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:21:08 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:21:08 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:21:08 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:21:08 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:21:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:21:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:21:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:21:08 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:21:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:21:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:21:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:21:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:21:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:21:08 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:21:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:21:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:21:08 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:21:08 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:21:08 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:21:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:21:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:21:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:21:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:21:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:21:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:21:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:21:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:21:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:21:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:21:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:21:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:21:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:21:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:21:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:21:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:21:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:21:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:21:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:21:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:21:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:21:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:21:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:21:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:21:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:21:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:21:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:21:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:21:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:21:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:21:08 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:21:09 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:21:09 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:21:09 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:21:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:21:09 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:21:09 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:21:09 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:21:09 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:21:09 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:21:09 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:21:09 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:21:10 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:21:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:21:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:21:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:21:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:21:10 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 04:21:11 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 04:21:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:21:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:21:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:21:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:21:11 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 04:21:12 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 04:21:12 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:21:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:21:12 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:21:12 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:21:12 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 04:21:13 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 04:21:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:21:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:21:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:21:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:21:13 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 04:21:14 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 04:21:14 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 04:21:15 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 04:21:15 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 04:21:16 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 04:21:16 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 04:21:17 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 04:21:17 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 04:21:18 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 04:21:18 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 04:21:19 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 04:21:19 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-27 04:21:19 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-27 04:21:20 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-27 04:21:20 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-27 04:21:21 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:21:21 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:21:21 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:21:21 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:21:21 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:21:21 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:21:21 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:21:21 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:21:21 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2693 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:21:21 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:21:21 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:21:21 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:21:21 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2693 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:21:26 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:21:26 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:21:26 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:21:26 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:21:26 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:21:26 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:21:26 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:21:26 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:21:26 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:21:26 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:21:26 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:21:26 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:21:26 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:21:26 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:21:26 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:21:26 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:21:26 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:21:26 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:21:26 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:21:26 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:21:26 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:21:26 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:21:26 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:21:26 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:21:26 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:21:26 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:21:26 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:21:26 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:21:26 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:21:26 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:21:26 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:21:26 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:21:26 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:21:26 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:21:26 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:21:26 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:21:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:21:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:21:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:21:26 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:21:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:21:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:21:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:21:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:21:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:21:26 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:21:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:21:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:21:26 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:21:26 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:21:26 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:21:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:21:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:21:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:21:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:21:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:21:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:21:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:21:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:21:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:21:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:21:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:21:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:21:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:21:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:21:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:21:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:21:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:21:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:21:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:21:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:21:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:21:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:21:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:21:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:21:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:21:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:21:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:21:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:21:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:21:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:21:26 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:21:26 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:21:26 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:21:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:21:26 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:21:26 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:21:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:21:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:21:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:21:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:21:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:21:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:21:26 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:21:26 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:21:27 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:21:27 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:21:27 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:21:27 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:21:27 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:21:27 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:21:28 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:21:28 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:21:28 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:21:28 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:21:28 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:21:28 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 04:21:29 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 04:21:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:21:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:21:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:21:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:21:29 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 04:21:29 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 04:21:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:21:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:21:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:21:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:21:30 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 04:21:30 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 04:21:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:21:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:21:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:21:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:21:31 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 04:21:31 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 04:21:32 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 04:21:32 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 04:21:33 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 04:21:33 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 04:21:34 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 04:21:34 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 04:21:35 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 04:21:35 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 04:21:36 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 04:21:36 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 04:21:37 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-27 04:21:37 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-27 04:21:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:21:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:21:37 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:21:37 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:21:37 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:21:37 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:21:37 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:21:37 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:21:37 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:21:37 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:21:37 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:21:37 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:21:37 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:21:37 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2477 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:21:37 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2477 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:21:37 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2477 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:21:37 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2477 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:21:37 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2477 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:21:37 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2477 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:21:37 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2477 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:21:42 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:21:42 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:21:42 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:21:42 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:21:42 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:21:42 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:21:42 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:21:42 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:21:42 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:21:42 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:21:42 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:21:42 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:21:42 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:21:42 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:21:42 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:21:42 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:21:42 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:21:42 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:21:42 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:21:42 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:21:42 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:21:42 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:21:42 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:21:42 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:21:42 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:21:42 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:21:42 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:21:42 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:21:42 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:21:42 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:21:42 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:21:42 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:21:42 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:21:42 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:21:42 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:21:42 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:21:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:21:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:21:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:21:42 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:21:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:21:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:21:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:21:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:21:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:21:42 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:21:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:21:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:21:42 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:21:42 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:21:42 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:21:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:21:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:21:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:21:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:21:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:21:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:21:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:21:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:21:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:21:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:21:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:21:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:21:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:21:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:21:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:21:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:21:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:21:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:21:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:21:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:21:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:21:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:21:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:21:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:21:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:21:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:21:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:21:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:21:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:21:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:21:42 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:21:43 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:21:43 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:21:43 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:21:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:21:43 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:21:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:21:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:21:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:21:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:21:43 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:21:43 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:21:43 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:21:43 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:21:43 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:21:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:21:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:21:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:21:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:21:44 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:21:44 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:21:44 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:21:44 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:21:44 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:21:44 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:21:45 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 04:21:45 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 04:21:45 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:21:45 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:21:45 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:21:45 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:21:46 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 04:21:46 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 04:21:46 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:21:46 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:21:46 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:21:46 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:21:47 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 04:21:47 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 04:21:47 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:21:47 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:21:47 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:21:47 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:21:48 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 04:21:48 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 04:21:48 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 04:21:49 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 04:21:49 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 04:21:50 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 04:21:50 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 04:21:51 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 04:21:51 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 04:21:52 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 04:21:52 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 04:21:53 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 04:21:53 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-27 04:21:54 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-27 04:21:54 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-27 04:21:55 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-27 04:21:55 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-27 04:21:56 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-27 04:21:56 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-27 04:21:56 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-27 04:21:57 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-27 04:21:57 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-27 04:21:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:21:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:21:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:21:58 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:21:58 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:21:58 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:21:58 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:21:58 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:21:58 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:21:58 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:21:58 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:21:58 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:21:58 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:21:58 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3346 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:21:58 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3346 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:21:58 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3346 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:22:03 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:22:03 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:22:03 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:22:03 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:22:03 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:22:03 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:22:03 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:22:03 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:22:03 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:22:03 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:22:03 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:22:03 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:22:03 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:22:03 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:22:03 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:22:03 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:22:03 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:22:03 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:22:03 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:22:03 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:22:03 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:22:03 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:22:03 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:22:03 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:22:03 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:22:03 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:22:03 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:22:03 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:22:03 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:22:03 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:22:03 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:22:03 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:22:03 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:22:03 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:22:03 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:22:03 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:22:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:22:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:22:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:22:03 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:22:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:22:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:22:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:22:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:22:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:22:03 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:22:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:22:03 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:22:03 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:22:03 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:22:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:22:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:22:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:22:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:22:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:22:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:22:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:22:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:22:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:22:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:22:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:22:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:22:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:22:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:22:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:22:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:22:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:22:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:22:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:22:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:22:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:22:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:22:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:22:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:22:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:22:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:22:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:22:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:22:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:22:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:22:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:22:03 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:22:03 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:22:03 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:22:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:22:03 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:22:03 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:22:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:22:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:22:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:22:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:22:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:22:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:22:03 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:22:03 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:22:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:22:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:22:03 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:22:03 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:22:03 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:22:03 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:22:03 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:22:03 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:22:03 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:22:03 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:22:03 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:22:03 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=124 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:22:03 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:22:03 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:22:03 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=124 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:22:03 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=124 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:22:03 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=124 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:22:03 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=124 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:22:03 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=125 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:22:03 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=125 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:22:03 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=125 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:22:03 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=125 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:22:03 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=125 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:22:03 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=125 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:22:03 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=125 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:22:03 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=125 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:22:08 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:22:08 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:22:08 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:22:08 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:22:08 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:22:08 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:22:08 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:22:08 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:22:08 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:22:08 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:22:08 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:22:08 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:22:08 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:22:08 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:22:08 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:22:08 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:22:08 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:22:08 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:22:08 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:22:08 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:22:08 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:22:08 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:22:08 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:22:08 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:22:08 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:22:08 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:22:08 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:22:08 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:22:08 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:22:08 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:22:08 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:22:08 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:22:08 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:22:08 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:22:08 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:22:08 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:22:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:22:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:22:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:22:08 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:22:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:22:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:22:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:22:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:22:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:22:08 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:22:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:22:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:22:08 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:22:08 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:22:08 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:22:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:22:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:22:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:22:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:22:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:22:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:22:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:22:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:22:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:22:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:22:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:22:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:22:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:22:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:22:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:22:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:22:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:22:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:22:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:22:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:22:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:22:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:22:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:22:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:22:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:22:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:22:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:22:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:22:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:22:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:22:08 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:22:09 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:22:09 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:22:09 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:22:09 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:22:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:22:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:22:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:22:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:22:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:22:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:22:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:22:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:22:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:22:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:22:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:22:09 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:22:09 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:22:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:22:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:22:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:22:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:22:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:22:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:22:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:22:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:22:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:22:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:22:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:22:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:22:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:22:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:22:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:22:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:22:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:22:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:22:09 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:22:09 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:22:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:22:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:22:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:22:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:22:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:22:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:22:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:22:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:22:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:22:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:22:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:22:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:22:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:22:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:22:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:22:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:22:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:22:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:22:09 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:22:09 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:22:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:22:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:22:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:22:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:22:09 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:22:09 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:22:09 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:22:09 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:22:09 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:22:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:22:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:22:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:22:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:22:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:22:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:22:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:22:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:22:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:22:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:22:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:22:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:22:10 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:22:10 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:22:10 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:22:10 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:22:10 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:22:10 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:22:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:22:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:22:10 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:22:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:22:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:22:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:22:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:22:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:22:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:22:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:22:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:22:10 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:22:10 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:22:10 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:22:10 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:22:10 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:22:10 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=328 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:22:10 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:22:10 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:22:10 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=329 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:22:10 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=329 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:22:10 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=329 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:22:10 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=329 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:22:10 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=329 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:22:10 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=329 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:22:10 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=329 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:22:10 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=329 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:22:10 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=330 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:22:10 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=330 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:22:10 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=330 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:22:10 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=330 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:22:10 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=330 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:22:10 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=330 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:22:10 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=330 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:22:10 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=330 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:22:15 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:22:15 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:22:15 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:22:15 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:22:15 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:22:15 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:22:15 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:22:15 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:22:15 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:22:15 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:22:15 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:22:15 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:22:15 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:22:15 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:22:15 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:22:15 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:22:15 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:22:15 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:22:15 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:22:15 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:22:15 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:22:15 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:22:15 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:22:15 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:22:15 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:22:15 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:22:15 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:22:15 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:22:15 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:22:15 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:22:15 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:22:15 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:22:15 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:22:15 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:22:15 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:22:15 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:22:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:22:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:22:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:22:15 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:22:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:22:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:22:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:22:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:22:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:22:15 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:22:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:22:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:22:15 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:22:15 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:22:15 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:22:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:22:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:22:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:22:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:22:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:22:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:22:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:22:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:22:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:22:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:22:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:22:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:22:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:22:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:22:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:22:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:22:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:22:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:22:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:22:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:22:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:22:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:22:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:22:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:22:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:22:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:22:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:22:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:22:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:22:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:22:15 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:22:15 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:22:16 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:22:16 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:22:16 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:22:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:22:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:22:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:22:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:22:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:22:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:22:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:22:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:22:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:22:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:22:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:22:16 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:22:16 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:22:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:22:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:22:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:22:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:22:16 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:22:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:22:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:22:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:22:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:22:16 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:22:17 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:22:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:22:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:22:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:22:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:22:17 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 04:22:18 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 04:22:18 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:22:18 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:22:18 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:22:18 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:22:18 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 04:22:19 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 04:22:19 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:22:19 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:22:19 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:22:19 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:22:19 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 04:22:20 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 04:22:20 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:22:20 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:22:20 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:22:20 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:22:20 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 04:22:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:22:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:22:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:22:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:22:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:22:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:22:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:22:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:22:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:22:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:22:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:22:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:22:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:22:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:22:21 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:22:21 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:22:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:22:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:22:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:22:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:22:21 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 04:22:21 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 04:22:22 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 04:22:22 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 04:22:23 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 04:22:23 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 04:22:24 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 04:22:24 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 04:22:24 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 04:22:25 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 04:22:25 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 04:22:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:22:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:22:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:22:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:22:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:22:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:22:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:22:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:22:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:22:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:22:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:22:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:22:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:22:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:22:26 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:22:26 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:22:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:22:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:22:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:22:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:22:26 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-27 04:22:26 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-27 04:22:27 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-27 04:22:27 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-27 04:22:28 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-27 04:22:28 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-27 04:22:29 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-27 04:22:29 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-27 04:22:30 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-27 04:22:30 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-27 04:22:31 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-27 04:22:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:22:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:22:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:22:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:22:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:22:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:22:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:22:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:22:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:22:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:22:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:22:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:22:31 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:22:31 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:22:31 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:22:31 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:22:31 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:22:31 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:22:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:22:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:22:31 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-27 04:22:32 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-27 04:22:32 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-27 04:22:33 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-27 04:22:33 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-27 04:22:33 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2025-04-27 04:22:34 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2025-04-27 04:22:34 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2025-04-27 04:22:35 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2025-04-27 04:22:35 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2025-04-27 04:22:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:22:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:22:36 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:22:36 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:22:36 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:22:36 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:22:36 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:22:36 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:22:36 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:22:36 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:22:36 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:22:36 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:22:36 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:22:36 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:22:36 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:22:36 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4484 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:22:36 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4484 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:22:36 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4484 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:22:36 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4484 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:22:36 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4484 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:22:36 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4484 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:22:36 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4485 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:22:36 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4485 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:22:36 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4485 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:22:36 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4485 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:22:36 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4485 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:22:36 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4485 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:22:36 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4485 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:22:36 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4485 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:22:36 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4486 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:22:36 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4486 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:22:36 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4486 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:22:36 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4486 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:22:36 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4486 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:22:36 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4486 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:22:36 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4486 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:22:36 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4486 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:22:36 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4487 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:22:36 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4487 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:22:36 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4487 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:22:36 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4487 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:22:36 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4487 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:22:36 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4487 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:22:36 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4487 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:22:36 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4487 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:22:41 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:22:41 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:22:41 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:22:41 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:22:41 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:22:41 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:22:41 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:22:41 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:22:41 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:22:41 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:22:41 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:22:41 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:22:41 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:22:41 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:22:41 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:22:41 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:22:41 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:22:41 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:22:41 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:22:41 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:22:41 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:22:41 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:22:41 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:22:41 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:22:41 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:22:41 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:22:41 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:22:41 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:22:41 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:22:41 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:22:41 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:22:41 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:22:41 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:22:41 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:22:41 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:22:41 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:22:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:22:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:22:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:22:41 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:22:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:22:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:22:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:22:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:22:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:22:41 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:22:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:22:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:22:41 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:22:41 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:22:41 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:22:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:22:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:22:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:22:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:22:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:22:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:22:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:22:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:22:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:22:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:22:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:22:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:22:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:22:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:22:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:22:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:22:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:22:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:22:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:22:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:22:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:22:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:22:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:22:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:22:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:22:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:22:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:22:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:22:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:22:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:22:41 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:22:41 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:22:41 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:22:41 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:22:41 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:22:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:22:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:22:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:22:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:22:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:22:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:22:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:22:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:22:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:22:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:22:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:22:41 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:22:41 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:22:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:22:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:22:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:22:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:22:42 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:22:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:22:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:22:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:22:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:22:42 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:22:43 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:22:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:22:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:22:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:22:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:22:43 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 04:22:44 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 04:22:44 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:22:44 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:22:44 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:22:44 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:22:44 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 04:22:45 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 04:22:45 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:22:45 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:22:45 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:22:45 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:22:45 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 04:22:46 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 04:22:46 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:22:46 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:22:46 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:22:46 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:22:46 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 04:22:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:22:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:22:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:22:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:22:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:22:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:22:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:22:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:22:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:22:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:22:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:22:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:22:47 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:22:47 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:22:47 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:22:47 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:22:47 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:22:47 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:22:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:22:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:22:47 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 04:22:47 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 04:22:48 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 04:22:48 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 04:22:48 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 04:22:49 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 04:22:49 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 04:22:50 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 04:22:50 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 04:22:51 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 04:22:51 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 04:22:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:22:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:22:52 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:22:52 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:22:52 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:22:52 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:22:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:22:52 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:22:52 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:22:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:22:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:22:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:22:52 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:22:52 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:22:52 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:22:52 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:22:52 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:22:52 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:22:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:22:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:22:52 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-27 04:22:52 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-27 04:22:53 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-27 04:22:53 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-27 04:22:54 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-27 04:22:54 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-27 04:22:55 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-27 04:22:55 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-27 04:22:56 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-27 04:22:56 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-27 04:22:57 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-27 04:22:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:22:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:22:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:22:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:22:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:22:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:22:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:22:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:22:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:22:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:22:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:22:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:22:57 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:22:57 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:22:57 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:22:57 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:22:57 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:22:57 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:22:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:22:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:22:57 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-27 04:22:57 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-27 04:22:58 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-27 04:22:58 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-27 04:22:59 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-27 04:22:59 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2025-04-27 04:23:00 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2025-04-27 04:23:00 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2025-04-27 04:23:01 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2025-04-27 04:23:01 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2025-04-27 04:23:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:23:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:23:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:23:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:23:02 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:23:02 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:23:02 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:23:02 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:23:02 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:23:02 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:23:02 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:23:02 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:23:02 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:23:02 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:23:02 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:23:02 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4477 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:23:02 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4477 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:23:02 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4477 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:23:02 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4477 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:23:02 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4477 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:23:02 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4477 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:23:02 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4477 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:23:07 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:23:07 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:23:07 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:23:07 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:23:07 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:23:07 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:23:07 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:23:07 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:23:07 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:23:07 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:23:07 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:23:07 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:23:07 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:23:07 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:23:07 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:23:07 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:23:07 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:23:07 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:23:07 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:23:07 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:23:07 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:23:07 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:23:07 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:23:07 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:23:07 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:23:07 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:23:07 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:23:07 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:23:07 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:23:07 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:23:07 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:23:07 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:23:07 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:23:07 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:23:07 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:23:07 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:23:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:23:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:23:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:23:07 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:23:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:23:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:23:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:23:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:23:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:23:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:23:07 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:23:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:23:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:23:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:23:07 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:23:07 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:23:07 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:23:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:23:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:23:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:23:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:23:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:23:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:23:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:23:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:23:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:23:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:23:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:23:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:23:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:23:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:23:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:23:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:23:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:23:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:23:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:23:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:23:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:23:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:23:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:23:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:23:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:23:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:23:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:23:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:23:07 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:23:07 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:23:07 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:23:07 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:23:07 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:23:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:23:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:23:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:23:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:23:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:23:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:23:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:23:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:23:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:23:07 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:23:07 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:23:07 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:23:07 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:23:07 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:23:07 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:23:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:23:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:23:08 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:23:08 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:23:08 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:23:08 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:23:08 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:23:08 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:23:09 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:23:09 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:23:09 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:23:09 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:23:09 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:23:09 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 04:23:10 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 04:23:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:23:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:23:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:23:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:23:10 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 04:23:11 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 04:23:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:23:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:23:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:23:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:23:11 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 04:23:11 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 04:23:12 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:23:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:23:12 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:23:12 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:23:12 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 04:23:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:23:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:23:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:23:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:23:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:23:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:23:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:23:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:23:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:23:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:23:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:23:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:23:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:23:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:23:12 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:23:12 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:23:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:23:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:23:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:23:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:23:12 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 04:23:13 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 04:23:13 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 04:23:14 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 04:23:14 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 04:23:15 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 04:23:15 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 04:23:16 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 04:23:16 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 04:23:17 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 04:23:17 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 04:23:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:23:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:23:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:23:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:23:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:23:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:23:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:23:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:23:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:23:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:23:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:23:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:23:17 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:23:17 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:23:17 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:23:17 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:23:17 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:23:17 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:23:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:23:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:23:18 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-27 04:23:18 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-27 04:23:19 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-27 04:23:19 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-27 04:23:19 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-27 04:23:20 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-27 04:23:20 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-27 04:23:21 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-27 04:23:21 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-27 04:23:22 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-27 04:23:22 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-27 04:23:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:23:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:23:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:23:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:23:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:23:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:23:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:23:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:23:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:23:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:23:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:23:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:23:22 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:23:22 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:23:22 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:23:22 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:23:22 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:23:22 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:23:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:23:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:23:23 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-27 04:23:23 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-27 04:23:24 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-27 04:23:24 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-27 04:23:25 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-27 04:23:25 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2025-04-27 04:23:26 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2025-04-27 04:23:26 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2025-04-27 04:23:27 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2025-04-27 04:23:27 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2025-04-27 04:23:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:23:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:23:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:23:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:23:27 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:23:27 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:23:27 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:23:27 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:23:27 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:23:27 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:23:27 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:23:27 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:23:27 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:23:27 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:23:27 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:23:27 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4483 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:23:27 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4483 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:23:27 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4483 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:23:27 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4483 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:23:27 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4483 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:23:27 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4483 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:23:27 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4483 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:23:27 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4484 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:23:27 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4484 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:23:27 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4484 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:23:27 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4484 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:23:27 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4484 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:23:27 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4484 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:23:27 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4484 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:23:27 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4484 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:23:32 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:23:32 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:23:32 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:23:32 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:23:32 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:23:32 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:23:32 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:23:32 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:23:32 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:23:32 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:23:32 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:23:32 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:23:32 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:23:32 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:23:32 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:23:32 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:23:32 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:23:32 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:23:32 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:23:32 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:23:32 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:23:32 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:23:32 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:23:33 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:23:33 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:23:33 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:23:33 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:23:33 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:23:33 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:23:33 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:23:33 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:23:33 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:23:33 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:23:33 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:23:33 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:23:33 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:23:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:23:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:23:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:23:33 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:23:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:23:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:23:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:23:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:23:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:23:33 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:23:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:23:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:23:33 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:23:33 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:23:33 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:23:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:23:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:23:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:23:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:23:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:23:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:23:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:23:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:23:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:23:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:23:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:23:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:23:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:23:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:23:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:23:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:23:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:23:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:23:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:23:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:23:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:23:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:23:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:23:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:23:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:23:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:23:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:23:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:23:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:23:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:23:33 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:23:33 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:23:33 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:23:33 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:23:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:23:33 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:23:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:23:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:23:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:23:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:23:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:23:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:23:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:23:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:23:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:23:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:23:33 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:23:33 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:23:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:23:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:23:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:23:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:23:33 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:23:34 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:23:34 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:23:34 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:23:34 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:23:34 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:23:34 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:23:35 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:23:35 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:23:35 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:23:35 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:23:35 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 04:23:35 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 04:23:36 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:23:36 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:23:36 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:23:36 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:23:36 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 04:23:36 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 04:23:37 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:23:37 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:23:37 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:23:37 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:23:37 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 04:23:37 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 04:23:38 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:23:38 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:23:38 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:23:38 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:23:38 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 04:23:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:23:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:23:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:23:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:23:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:23:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:23:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:23:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:23:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:23:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:23:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:23:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:23:38 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:23:38 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:23:38 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:23:38 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:23:38 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:23:38 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:23:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:23:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:23:38 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 04:23:39 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 04:23:39 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 04:23:40 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 04:23:40 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 04:23:41 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 04:23:41 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 04:23:42 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 04:23:42 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 04:23:42 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 04:23:43 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 04:23:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:23:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:23:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:23:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:23:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:23:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:23:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:23:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:23:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:23:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:23:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:23:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:23:43 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:23:43 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:23:43 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:23:43 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:23:43 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:23:43 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:23:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:23:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:23:43 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-27 04:23:44 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-27 04:23:44 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-27 04:23:45 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-27 04:23:45 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-27 04:23:46 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-27 04:23:46 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-27 04:23:47 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-27 04:23:47 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-27 04:23:48 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-27 04:23:48 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-27 04:23:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:23:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:23:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:23:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:23:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:23:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:23:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:23:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:23:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:23:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:23:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:23:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:23:48 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:23:48 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:23:48 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:23:48 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:23:48 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:23:48 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:23:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:23:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:23:49 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-27 04:23:49 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-27 04:23:50 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-27 04:23:50 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-27 04:23:51 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-27 04:23:51 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2025-04-27 04:23:51 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2025-04-27 04:23:52 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2025-04-27 04:23:52 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2025-04-27 04:23:53 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2025-04-27 04:23:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:23:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:23:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:23:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:23:53 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:23:53 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:23:53 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:23:53 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:23:53 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:23:53 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:23:53 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:23:53 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:23:53 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:23:53 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4472 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:23:53 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:23:53 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:23:53 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4472 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:23:53 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4472 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:23:53 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4472 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:23:53 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4472 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:23:53 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4472 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:23:53 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4473 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:23:53 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4473 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:23:53 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4473 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:23:53 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4473 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:23:53 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4473 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:23:53 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4473 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:23:53 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4473 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:23:53 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4473 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:23:58 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:23:58 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:23:58 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:23:58 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:23:58 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:23:58 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:23:58 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:23:58 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:23:58 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:23:58 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:23:58 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:23:58 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:23:58 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:23:58 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:23:58 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:23:58 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:23:58 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:23:58 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:23:58 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:23:58 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:23:58 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:23:58 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:23:58 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:23:58 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:23:58 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:23:58 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:23:58 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:23:58 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:23:58 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:23:58 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:23:58 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:23:58 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:23:58 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:23:58 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:23:58 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:23:58 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:23:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:23:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:23:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:23:58 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:23:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:23:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:23:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:23:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:23:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:23:58 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:23:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:23:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:23:58 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:23:58 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:23:58 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:23:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:23:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:23:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:23:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:23:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:23:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:23:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:23:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:23:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:23:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:23:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:23:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:23:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:23:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:23:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:23:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:23:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:23:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:23:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:23:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:23:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:23:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:23:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:23:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:23:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:23:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:23:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:23:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:23:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:23:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:23:58 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:23:59 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:23:59 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:23:59 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:23:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:23:59 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:23:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:23:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:23:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:23:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:23:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:23:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:23:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:23:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:23:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:23:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:23:59 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:23:59 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:23:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:23:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:23:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:23:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:23:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:23:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:23:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:23:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:23:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:23:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:23:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:23:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:23:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:23:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:23:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:23:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:23:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:23:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:23:59 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:23:59 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:23:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:23:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:23:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:23:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:23:59 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:23:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:23:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:23:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:23:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:24:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:24:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:24:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:24:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:24:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:24:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:24:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:24:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:24:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:24:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:24:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:24:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:24:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:24:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:24:00 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:24:00 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:24:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:24:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:24:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:24:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:24:00 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:24:00 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:24:00 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:24:00 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:24:00 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:24:00 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:24:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:24:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:24:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:24:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:24:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:24:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:24:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:24:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:24:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:24:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:24:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:24:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:24:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:24:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:24:00 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:24:00 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:24:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:24:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:24:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:24:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:24:01 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 04:24:01 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 04:24:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:24:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:24:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:24:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:24:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:24:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:24:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:24:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:24:01 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:24:01 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:24:01 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:24:01 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:24:01 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=636 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:24:01 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:24:01 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:24:01 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:24:01 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=636 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:24:01 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=636 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:24:01 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=636 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:24:01 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=636 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:24:01 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=636 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:24:01 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=636 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:24:01 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=636 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:24:06 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:24:06 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:24:06 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:24:06 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:24:06 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:24:06 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:24:06 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:24:06 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:24:06 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:24:06 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:24:06 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:24:06 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:24:06 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:24:06 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:24:06 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:24:06 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:24:06 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:24:06 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:24:06 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:24:06 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:24:06 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:24:06 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:24:06 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:24:06 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:24:06 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:24:06 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:24:06 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:24:06 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:24:06 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:24:06 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:24:06 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:24:06 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:24:06 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:24:06 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:24:06 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:24:06 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:24:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:24:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:24:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:24:06 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:24:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:24:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:24:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:24:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:24:06 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:24:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:24:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:24:06 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:24:06 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:24:06 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:24:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:24:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:24:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:24:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:24:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:24:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:24:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:24:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:24:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:24:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:24:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:24:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:24:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:24:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:24:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:24:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:24:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:24:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:24:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:24:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:24:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:24:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:24:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:24:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:24:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:24:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:24:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:24:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:24:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:24:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:24:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:24:06 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:24:07 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:24:07 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:24:07 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:24:07 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:24:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:24:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:24:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:24:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:24:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:24:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:24:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:24:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:24:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:24:07 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:24:07 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:24:07 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:24:07 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:24:07 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:24:07 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:24:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:24:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:24:07 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:24:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:24:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:24:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:24:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:24:08 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:24:08 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:24:08 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:24:08 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:24:08 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:24:08 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:24:09 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 04:24:09 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 04:24:09 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:24:09 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:24:09 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:24:09 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:24:10 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 04:24:10 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 04:24:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:24:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:24:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:24:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:24:11 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 04:24:11 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 04:24:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:24:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:24:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:24:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:24:12 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 04:24:12 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 04:24:12 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 04:24:13 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 04:24:13 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 04:24:14 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 04:24:14 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 04:24:15 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 04:24:15 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 04:24:16 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 04:24:16 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 04:24:17 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 04:24:17 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-27 04:24:18 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-27 04:24:18 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-27 04:24:19 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-27 04:24:19 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-27 04:24:19 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-27 04:24:20 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-27 04:24:20 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-27 04:24:21 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-27 04:24:21 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-27 04:24:22 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-27 04:24:22 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-27 04:24:23 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-27 04:24:23 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-27 04:24:24 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-27 04:24:24 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-27 04:24:25 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2025-04-27 04:24:25 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2025-04-27 04:24:26 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2025-04-27 04:24:26 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2025-04-27 04:24:27 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2025-04-27 04:24:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:24:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:24:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:24:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:24:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:24:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:24:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:24:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:24:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:24:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:24:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:24:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:24:27 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:24:27 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:24:27 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:24:27 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:24:27 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:24:27 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:24:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:24:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:24:27 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2025-04-27 04:24:28 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2025-04-27 04:24:28 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2025-04-27 04:24:28 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2025-04-27 04:24:29 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2025-04-27 04:24:29 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2025-04-27 04:24:30 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2025-04-27 04:24:30 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2025-04-27 04:24:31 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2025-04-27 04:24:31 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2025-04-27 04:24:32 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2025-04-27 04:24:32 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2025-04-27 04:24:33 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2025-04-27 04:24:33 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2025-04-27 04:24:34 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2025-04-27 04:24:34 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2025-04-27 04:24:35 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2025-04-27 04:24:35 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2025-04-27 04:24:36 [DEBUG] clck_gen.py:102 IND CLOCK 6324
2025-04-27 04:24:36 [DEBUG] clck_gen.py:102 IND CLOCK 6426
2025-04-27 04:24:36 [DEBUG] clck_gen.py:102 IND CLOCK 6528
2025-04-27 04:24:37 [DEBUG] clck_gen.py:102 IND CLOCK 6630
2025-04-27 04:24:37 [DEBUG] clck_gen.py:102 IND CLOCK 6732
2025-04-27 04:24:38 [DEBUG] clck_gen.py:102 IND CLOCK 6834
2025-04-27 04:24:38 [DEBUG] clck_gen.py:102 IND CLOCK 6936
2025-04-27 04:24:39 [DEBUG] clck_gen.py:102 IND CLOCK 7038
2025-04-27 04:24:39 [DEBUG] clck_gen.py:102 IND CLOCK 7140
2025-04-27 04:24:40 [DEBUG] clck_gen.py:102 IND CLOCK 7242
2025-04-27 04:24:40 [DEBUG] clck_gen.py:102 IND CLOCK 7344
2025-04-27 04:24:41 [DEBUG] clck_gen.py:102 IND CLOCK 7446
2025-04-27 04:24:41 [DEBUG] clck_gen.py:102 IND CLOCK 7548
2025-04-27 04:24:42 [DEBUG] clck_gen.py:102 IND CLOCK 7650
2025-04-27 04:24:42 [DEBUG] clck_gen.py:102 IND CLOCK 7752
2025-04-27 04:24:43 [DEBUG] clck_gen.py:102 IND CLOCK 7854
2025-04-27 04:24:43 [DEBUG] clck_gen.py:102 IND CLOCK 7956
2025-04-27 04:24:44 [DEBUG] clck_gen.py:102 IND CLOCK 8058
2025-04-27 04:24:44 [DEBUG] clck_gen.py:102 IND CLOCK 8160
2025-04-27 04:24:45 [DEBUG] clck_gen.py:102 IND CLOCK 8262
2025-04-27 04:24:45 [DEBUG] clck_gen.py:102 IND CLOCK 8364
2025-04-27 04:24:45 [DEBUG] clck_gen.py:102 IND CLOCK 8466
2025-04-27 04:24:46 [DEBUG] clck_gen.py:102 IND CLOCK 8568
2025-04-27 04:24:46 [DEBUG] clck_gen.py:102 IND CLOCK 8670
2025-04-27 04:24:47 [DEBUG] clck_gen.py:102 IND CLOCK 8772
2025-04-27 04:24:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:24:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:24:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:24:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:24:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:24:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:24:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:24:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:24:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:24:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:24:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:24:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:24:47 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:24:47 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:24:47 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:24:47 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:24:47 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:24:47 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:24:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:24:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:24:47 [DEBUG] clck_gen.py:102 IND CLOCK 8874
2025-04-27 04:24:48 [DEBUG] clck_gen.py:102 IND CLOCK 8976
2025-04-27 04:24:48 [DEBUG] clck_gen.py:102 IND CLOCK 9078
2025-04-27 04:24:49 [DEBUG] clck_gen.py:102 IND CLOCK 9180
2025-04-27 04:24:49 [DEBUG] clck_gen.py:102 IND CLOCK 9282
2025-04-27 04:24:50 [DEBUG] clck_gen.py:102 IND CLOCK 9384
2025-04-27 04:24:50 [DEBUG] clck_gen.py:102 IND CLOCK 9486
2025-04-27 04:24:51 [DEBUG] clck_gen.py:102 IND CLOCK 9588
2025-04-27 04:24:51 [DEBUG] clck_gen.py:102 IND CLOCK 9690
2025-04-27 04:24:52 [DEBUG] clck_gen.py:102 IND CLOCK 9792
2025-04-27 04:24:52 [DEBUG] clck_gen.py:102 IND CLOCK 9894
2025-04-27 04:24:53 [DEBUG] clck_gen.py:102 IND CLOCK 9996
2025-04-27 04:24:53 [DEBUG] clck_gen.py:102 IND CLOCK 10098
2025-04-27 04:24:54 [DEBUG] clck_gen.py:102 IND CLOCK 10200
2025-04-27 04:24:54 [DEBUG] clck_gen.py:102 IND CLOCK 10302
2025-04-27 04:24:55 [DEBUG] clck_gen.py:102 IND CLOCK 10404
2025-04-27 04:24:55 [DEBUG] clck_gen.py:102 IND CLOCK 10506
2025-04-27 04:24:56 [DEBUG] clck_gen.py:102 IND CLOCK 10608
2025-04-27 04:24:56 [DEBUG] clck_gen.py:102 IND CLOCK 10710
2025-04-27 04:24:56 [DEBUG] clck_gen.py:102 IND CLOCK 10812
2025-04-27 04:24:57 [DEBUG] clck_gen.py:102 IND CLOCK 10914
2025-04-27 04:24:57 [DEBUG] clck_gen.py:102 IND CLOCK 11016
2025-04-27 04:24:58 [DEBUG] clck_gen.py:102 IND CLOCK 11118
2025-04-27 04:24:58 [DEBUG] clck_gen.py:102 IND CLOCK 11220
2025-04-27 04:24:59 [DEBUG] clck_gen.py:102 IND CLOCK 11322
2025-04-27 04:24:59 [DEBUG] clck_gen.py:102 IND CLOCK 11424
2025-04-27 04:25:00 [DEBUG] clck_gen.py:102 IND CLOCK 11526
2025-04-27 04:25:00 [DEBUG] clck_gen.py:102 IND CLOCK 11628
2025-04-27 04:25:01 [DEBUG] clck_gen.py:102 IND CLOCK 11730
2025-04-27 04:25:01 [DEBUG] clck_gen.py:102 IND CLOCK 11832
2025-04-27 04:25:02 [DEBUG] clck_gen.py:102 IND CLOCK 11934
2025-04-27 04:25:02 [DEBUG] clck_gen.py:102 IND CLOCK 12036
2025-04-27 04:25:03 [DEBUG] clck_gen.py:102 IND CLOCK 12138
2025-04-27 04:25:03 [DEBUG] clck_gen.py:102 IND CLOCK 12240
2025-04-27 04:25:04 [DEBUG] clck_gen.py:102 IND CLOCK 12342
2025-04-27 04:25:04 [DEBUG] clck_gen.py:102 IND CLOCK 12444
2025-04-27 04:25:05 [DEBUG] clck_gen.py:102 IND CLOCK 12546
2025-04-27 04:25:05 [DEBUG] clck_gen.py:102 IND CLOCK 12648
2025-04-27 04:25:06 [DEBUG] clck_gen.py:102 IND CLOCK 12750
2025-04-27 04:25:06 [DEBUG] clck_gen.py:102 IND CLOCK 12852
2025-04-27 04:25:06 [DEBUG] clck_gen.py:102 IND CLOCK 12954
2025-04-27 04:25:07 [DEBUG] clck_gen.py:102 IND CLOCK 13056
2025-04-27 04:25:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:25:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:25:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:25:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:25:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:25:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:25:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:25:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:25:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:25:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:25:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:25:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:25:07 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:25:07 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:25:07 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:25:07 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:25:07 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:25:07 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:25:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:25:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:25:07 [DEBUG] clck_gen.py:102 IND CLOCK 13158
2025-04-27 04:25:08 [DEBUG] clck_gen.py:102 IND CLOCK 13260
2025-04-27 04:25:08 [DEBUG] clck_gen.py:102 IND CLOCK 13362
2025-04-27 04:25:09 [DEBUG] clck_gen.py:102 IND CLOCK 13464
2025-04-27 04:25:09 [DEBUG] clck_gen.py:102 IND CLOCK 13566
2025-04-27 04:25:10 [DEBUG] clck_gen.py:102 IND CLOCK 13668
2025-04-27 04:25:10 [DEBUG] clck_gen.py:102 IND CLOCK 13770
2025-04-27 04:25:11 [DEBUG] clck_gen.py:102 IND CLOCK 13872
2025-04-27 04:25:11 [DEBUG] clck_gen.py:102 IND CLOCK 13974
2025-04-27 04:25:12 [DEBUG] clck_gen.py:102 IND CLOCK 14076
2025-04-27 04:25:12 [DEBUG] clck_gen.py:102 IND CLOCK 14178
2025-04-27 04:25:13 [DEBUG] clck_gen.py:102 IND CLOCK 14280
2025-04-27 04:25:13 [DEBUG] clck_gen.py:102 IND CLOCK 14382
2025-04-27 04:25:14 [DEBUG] clck_gen.py:102 IND CLOCK 14484
2025-04-27 04:25:14 [DEBUG] clck_gen.py:102 IND CLOCK 14586
2025-04-27 04:25:15 [DEBUG] clck_gen.py:102 IND CLOCK 14688
2025-04-27 04:25:15 [DEBUG] clck_gen.py:102 IND CLOCK 14790
2025-04-27 04:25:15 [DEBUG] clck_gen.py:102 IND CLOCK 14892
2025-04-27 04:25:16 [DEBUG] clck_gen.py:102 IND CLOCK 14994
2025-04-27 04:25:16 [DEBUG] clck_gen.py:102 IND CLOCK 15096
2025-04-27 04:25:17 [DEBUG] clck_gen.py:102 IND CLOCK 15198
2025-04-27 04:25:17 [DEBUG] clck_gen.py:102 IND CLOCK 15300
2025-04-27 04:25:18 [DEBUG] clck_gen.py:102 IND CLOCK 15402
2025-04-27 04:25:18 [DEBUG] clck_gen.py:102 IND CLOCK 15504
2025-04-27 04:25:19 [DEBUG] clck_gen.py:102 IND CLOCK 15606
2025-04-27 04:25:19 [DEBUG] clck_gen.py:102 IND CLOCK 15708
2025-04-27 04:25:20 [DEBUG] clck_gen.py:102 IND CLOCK 15810
2025-04-27 04:25:20 [DEBUG] clck_gen.py:102 IND CLOCK 15912
2025-04-27 04:25:21 [DEBUG] clck_gen.py:102 IND CLOCK 16014
2025-04-27 04:25:21 [DEBUG] clck_gen.py:102 IND CLOCK 16116
2025-04-27 04:25:22 [DEBUG] clck_gen.py:102 IND CLOCK 16218
2025-04-27 04:25:22 [DEBUG] clck_gen.py:102 IND CLOCK 16320
2025-04-27 04:25:23 [DEBUG] clck_gen.py:102 IND CLOCK 16422
2025-04-27 04:25:23 [DEBUG] clck_gen.py:102 IND CLOCK 16524
2025-04-27 04:25:24 [DEBUG] clck_gen.py:102 IND CLOCK 16626
2025-04-27 04:25:24 [DEBUG] clck_gen.py:102 IND CLOCK 16728
2025-04-27 04:25:25 [DEBUG] clck_gen.py:102 IND CLOCK 16830
2025-04-27 04:25:25 [DEBUG] clck_gen.py:102 IND CLOCK 16932
2025-04-27 04:25:25 [DEBUG] clck_gen.py:102 IND CLOCK 17034
2025-04-27 04:25:26 [DEBUG] clck_gen.py:102 IND CLOCK 17136
2025-04-27 04:25:26 [DEBUG] clck_gen.py:102 IND CLOCK 17238
2025-04-27 04:25:27 [DEBUG] clck_gen.py:102 IND CLOCK 17340
2025-04-27 04:25:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:25:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:25:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:25:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:25:27 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:25:27 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:25:27 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:25:27 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:25:27 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:25:27 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:25:27 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:25:27 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:25:27 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:25:27 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:25:27 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:25:32 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:25:32 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:25:32 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:25:32 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:25:32 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:25:32 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:25:32 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:25:32 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:25:32 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:25:32 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:25:32 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:25:32 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:25:32 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:25:32 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:25:32 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:25:32 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:25:32 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:25:32 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:25:32 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:25:32 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:25:32 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:25:32 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:25:32 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:25:32 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:25:32 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:25:32 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:25:32 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:25:32 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:25:32 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:25:32 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:25:32 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:25:32 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:25:32 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:25:32 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:25:32 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:25:32 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:25:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:25:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:25:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:25:32 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:25:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:25:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:25:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:25:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:25:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:25:32 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:25:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:25:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:25:32 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:25:32 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:25:32 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:25:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:25:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:25:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:25:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:25:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:25:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:25:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:25:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:25:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:25:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:25:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:25:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:25:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:25:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:25:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:25:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:25:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:25:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:25:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:25:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:25:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:25:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:25:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:25:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:25:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:25:32 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:25:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:25:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:25:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:25:32 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:25:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:25:32 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:25:32 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:25:32 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:25:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:25:32 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:25:37 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:25:37 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:25:37 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:25:37 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:25:37 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:25:37 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:25:37 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:25:37 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:25:37 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:25:37 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:25:37 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:25:37 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:25:37 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:25:37 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:25:37 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:25:37 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:25:37 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:25:37 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:25:37 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:25:37 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:25:37 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:25:37 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:25:37 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:25:37 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:25:37 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:25:37 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:25:37 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:25:37 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:25:37 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:25:37 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:25:37 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:25:37 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:25:37 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:25:37 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:25:37 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:25:37 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:25:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:25:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:25:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:25:37 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:25:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:25:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:25:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:25:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:25:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:25:37 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:25:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:25:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:25:37 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:25:37 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:25:37 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:25:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:25:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:25:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:25:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:25:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:25:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:25:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:25:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:25:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:25:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:25:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:25:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:25:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:25:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:25:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:25:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:25:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:25:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:25:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:25:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:25:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:25:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:25:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:25:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:25:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:25:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:25:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:25:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:25:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:25:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:25:37 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:25:38 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:25:38 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:25:38 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:25:38 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:25:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:25:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:25:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:25:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:25:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:25:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:25:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:25:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:25:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:25:38 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:25:38 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:25:38 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:25:38 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:25:38 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:25:38 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:25:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:25:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:25:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:25:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:25:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:25:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:25:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:25:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:25:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:25:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:25:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:25:38 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:25:38 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:25:38 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:25:38 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:25:38 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:25:38 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:25:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:25:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:25:38 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:25:38 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:25:38 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:25:38 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:25:38 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:25:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:25:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:25:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:25:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:25:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:25:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:25:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:25:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:25:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:25:38 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:25:38 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:25:38 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:25:38 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:25:38 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:25:38 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:25:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:25:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:25:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:25:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:25:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:25:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:25:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:25:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:25:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:25:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:25:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:25:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:25:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:25:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:25:38 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:25:38 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:25:38 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:25:38 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:25:38 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:25:38 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:25:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:25:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:25:39 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:25:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:25:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:25:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:25:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:25:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:25:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:25:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:25:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:25:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:25:39 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:25:39 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:25:39 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:25:39 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:25:39 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:25:39 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:25:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:25:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:25:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:25:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:25:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:25:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:25:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:25:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:25:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:25:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:25:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:25:39 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:25:39 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:25:39 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:25:39 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:25:39 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:25:39 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:25:39 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:25:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:25:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:25:39 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:25:39 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:25:39 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:25:39 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:25:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:25:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:25:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:25:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:25:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:25:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:25:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:25:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:25:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:25:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:25:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:25:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:25:39 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:25:39 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:25:39 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:25:39 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:25:40 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:25:40 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:25:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:25:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:25:40 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 04:25:40 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 04:25:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:25:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:25:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:25:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:25:41 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 04:25:41 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 04:25:41 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:25:41 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:25:41 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:25:41 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:25:41 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 04:25:42 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 04:25:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:25:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:25:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:25:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:25:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:25:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:25:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:25:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:25:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:25:42 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:25:42 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:25:42 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:25:42 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:25:42 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:25:42 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:25:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:25:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:25:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:25:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:25:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:25:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:25:42 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 04:25:43 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 04:25:43 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 04:25:44 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 04:25:44 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 04:25:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:25:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:25:45 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:25:45 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:25:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:25:45 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:25:45 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:25:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:25:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:25:45 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:25:45 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:25:45 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:25:45 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:25:45 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:25:45 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:25:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:25:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:25:45 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 04:25:45 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 04:25:46 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 04:25:46 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 04:25:47 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 04:25:47 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 04:25:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:25:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:25:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:25:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:25:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:25:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:25:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:25:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:25:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:25:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:25:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:25:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:25:47 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:25:47 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:25:47 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:25:47 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:25:47 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:25:47 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:25:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:25:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:25:48 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 04:25:48 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-27 04:25:49 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-27 04:25:49 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-27 04:25:50 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-27 04:25:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:25:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:25:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:25:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:25:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:25:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:25:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:25:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:25:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:25:50 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:25:50 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:25:50 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:25:50 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:25:50 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:25:50 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:25:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:25:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:25:50 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-27 04:25:51 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-27 04:25:51 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-27 04:25:51 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-27 04:25:52 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-27 04:25:52 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-27 04:25:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:25:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:25:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:25:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:25:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:25:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:25:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:25:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:25:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:25:53 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:25:53 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:25:53 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:25:53 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:25:53 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:25:53 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:25:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:25:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:25:53 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-27 04:25:53 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-27 04:25:54 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-27 04:25:54 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-27 04:25:55 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-27 04:25:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:25:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:25:55 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:25:55 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:25:55 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:25:55 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:25:55 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:25:55 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:25:55 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:25:55 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:25:55 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:25:55 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:25:55 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:25:55 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:25:55 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:25:55 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3848 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:25:55 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3848 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:25:55 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3848 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:25:55 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3848 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:25:55 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3848 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:25:55 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3848 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:26:00 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:26:00 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:26:00 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:26:00 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:26:00 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:26:00 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:26:00 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:26:00 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:26:00 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:26:00 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:26:00 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:26:00 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:26:00 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:26:00 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:26:00 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:26:00 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:26:00 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:26:00 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:26:00 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:26:00 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:26:00 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:26:00 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:26:00 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:26:00 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:26:00 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:26:00 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:26:00 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:26:00 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:26:00 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:26:00 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:26:00 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:26:00 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:26:00 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:26:00 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:26:00 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:26:00 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:26:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:26:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:26:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:26:00 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:26:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:26:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:26:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:26:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:26:00 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:26:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:26:00 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:26:00 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:26:00 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:26:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:26:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:26:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:26:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:26:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:26:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:26:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:26:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:26:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:26:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:26:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:26:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:26:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:26:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:26:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:26:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:26:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:26:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:26:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:26:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:26:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:26:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:26:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:26:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:26:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:26:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:26:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:26:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:26:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:26:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:26:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:26:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:26:00 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:26:01 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:26:01 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:26:01 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:26:01 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:26:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:26:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:26:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:26:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:26:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:26:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:26:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:26:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:26:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:26:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:26:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:26:01 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:26:01 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:26:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:26:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:26:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:26:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:26:01 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:26:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:26:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:26:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:26:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:26:02 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:26:02 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:26:02 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:26:02 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:26:02 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:26:02 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:26:03 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 04:26:03 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 04:26:03 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:26:03 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:26:03 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:26:03 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:26:04 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 04:26:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:26:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:26:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:26:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:26:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:26:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:26:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:26:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:26:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:26:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:26:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:26:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:26:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:26:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:26:04 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:26:04 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:26:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:26:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:26:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:26:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:26:04 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 04:26:04 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:26:04 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:26:04 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:26:04 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:26:04 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 04:26:05 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 04:26:05 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:26:05 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:26:05 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:26:05 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:26:05 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 04:26:06 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 04:26:06 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 04:26:07 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 04:26:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:26:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:26:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:26:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:26:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:26:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:26:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:26:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:26:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:26:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:26:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:26:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:26:07 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:26:07 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:26:07 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:26:07 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:26:07 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:26:07 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:26:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:26:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:26:07 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 04:26:08 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 04:26:08 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 04:26:09 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 04:26:09 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 04:26:10 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 04:26:10 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 04:26:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:26:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:26:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:26:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:26:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:26:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:26:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:26:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:26:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:26:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:26:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:26:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:26:10 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:26:10 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:26:10 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:26:10 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:26:10 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:26:10 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:26:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:26:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:26:11 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 04:26:11 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-27 04:26:12 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-27 04:26:12 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-27 04:26:13 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-27 04:26:13 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-27 04:26:14 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-27 04:26:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:26:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:26:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:26:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:26:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:26:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:26:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:26:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:26:14 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:26:14 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:26:14 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:26:14 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:26:14 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:26:14 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:26:14 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:26:19 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:26:19 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:26:19 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:26:19 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:26:19 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:26:19 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:26:19 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:26:19 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:26:19 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:26:19 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:26:19 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:26:19 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:26:19 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:26:19 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:26:19 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:26:19 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:26:19 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:26:19 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:26:19 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:26:19 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:26:19 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:26:19 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:26:19 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:26:19 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:26:19 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:26:19 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:26:19 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:26:19 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:26:19 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:26:19 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:26:19 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:26:19 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:26:19 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:26:19 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:26:19 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:26:19 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:26:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:26:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:26:19 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:26:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:26:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:26:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:26:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:26:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:26:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:26:19 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:26:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:26:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:26:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:26:19 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:26:19 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:26:19 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:26:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:26:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:26:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:26:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:26:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:26:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:26:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:26:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:26:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:26:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:26:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:26:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:26:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:26:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:26:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:26:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:26:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:26:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:26:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:26:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:26:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:26:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:26:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:26:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:26:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:26:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:26:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:26:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:26:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:26:19 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:26:19 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:26:19 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:26:19 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:26:19 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:26:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:26:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:26:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:26:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:26:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:26:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:26:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:26:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:26:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:26:19 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:26:19 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:26:19 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:26:19 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:26:19 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:26:19 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:26:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:26:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:26:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:26:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:26:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:26:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:26:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:26:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:26:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:26:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:26:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:26:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:26:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:26:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:26:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:26:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:26:20 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:26:20 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:26:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:26:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:26:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:26:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:26:20 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:26:20 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:26:20 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:26:20 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:26:20 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:26:20 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:26:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:26:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:26:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:26:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:26:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:26:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:26:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:26:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:26:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:26:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:26:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:26:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:26:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:26:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:26:20 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:26:20 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:26:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:26:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:26:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:26:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:26:21 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:26:21 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:26:21 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:26:21 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:26:21 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:26:21 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 04:26:21 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 04:26:22 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:26:22 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:26:22 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:26:22 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:26:22 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 04:26:22 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 04:26:23 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:26:23 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:26:23 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:26:23 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:26:23 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 04:26:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:26:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:26:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:26:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:26:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:26:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:26:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:26:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:26:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:26:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:26:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:26:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:26:23 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:26:23 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:26:23 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:26:23 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:26:23 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:26:23 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:26:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:26:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:26:23 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 04:26:24 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:26:24 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:26:24 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:26:24 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:26:24 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 04:26:24 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 04:26:25 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 04:26:25 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 04:26:26 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 04:26:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:26:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:26:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:26:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:26:26 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:26:26 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:26:26 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:26:26 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:26:26 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:26:26 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:26:26 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:26:26 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:26:26 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:26:26 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:26:26 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:26:26 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1604 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:26:26 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1604 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:26:26 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1604 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:26:26 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1604 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:26:26 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1604 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:26:26 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1604 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:26:31 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:26:31 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:26:31 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:26:31 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:26:31 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:26:31 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:26:31 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:26:31 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:26:31 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:26:31 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:26:31 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:26:31 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:26:31 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:26:31 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:26:31 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:26:31 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:26:31 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:26:31 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:26:31 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:26:31 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:26:31 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:26:31 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:26:31 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:26:31 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:26:31 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:26:31 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:26:31 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:26:31 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:26:31 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:26:31 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:26:31 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:26:31 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:26:31 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:26:31 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:26:31 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:26:31 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:26:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:26:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:26:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:26:31 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:26:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:26:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:26:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:26:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:26:31 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:26:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:26:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:26:31 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:26:31 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:26:31 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:26:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:26:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:26:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:26:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:26:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:26:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:26:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:26:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:26:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:26:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:26:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:26:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:26:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:26:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:26:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:26:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:26:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:26:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:26:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:26:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:26:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:26:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:26:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:26:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:26:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:26:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:26:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:26:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:26:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:26:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:26:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:26:31 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:26:32 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:26:32 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:26:32 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:26:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:26:32 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:26:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:26:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:26:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:26:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:26:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:26:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:26:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:26:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:26:32 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:26:32 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:26:32 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:26:32 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:26:32 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:26:32 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:26:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:26:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:26:32 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:26:32 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:26:32 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:26:32 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:26:32 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:26:33 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:26:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:26:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:26:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:26:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:26:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:26:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:26:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:26:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:26:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:26:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:26:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:26:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:26:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:26:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:26:33 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:26:33 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:26:33 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:26:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:26:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:26:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:26:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:26:33 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:26:33 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:26:33 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:26:33 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:26:34 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 04:26:34 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 04:26:34 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:26:34 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:26:34 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:26:34 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:26:34 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 04:26:35 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 04:26:35 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:26:35 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:26:35 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:26:35 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:26:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:26:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:26:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:26:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:26:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:26:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:26:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:26:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:26:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:26:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:26:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:26:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:26:35 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:26:35 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:26:35 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:26:35 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:26:35 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:26:35 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:26:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:26:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:26:35 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 04:26:36 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 04:26:36 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:26:36 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:26:36 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:26:36 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:26:36 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 04:26:37 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 04:26:37 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 04:26:38 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 04:26:38 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 04:26:39 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 04:26:39 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 04:26:40 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 04:26:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:26:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:26:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:26:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:26:40 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 04:26:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:26:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:26:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:26:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:26:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:26:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:26:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:26:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:26:40 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:26:40 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:26:40 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:26:40 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:26:40 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:26:40 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:26:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:26:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:26:41 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 04:26:41 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 04:26:42 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 04:26:42 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-27 04:26:43 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-27 04:26:43 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-27 04:26:44 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-27 04:26:44 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-27 04:26:45 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-27 04:26:45 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-27 04:26:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:26:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:26:45 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:26:45 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:26:45 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:26:45 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:26:45 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:26:45 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:26:45 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:26:45 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:26:45 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:26:45 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:26:45 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2996 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:26:45 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:26:45 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:26:45 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:26:45 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2996 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:26:45 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2996 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:26:45 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2996 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:26:50 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:26:50 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:26:50 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:26:50 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:26:50 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:26:50 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:26:50 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:26:50 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:26:50 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:26:50 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:26:50 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:26:50 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:26:50 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:26:50 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:26:50 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:26:50 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:26:50 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:26:50 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:26:50 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:26:50 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:26:50 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:26:50 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:26:50 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:26:50 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:26:50 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:26:50 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:26:50 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:26:50 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:26:50 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:26:50 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:26:50 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:26:50 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:26:50 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:26:50 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:26:50 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:26:50 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:26:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:26:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:26:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:26:50 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:26:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:26:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:26:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:26:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:26:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:26:50 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:26:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:26:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:26:50 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:26:50 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:26:50 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:26:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:26:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:26:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:26:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:26:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:26:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:26:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:26:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:26:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:26:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:26:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:26:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:26:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:26:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:26:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:26:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:26:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:26:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:26:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:26:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:26:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:26:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:26:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:26:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:26:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:26:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:26:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:26:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:26:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:26:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:26:50 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:26:51 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:26:51 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:26:51 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:26:51 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:26:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:26:51 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:26:51 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:26:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:26:51 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:26:51 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:26:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:26:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:26:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:26:51 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:26:51 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:26:51 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:26:51 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:26:51 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:26:51 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:26:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:26:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:26:51 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:26:51 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:26:51 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:26:51 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:26:51 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:26:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:26:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:26:51 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:26:51 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:26:51 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:26:51 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:26:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:26:51 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:26:51 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:26:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:26:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:26:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:26:51 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:26:51 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:26:51 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:26:51 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:26:51 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:26:51 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:26:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:26:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:26:52 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:26:52 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:26:52 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:26:52 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:26:52 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:26:52 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:26:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:26:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:26:52 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:26:52 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:26:52 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:26:52 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:26:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:26:52 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:26:52 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:26:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:26:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:26:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:26:52 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:26:52 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:26:52 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:26:52 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:26:52 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:26:52 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:26:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:26:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:26:53 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 04:26:53 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 04:26:53 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:26:53 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:26:53 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:26:53 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:26:54 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 04:26:54 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 04:26:54 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:26:54 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:26:54 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:26:54 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:26:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:26:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:26:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:26:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:26:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:26:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:26:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:26:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:26:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:26:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:26:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:26:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:26:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:26:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:26:54 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:26:54 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:26:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:26:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:26:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:26:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:26:54 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 04:26:55 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 04:26:55 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:26:55 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:26:55 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:26:55 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:26:55 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 04:26:56 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 04:26:56 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 04:26:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:26:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:26:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:26:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:26:57 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:26:57 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:26:57 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:26:57 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:26:57 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:26:57 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:26:57 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:26:57 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:26:57 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:26:57 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:26:57 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:26:57 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1348 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:26:57 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1348 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:26:57 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1348 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:26:57 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1348 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:26:57 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1348 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:26:57 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1348 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:26:57 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1348 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:26:57 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1349 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:26:57 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1349 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:26:57 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1349 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:26:57 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1349 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:26:57 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1349 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:26:57 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1349 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:26:57 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1349 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:26:57 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1349 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:27:02 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:27:02 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:27:02 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:27:02 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:27:02 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:27:02 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:27:02 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:27:02 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:27:02 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:27:02 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:27:02 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:27:02 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:27:02 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:27:02 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:27:02 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:27:02 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:27:02 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:27:02 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:27:02 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:27:02 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:27:02 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:27:02 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:27:02 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:27:02 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:27:02 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:27:02 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:27:02 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:27:02 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:27:02 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:27:02 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:27:02 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:27:02 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:27:02 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:27:02 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:27:02 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:27:02 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:27:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:27:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:27:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:27:02 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:27:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:27:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:27:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:27:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:27:02 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:27:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:27:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:27:02 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:27:02 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:27:02 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:27:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:27:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:27:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:27:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:27:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:27:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:27:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:27:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:27:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:27:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:27:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:27:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:27:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:27:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:27:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:27:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:27:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:27:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:27:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:27:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:27:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:27:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:27:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:27:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:27:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:27:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:27:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:27:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:27:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:27:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:27:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:27:02 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:27:02 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:27:02 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:27:02 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:27:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:27:02 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:27:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:27:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:27:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:27:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:27:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:27:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:27:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:27:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:27:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:27:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:27:02 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:27:02 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:27:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:27:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:27:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:27:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:27:02 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:27:03 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:27:03 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:27:03 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:27:03 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:27:03 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:27:03 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:27:04 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:27:04 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:27:04 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:27:04 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:27:04 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 04:27:04 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 04:27:05 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:27:05 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:27:05 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:27:05 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:27:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:27:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:27:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:27:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:27:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:27:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:27:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:27:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:27:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:27:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:27:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:27:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:27:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:27:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:27:05 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:27:05 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:27:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:27:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:27:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:27:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:27:05 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 04:27:05 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 04:27:06 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:27:06 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:27:06 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:27:06 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:27:06 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 04:27:06 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 04:27:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:27:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:27:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:27:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:27:07 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 04:27:07 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 04:27:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:27:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:27:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:27:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:27:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:27:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:27:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:27:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:27:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:27:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:27:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:27:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:27:07 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:27:07 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:27:07 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:27:07 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:27:07 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:27:07 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:27:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:27:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:27:08 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 04:27:08 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 04:27:09 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 04:27:09 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 04:27:10 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 04:27:10 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 04:27:11 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 04:27:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:27:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:27:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:27:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:27:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:27:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:27:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:27:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:27:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:27:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:27:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:27:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:27:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:27:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:27:11 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:27:11 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:27:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:27:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:27:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:27:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:27:11 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 04:27:11 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 04:27:12 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 04:27:12 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-27 04:27:13 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-27 04:27:13 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-27 04:27:14 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-27 04:27:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:27:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:27:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:27:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:27:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:27:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:27:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:27:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:27:14 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:27:14 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:27:14 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:27:14 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:27:14 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:27:14 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:27:14 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:27:14 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2725 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:27:14 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2725 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:27:14 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2725 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:27:14 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2725 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:27:14 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2725 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:27:14 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2725 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:27:14 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2726 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:27:14 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2726 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:27:14 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2726 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:27:14 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2726 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:27:14 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2726 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:27:14 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2726 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:27:14 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2726 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:27:14 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2726 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:27:19 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:27:19 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:27:19 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:27:19 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:27:19 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:27:19 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:27:19 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:27:19 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:27:19 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:27:19 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:27:19 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:27:19 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:27:19 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:27:19 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:27:19 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:27:19 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:27:19 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:27:19 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:27:19 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:27:19 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:27:19 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:27:19 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:27:19 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:27:19 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:27:19 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:27:19 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:27:19 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:27:19 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:27:19 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:27:19 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:27:19 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:27:19 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:27:19 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:27:19 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:27:19 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:27:19 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:27:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:27:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:27:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:27:19 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:27:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:27:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:27:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:27:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:27:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:27:19 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:27:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:27:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:27:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:27:19 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:27:19 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:27:19 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:27:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:27:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:27:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:27:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:27:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:27:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:27:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:27:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:27:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:27:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:27:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:27:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:27:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:27:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:27:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:27:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:27:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:27:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:27:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:27:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:27:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:27:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:27:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:27:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:27:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:27:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:27:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:27:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:27:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:27:19 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:27:20 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:27:20 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:27:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:27:20 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:27:20 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:27:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:27:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:27:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:27:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:27:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:27:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:27:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:27:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:27:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:27:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:27:20 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:27:20 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:27:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:27:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:27:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:27:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:27:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:27:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:27:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:27:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:27:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:27:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:27:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:27:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:27:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:27:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:27:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:27:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:27:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:27:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:27:20 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:27:20 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:27:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:27:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:27:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:27:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:27:20 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:27:20 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:27:20 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:27:20 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:27:20 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:27:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:27:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:27:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:27:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:27:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:27:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:27:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:27:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:27:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:27:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:27:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:27:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:27:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:27:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:27:20 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:27:20 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:27:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:27:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:27:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:27:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:27:21 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:27:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:27:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:27:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:27:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:27:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:27:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:27:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:27:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:27:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:27:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:27:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:27:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:27:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:27:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:27:21 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:27:21 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:27:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:27:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:27:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:27:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:27:21 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:27:21 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:27:21 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:27:21 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:27:21 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:27:22 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 04:27:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:27:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:27:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:27:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:27:22 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:27:22 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:27:22 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:27:22 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:27:22 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:27:22 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:27:22 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:27:22 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:27:22 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:27:22 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=532 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:27:22 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:27:22 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:27:22 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=532 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:27:22 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=532 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:27:22 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=532 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:27:22 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=532 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:27:22 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=532 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:27:22 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=533 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:27:22 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=533 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:27:22 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=533 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:27:22 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=533 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:27:22 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=533 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:27:22 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=533 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:27:22 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=533 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:27:22 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=533 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:27:27 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:27:27 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:27:27 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:27:27 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:27:27 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:27:27 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:27:27 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:27:27 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:27:27 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:27:27 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:27:27 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:27:27 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:27:27 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:27:27 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:27:27 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:27:27 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:27:27 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:27:27 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:27:27 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:27:27 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:27:27 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:27:27 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:27:27 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:27:27 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:27:27 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:27:27 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:27:27 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:27:27 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:27:27 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:27:27 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:27:27 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:27:27 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:27:27 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:27:27 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:27:27 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:27:27 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:27:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:27:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:27:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:27:27 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:27:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:27:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:27:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:27:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:27:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:27:27 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:27:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:27:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:27:27 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:27:27 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:27:27 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:27:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:27:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:27:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:27:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:27:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:27:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:27:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:27:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:27:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:27:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:27:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:27:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:27:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:27:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:27:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:27:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:27:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:27:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:27:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:27:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:27:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:27:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:27:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:27:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:27:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:27:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:27:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:27:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:27:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:27:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:27:27 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:27:27 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:27:27 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:27:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:27:27 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:27:27 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:27:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:27:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:27:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:27:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:27:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:27:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:27:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:27:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:27:27 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:27:27 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:27:27 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:27:27 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:27:27 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:27:27 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:27:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:27:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:27:28 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:27:28 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:27:28 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:27:28 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:27:28 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:27:28 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:27:29 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:27:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:27:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:27:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:27:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:27:29 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 04:27:30 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 04:27:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:27:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:27:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:27:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:27:30 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 04:27:31 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 04:27:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:27:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:27:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:27:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:27:31 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 04:27:31 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 04:27:32 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:27:32 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:27:32 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:27:32 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:27:32 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 04:27:32 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 04:27:33 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 04:27:33 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 04:27:34 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 04:27:34 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 04:27:35 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 04:27:35 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 04:27:36 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 04:27:36 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 04:27:37 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 04:27:37 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 04:27:38 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-27 04:27:38 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-27 04:27:39 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-27 04:27:39 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-27 04:27:40 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-27 04:27:40 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-27 04:27:40 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-27 04:27:41 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-27 04:27:41 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-27 04:27:42 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-27 04:27:42 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-27 04:27:43 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-27 04:27:43 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-27 04:27:44 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-27 04:27:44 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-27 04:27:45 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-27 04:27:45 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2025-04-27 04:27:46 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2025-04-27 04:27:46 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2025-04-27 04:27:47 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2025-04-27 04:27:47 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2025-04-27 04:27:48 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2025-04-27 04:27:48 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2025-04-27 04:27:49 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2025-04-27 04:27:49 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2025-04-27 04:27:49 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2025-04-27 04:27:50 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2025-04-27 04:27:50 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2025-04-27 04:27:51 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2025-04-27 04:27:51 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2025-04-27 04:27:52 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2025-04-27 04:27:52 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2025-04-27 04:27:53 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2025-04-27 04:27:53 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2025-04-27 04:27:54 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2025-04-27 04:27:54 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2025-04-27 04:27:55 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2025-04-27 04:27:55 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2025-04-27 04:27:56 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2025-04-27 04:27:56 [DEBUG] clck_gen.py:102 IND CLOCK 6324
2025-04-27 04:27:57 [DEBUG] clck_gen.py:102 IND CLOCK 6426
2025-04-27 04:27:57 [DEBUG] clck_gen.py:102 IND CLOCK 6528
2025-04-27 04:27:58 [DEBUG] clck_gen.py:102 IND CLOCK 6630
2025-04-27 04:27:58 [DEBUG] clck_gen.py:102 IND CLOCK 6732
2025-04-27 04:27:58 [DEBUG] clck_gen.py:102 IND CLOCK 6834
2025-04-27 04:27:59 [DEBUG] clck_gen.py:102 IND CLOCK 6936
2025-04-27 04:27:59 [DEBUG] clck_gen.py:102 IND CLOCK 7038
2025-04-27 04:28:00 [DEBUG] clck_gen.py:102 IND CLOCK 7140
2025-04-27 04:28:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:28:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:28:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:28:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:28:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:28:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:28:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:28:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:28:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:28:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:28:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:28:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:28:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:28:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:28:00 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:28:00 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:28:00 [DEBUG] clck_gen.py:102 IND CLOCK 7242
2025-04-27 04:28:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:28:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:28:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:28:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:28:01 [DEBUG] clck_gen.py:102 IND CLOCK 7344
2025-04-27 04:28:01 [DEBUG] clck_gen.py:102 IND CLOCK 7446
2025-04-27 04:28:02 [DEBUG] clck_gen.py:102 IND CLOCK 7548
2025-04-27 04:28:02 [DEBUG] clck_gen.py:102 IND CLOCK 7650
2025-04-27 04:28:03 [DEBUG] clck_gen.py:102 IND CLOCK 7752
2025-04-27 04:28:03 [DEBUG] clck_gen.py:102 IND CLOCK 7854
2025-04-27 04:28:04 [DEBUG] clck_gen.py:102 IND CLOCK 7956
2025-04-27 04:28:04 [DEBUG] clck_gen.py:102 IND CLOCK 8058
2025-04-27 04:28:05 [DEBUG] clck_gen.py:102 IND CLOCK 8160
2025-04-27 04:28:05 [DEBUG] clck_gen.py:102 IND CLOCK 8262
2025-04-27 04:28:06 [DEBUG] clck_gen.py:102 IND CLOCK 8364
2025-04-27 04:28:06 [DEBUG] clck_gen.py:102 IND CLOCK 8466
2025-04-27 04:28:06 [DEBUG] clck_gen.py:102 IND CLOCK 8568
2025-04-27 04:28:07 [DEBUG] clck_gen.py:102 IND CLOCK 8670
2025-04-27 04:28:07 [DEBUG] clck_gen.py:102 IND CLOCK 8772
2025-04-27 04:28:08 [DEBUG] clck_gen.py:102 IND CLOCK 8874
2025-04-27 04:28:08 [DEBUG] clck_gen.py:102 IND CLOCK 8976
2025-04-27 04:28:09 [DEBUG] clck_gen.py:102 IND CLOCK 9078
2025-04-27 04:28:09 [DEBUG] clck_gen.py:102 IND CLOCK 9180
2025-04-27 04:28:10 [DEBUG] clck_gen.py:102 IND CLOCK 9282
2025-04-27 04:28:10 [DEBUG] clck_gen.py:102 IND CLOCK 9384
2025-04-27 04:28:11 [DEBUG] clck_gen.py:102 IND CLOCK 9486
2025-04-27 04:28:11 [DEBUG] clck_gen.py:102 IND CLOCK 9588
2025-04-27 04:28:12 [DEBUG] clck_gen.py:102 IND CLOCK 9690
2025-04-27 04:28:12 [DEBUG] clck_gen.py:102 IND CLOCK 9792
2025-04-27 04:28:13 [DEBUG] clck_gen.py:102 IND CLOCK 9894
2025-04-27 04:28:13 [DEBUG] clck_gen.py:102 IND CLOCK 9996
2025-04-27 04:28:14 [DEBUG] clck_gen.py:102 IND CLOCK 10098
2025-04-27 04:28:14 [DEBUG] clck_gen.py:102 IND CLOCK 10200
2025-04-27 04:28:14 [DEBUG] clck_gen.py:102 IND CLOCK 10302
2025-04-27 04:28:15 [DEBUG] clck_gen.py:102 IND CLOCK 10404
2025-04-27 04:28:15 [DEBUG] clck_gen.py:102 IND CLOCK 10506
2025-04-27 04:28:16 [DEBUG] clck_gen.py:102 IND CLOCK 10608
2025-04-27 04:28:16 [DEBUG] clck_gen.py:102 IND CLOCK 10710
2025-04-27 04:28:17 [DEBUG] clck_gen.py:102 IND CLOCK 10812
2025-04-27 04:28:17 [DEBUG] clck_gen.py:102 IND CLOCK 10914
2025-04-27 04:28:18 [DEBUG] clck_gen.py:102 IND CLOCK 11016
2025-04-27 04:28:18 [DEBUG] clck_gen.py:102 IND CLOCK 11118
2025-04-27 04:28:19 [DEBUG] clck_gen.py:102 IND CLOCK 11220
2025-04-27 04:28:19 [DEBUG] clck_gen.py:102 IND CLOCK 11322
2025-04-27 04:28:20 [DEBUG] clck_gen.py:102 IND CLOCK 11424
2025-04-27 04:28:20 [DEBUG] clck_gen.py:102 IND CLOCK 11526
2025-04-27 04:28:21 [DEBUG] clck_gen.py:102 IND CLOCK 11628
2025-04-27 04:28:21 [DEBUG] clck_gen.py:102 IND CLOCK 11730
2025-04-27 04:28:22 [DEBUG] clck_gen.py:102 IND CLOCK 11832
2025-04-27 04:28:22 [DEBUG] clck_gen.py:102 IND CLOCK 11934
2025-04-27 04:28:22 [DEBUG] clck_gen.py:102 IND CLOCK 12036
2025-04-27 04:28:23 [DEBUG] clck_gen.py:102 IND CLOCK 12138
2025-04-27 04:28:23 [DEBUG] clck_gen.py:102 IND CLOCK 12240
2025-04-27 04:28:24 [DEBUG] clck_gen.py:102 IND CLOCK 12342
2025-04-27 04:28:24 [DEBUG] clck_gen.py:102 IND CLOCK 12444
2025-04-27 04:28:25 [DEBUG] clck_gen.py:102 IND CLOCK 12546
2025-04-27 04:28:25 [DEBUG] clck_gen.py:102 IND CLOCK 12648
2025-04-27 04:28:26 [DEBUG] clck_gen.py:102 IND CLOCK 12750
2025-04-27 04:28:26 [DEBUG] clck_gen.py:102 IND CLOCK 12852
2025-04-27 04:28:27 [DEBUG] clck_gen.py:102 IND CLOCK 12954
2025-04-27 04:28:27 [DEBUG] clck_gen.py:102 IND CLOCK 13056
2025-04-27 04:28:28 [DEBUG] clck_gen.py:102 IND CLOCK 13158
2025-04-27 04:28:28 [DEBUG] clck_gen.py:102 IND CLOCK 13260
2025-04-27 04:28:29 [DEBUG] clck_gen.py:102 IND CLOCK 13362
2025-04-27 04:28:29 [DEBUG] clck_gen.py:102 IND CLOCK 13464
2025-04-27 04:28:30 [DEBUG] clck_gen.py:102 IND CLOCK 13566
2025-04-27 04:28:30 [DEBUG] clck_gen.py:102 IND CLOCK 13668
2025-04-27 04:28:30 [DEBUG] clck_gen.py:102 IND CLOCK 13770
2025-04-27 04:28:31 [DEBUG] clck_gen.py:102 IND CLOCK 13872
2025-04-27 04:28:31 [DEBUG] clck_gen.py:102 IND CLOCK 13974
2025-04-27 04:28:32 [DEBUG] clck_gen.py:102 IND CLOCK 14076
2025-04-27 04:28:32 [DEBUG] clck_gen.py:102 IND CLOCK 14178
2025-04-27 04:28:33 [DEBUG] clck_gen.py:102 IND CLOCK 14280
2025-04-27 04:28:33 [DEBUG] clck_gen.py:102 IND CLOCK 14382
2025-04-27 04:28:34 [DEBUG] clck_gen.py:102 IND CLOCK 14484
2025-04-27 04:28:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:28:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:28:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:28:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:28:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:28:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:28:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:28:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:28:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:28:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:28:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:28:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:28:34 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:28:34 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:28:34 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:28:34 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:28:34 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:28:34 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:28:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:28:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:28:34 [DEBUG] clck_gen.py:102 IND CLOCK 14586
2025-04-27 04:28:35 [DEBUG] clck_gen.py:102 IND CLOCK 14688
2025-04-27 04:28:35 [DEBUG] clck_gen.py:102 IND CLOCK 14790
2025-04-27 04:28:36 [DEBUG] clck_gen.py:102 IND CLOCK 14892
2025-04-27 04:28:36 [DEBUG] clck_gen.py:102 IND CLOCK 14994
2025-04-27 04:28:37 [DEBUG] clck_gen.py:102 IND CLOCK 15096
2025-04-27 04:28:37 [DEBUG] clck_gen.py:102 IND CLOCK 15198
2025-04-27 04:28:38 [DEBUG] clck_gen.py:102 IND CLOCK 15300
2025-04-27 04:28:38 [DEBUG] clck_gen.py:102 IND CLOCK 15402
2025-04-27 04:28:38 [DEBUG] clck_gen.py:102 IND CLOCK 15504
2025-04-27 04:28:39 [DEBUG] clck_gen.py:102 IND CLOCK 15606
2025-04-27 04:28:39 [DEBUG] clck_gen.py:102 IND CLOCK 15708
2025-04-27 04:28:40 [DEBUG] clck_gen.py:102 IND CLOCK 15810
2025-04-27 04:28:40 [DEBUG] clck_gen.py:102 IND CLOCK 15912
2025-04-27 04:28:41 [DEBUG] clck_gen.py:102 IND CLOCK 16014
2025-04-27 04:28:41 [DEBUG] clck_gen.py:102 IND CLOCK 16116
2025-04-27 04:28:42 [DEBUG] clck_gen.py:102 IND CLOCK 16218
2025-04-27 04:28:42 [DEBUG] clck_gen.py:102 IND CLOCK 16320
2025-04-27 04:28:43 [DEBUG] clck_gen.py:102 IND CLOCK 16422
2025-04-27 04:28:43 [DEBUG] clck_gen.py:102 IND CLOCK 16524
2025-04-27 04:28:44 [DEBUG] clck_gen.py:102 IND CLOCK 16626
2025-04-27 04:28:44 [DEBUG] clck_gen.py:102 IND CLOCK 16728
2025-04-27 04:28:45 [DEBUG] clck_gen.py:102 IND CLOCK 16830
2025-04-27 04:28:45 [DEBUG] clck_gen.py:102 IND CLOCK 16932
2025-04-27 04:28:46 [DEBUG] clck_gen.py:102 IND CLOCK 17034
2025-04-27 04:28:46 [DEBUG] clck_gen.py:102 IND CLOCK 17136
2025-04-27 04:28:46 [DEBUG] clck_gen.py:102 IND CLOCK 17238
2025-04-27 04:28:47 [DEBUG] clck_gen.py:102 IND CLOCK 17340
2025-04-27 04:28:47 [DEBUG] clck_gen.py:102 IND CLOCK 17442
2025-04-27 04:28:48 [DEBUG] clck_gen.py:102 IND CLOCK 17544
2025-04-27 04:28:48 [DEBUG] clck_gen.py:102 IND CLOCK 17646
2025-04-27 04:28:49 [DEBUG] clck_gen.py:102 IND CLOCK 17748
2025-04-27 04:28:49 [DEBUG] clck_gen.py:102 IND CLOCK 17850
2025-04-27 04:28:50 [DEBUG] clck_gen.py:102 IND CLOCK 17952
2025-04-27 04:28:50 [DEBUG] clck_gen.py:102 IND CLOCK 18054
2025-04-27 04:28:51 [DEBUG] clck_gen.py:102 IND CLOCK 18156
2025-04-27 04:28:51 [DEBUG] clck_gen.py:102 IND CLOCK 18258
2025-04-27 04:28:52 [DEBUG] clck_gen.py:102 IND CLOCK 18360
2025-04-27 04:28:52 [DEBUG] clck_gen.py:102 IND CLOCK 18462
2025-04-27 04:28:53 [DEBUG] clck_gen.py:102 IND CLOCK 18564
2025-04-27 04:28:53 [DEBUG] clck_gen.py:102 IND CLOCK 18666
2025-04-27 04:28:54 [DEBUG] clck_gen.py:102 IND CLOCK 18768
2025-04-27 04:28:54 [DEBUG] clck_gen.py:102 IND CLOCK 18870
2025-04-27 04:28:54 [DEBUG] clck_gen.py:102 IND CLOCK 18972
2025-04-27 04:28:55 [DEBUG] clck_gen.py:102 IND CLOCK 19074
2025-04-27 04:28:55 [DEBUG] clck_gen.py:102 IND CLOCK 19176
2025-04-27 04:28:56 [DEBUG] clck_gen.py:102 IND CLOCK 19278
2025-04-27 04:28:56 [DEBUG] clck_gen.py:102 IND CLOCK 19380
2025-04-27 04:28:57 [DEBUG] clck_gen.py:102 IND CLOCK 19482
2025-04-27 04:28:57 [DEBUG] clck_gen.py:102 IND CLOCK 19584
2025-04-27 04:28:58 [DEBUG] clck_gen.py:102 IND CLOCK 19686
2025-04-27 04:28:58 [DEBUG] clck_gen.py:102 IND CLOCK 19788
2025-04-27 04:28:59 [DEBUG] clck_gen.py:102 IND CLOCK 19890
2025-04-27 04:28:59 [DEBUG] clck_gen.py:102 IND CLOCK 19992
2025-04-27 04:29:00 [DEBUG] clck_gen.py:102 IND CLOCK 20094
2025-04-27 04:29:00 [DEBUG] clck_gen.py:102 IND CLOCK 20196
2025-04-27 04:29:01 [DEBUG] clck_gen.py:102 IND CLOCK 20298
2025-04-27 04:29:01 [DEBUG] clck_gen.py:102 IND CLOCK 20400
2025-04-27 04:29:02 [DEBUG] clck_gen.py:102 IND CLOCK 20502
2025-04-27 04:29:02 [DEBUG] clck_gen.py:102 IND CLOCK 20604
2025-04-27 04:29:02 [DEBUG] clck_gen.py:102 IND CLOCK 20706
2025-04-27 04:29:03 [DEBUG] clck_gen.py:102 IND CLOCK 20808
2025-04-27 04:29:03 [DEBUG] clck_gen.py:102 IND CLOCK 20910
2025-04-27 04:29:04 [DEBUG] clck_gen.py:102 IND CLOCK 21012
2025-04-27 04:29:04 [DEBUG] clck_gen.py:102 IND CLOCK 21114
2025-04-27 04:29:05 [DEBUG] clck_gen.py:102 IND CLOCK 21216
2025-04-27 04:29:05 [DEBUG] clck_gen.py:102 IND CLOCK 21318
2025-04-27 04:29:06 [DEBUG] clck_gen.py:102 IND CLOCK 21420
2025-04-27 04:29:06 [DEBUG] clck_gen.py:102 IND CLOCK 21522
2025-04-27 04:29:07 [DEBUG] clck_gen.py:102 IND CLOCK 21624
2025-04-27 04:29:07 [DEBUG] clck_gen.py:102 IND CLOCK 21726
2025-04-27 04:29:08 [DEBUG] clck_gen.py:102 IND CLOCK 21828
2025-04-27 04:29:08 [DEBUG] clck_gen.py:102 IND CLOCK 21930
2025-04-27 04:29:09 [DEBUG] clck_gen.py:102 IND CLOCK 22032
2025-04-27 04:29:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:29:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:29:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:29:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:29:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:29:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:29:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:29:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:29:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:29:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:29:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:29:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:29:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:29:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:29:09 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:29:09 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:29:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:29:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:29:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:29:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:29:09 [DEBUG] clck_gen.py:102 IND CLOCK 22134
2025-04-27 04:29:10 [DEBUG] clck_gen.py:102 IND CLOCK 22236
2025-04-27 04:29:10 [DEBUG] clck_gen.py:102 IND CLOCK 22338
2025-04-27 04:29:11 [DEBUG] clck_gen.py:102 IND CLOCK 22440
2025-04-27 04:29:11 [DEBUG] clck_gen.py:102 IND CLOCK 22542
2025-04-27 04:29:11 [DEBUG] clck_gen.py:102 IND CLOCK 22644
2025-04-27 04:29:12 [DEBUG] clck_gen.py:102 IND CLOCK 22746
2025-04-27 04:29:12 [DEBUG] clck_gen.py:102 IND CLOCK 22848
2025-04-27 04:29:13 [DEBUG] clck_gen.py:102 IND CLOCK 22950
2025-04-27 04:29:13 [DEBUG] clck_gen.py:102 IND CLOCK 23052
2025-04-27 04:29:14 [DEBUG] clck_gen.py:102 IND CLOCK 23154
2025-04-27 04:29:14 [DEBUG] clck_gen.py:102 IND CLOCK 23256
2025-04-27 04:29:15 [DEBUG] clck_gen.py:102 IND CLOCK 23358
2025-04-27 04:29:15 [DEBUG] clck_gen.py:102 IND CLOCK 23460
2025-04-27 04:29:16 [DEBUG] clck_gen.py:102 IND CLOCK 23562
2025-04-27 04:29:16 [DEBUG] clck_gen.py:102 IND CLOCK 23664
2025-04-27 04:29:17 [DEBUG] clck_gen.py:102 IND CLOCK 23766
2025-04-27 04:29:17 [DEBUG] clck_gen.py:102 IND CLOCK 23868
2025-04-27 04:29:18 [DEBUG] clck_gen.py:102 IND CLOCK 23970
2025-04-27 04:29:18 [DEBUG] clck_gen.py:102 IND CLOCK 24072
2025-04-27 04:29:19 [DEBUG] clck_gen.py:102 IND CLOCK 24174
2025-04-27 04:29:19 [DEBUG] clck_gen.py:102 IND CLOCK 24276
2025-04-27 04:29:19 [DEBUG] clck_gen.py:102 IND CLOCK 24378
2025-04-27 04:29:20 [DEBUG] clck_gen.py:102 IND CLOCK 24480
2025-04-27 04:29:20 [DEBUG] clck_gen.py:102 IND CLOCK 24582
2025-04-27 04:29:21 [DEBUG] clck_gen.py:102 IND CLOCK 24684
2025-04-27 04:29:21 [DEBUG] clck_gen.py:102 IND CLOCK 24786
2025-04-27 04:29:22 [DEBUG] clck_gen.py:102 IND CLOCK 24888
2025-04-27 04:29:22 [DEBUG] clck_gen.py:102 IND CLOCK 24990
2025-04-27 04:29:23 [DEBUG] clck_gen.py:102 IND CLOCK 25092
2025-04-27 04:29:23 [DEBUG] clck_gen.py:102 IND CLOCK 25194
2025-04-27 04:29:24 [DEBUG] clck_gen.py:102 IND CLOCK 25296
2025-04-27 04:29:24 [DEBUG] clck_gen.py:102 IND CLOCK 25398
2025-04-27 04:29:25 [DEBUG] clck_gen.py:102 IND CLOCK 25500
2025-04-27 04:29:25 [DEBUG] clck_gen.py:102 IND CLOCK 25602
2025-04-27 04:29:26 [DEBUG] clck_gen.py:102 IND CLOCK 25704
2025-04-27 04:29:26 [DEBUG] clck_gen.py:102 IND CLOCK 25806
2025-04-27 04:29:27 [DEBUG] clck_gen.py:102 IND CLOCK 25908
2025-04-27 04:29:27 [DEBUG] clck_gen.py:102 IND CLOCK 26010
2025-04-27 04:29:28 [DEBUG] clck_gen.py:102 IND CLOCK 26112
2025-04-27 04:29:28 [DEBUG] clck_gen.py:102 IND CLOCK 26214
2025-04-27 04:29:29 [DEBUG] clck_gen.py:102 IND CLOCK 26316
2025-04-27 04:29:29 [DEBUG] clck_gen.py:102 IND CLOCK 26418
2025-04-27 04:29:29 [DEBUG] clck_gen.py:102 IND CLOCK 26520
2025-04-27 04:29:30 [DEBUG] clck_gen.py:102 IND CLOCK 26622
2025-04-27 04:29:30 [DEBUG] clck_gen.py:102 IND CLOCK 26724
2025-04-27 04:29:31 [DEBUG] clck_gen.py:102 IND CLOCK 26826
2025-04-27 04:29:31 [DEBUG] clck_gen.py:102 IND CLOCK 26928
2025-04-27 04:29:32 [DEBUG] clck_gen.py:102 IND CLOCK 27030
2025-04-27 04:29:32 [DEBUG] clck_gen.py:102 IND CLOCK 27132
2025-04-27 04:29:33 [DEBUG] clck_gen.py:102 IND CLOCK 27234
2025-04-27 04:29:33 [DEBUG] clck_gen.py:102 IND CLOCK 27336
2025-04-27 04:29:34 [DEBUG] clck_gen.py:102 IND CLOCK 27438
2025-04-27 04:29:34 [DEBUG] clck_gen.py:102 IND CLOCK 27540
2025-04-27 04:29:35 [DEBUG] clck_gen.py:102 IND CLOCK 27642
2025-04-27 04:29:35 [DEBUG] clck_gen.py:102 IND CLOCK 27744
2025-04-27 04:29:36 [DEBUG] clck_gen.py:102 IND CLOCK 27846
2025-04-27 04:29:36 [DEBUG] clck_gen.py:102 IND CLOCK 27948
2025-04-27 04:29:37 [DEBUG] clck_gen.py:102 IND CLOCK 28050
2025-04-27 04:29:37 [DEBUG] clck_gen.py:102 IND CLOCK 28152
2025-04-27 04:29:37 [DEBUG] clck_gen.py:102 IND CLOCK 28254
2025-04-27 04:29:38 [DEBUG] clck_gen.py:102 IND CLOCK 28356
2025-04-27 04:29:38 [DEBUG] clck_gen.py:102 IND CLOCK 28458
2025-04-27 04:29:39 [DEBUG] clck_gen.py:102 IND CLOCK 28560
2025-04-27 04:29:39 [DEBUG] clck_gen.py:102 IND CLOCK 28662
2025-04-27 04:29:40 [DEBUG] clck_gen.py:102 IND CLOCK 28764
2025-04-27 04:29:40 [DEBUG] clck_gen.py:102 IND CLOCK 28866
2025-04-27 04:29:41 [DEBUG] clck_gen.py:102 IND CLOCK 28968
2025-04-27 04:29:41 [DEBUG] clck_gen.py:102 IND CLOCK 29070
2025-04-27 04:29:42 [DEBUG] clck_gen.py:102 IND CLOCK 29172
2025-04-27 04:29:42 [DEBUG] clck_gen.py:102 IND CLOCK 29274
2025-04-27 04:29:43 [DEBUG] clck_gen.py:102 IND CLOCK 29376
2025-04-27 04:29:43 [DEBUG] clck_gen.py:102 IND CLOCK 29478
2025-04-27 04:29:44 [DEBUG] clck_gen.py:102 IND CLOCK 29580
2025-04-27 04:29:44 [DEBUG] clck_gen.py:102 IND CLOCK 29682
2025-04-27 04:29:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:29:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:29:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:29:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:29:44 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:29:44 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:29:44 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:29:44 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:29:44 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:29:44 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:29:44 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:29:44 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:29:44 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:29:44 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:29:44 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:29:49 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:29:49 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:29:49 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:29:49 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:29:49 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:29:49 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:29:49 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:29:49 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:29:49 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:29:49 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:29:49 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:29:49 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:29:49 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:29:49 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:29:49 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:29:49 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:29:49 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:29:49 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:29:49 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:29:49 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:29:49 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:29:49 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:29:49 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:29:49 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:29:49 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:29:49 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:29:49 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:29:49 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:29:49 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:29:49 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:29:49 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:29:49 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:29:49 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:29:49 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:29:49 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:29:49 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:29:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:29:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:29:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:29:49 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:29:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:29:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:29:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:29:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:29:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:29:49 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:29:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:29:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:29:49 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:29:49 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:29:49 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:29:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:29:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:29:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:29:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:29:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:29:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:29:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:29:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:29:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:29:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:29:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:29:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:29:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:29:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:29:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:29:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:29:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:29:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:29:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:29:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:29:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:29:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:29:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:29:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:29:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:29:49 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:29:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:29:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:29:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:29:49 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:29:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:29:49 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:29:49 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:29:49 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:29:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:29:49 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:29:54 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:29:54 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:29:54 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:29:54 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:29:54 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:29:54 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:29:54 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:29:54 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:29:54 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:29:54 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:29:54 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:29:54 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:29:54 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:29:54 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:29:54 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:29:54 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:29:54 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:29:54 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:29:54 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:29:54 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:29:54 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:29:54 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:29:54 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:29:54 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:29:54 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:29:54 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:29:54 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:29:54 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:29:54 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:29:54 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:29:54 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:29:54 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:29:54 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:29:54 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:29:54 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:29:54 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:29:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:29:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:29:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:29:54 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:29:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:29:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:29:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:29:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:29:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:29:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:29:54 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:29:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:29:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:29:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:29:54 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:29:54 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:29:54 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:29:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:29:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:29:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:29:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:29:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:29:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:29:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:29:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:29:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:29:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:29:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:29:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:29:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:29:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:29:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:29:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:29:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:29:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:29:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:29:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:29:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:29:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:29:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:29:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:29:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:29:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:29:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:29:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:29:54 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:29:55 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:29:55 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:29:55 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:29:55 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:29:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:29:55 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:29:55 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:29:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:29:55 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:29:55 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:29:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:29:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:29:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:29:55 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:29:55 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:29:55 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:29:55 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:29:55 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:29:55 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:29:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:29:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:29:55 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:29:55 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:29:55 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:29:55 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:29:55 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:29:56 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:29:56 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:29:56 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:29:56 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:29:56 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:29:56 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:29:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:29:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:29:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:29:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:29:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:29:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:29:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:29:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:29:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:29:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:29:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:29:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:29:57 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:29:57 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:29:57 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:29:57 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:29:57 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:29:57 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:29:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:29:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:29:57 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 04:29:57 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 04:29:57 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:29:57 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:29:57 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:29:57 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:29:58 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 04:29:58 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 04:29:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:29:58 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:29:58 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:29:58 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:29:59 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 04:29:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:29:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:29:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:29:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:29:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:29:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:29:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:29:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:29:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:29:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:29:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:29:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:29:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:29:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:29:59 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:29:59 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:29:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:29:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:29:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:29:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:29:59 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 04:29:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:29:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:29:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:29:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:30:00 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 04:30:00 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 04:30:01 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 04:30:01 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 04:30:02 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 04:30:02 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 04:30:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:30:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:30:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:30:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:30:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:30:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:30:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:30:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:30:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:30:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:30:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:30:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:30:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:30:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:30:02 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:30:02 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:30:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:30:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:30:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:30:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:30:03 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 04:30:03 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 04:30:04 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 04:30:04 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 04:30:04 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 04:30:05 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 04:30:05 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-27 04:30:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:30:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:30:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:30:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:30:06 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:30:06 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:30:06 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:30:06 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:30:06 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:30:06 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:30:06 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:30:06 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:30:06 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:30:06 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:30:06 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:30:11 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:30:11 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:30:11 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:30:11 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:30:11 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:30:11 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:30:11 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:30:11 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:30:11 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:30:11 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:30:11 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:30:11 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:30:11 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:30:11 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:30:11 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:30:11 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:30:11 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:30:11 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:30:11 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:30:11 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:30:11 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:30:11 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:30:11 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:30:11 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:30:11 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:30:11 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:30:11 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:30:11 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:30:11 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:30:11 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:30:11 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:30:11 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:30:11 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:30:11 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:30:11 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:30:11 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:30:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:30:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:30:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:30:11 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:30:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:30:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:30:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:30:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:30:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:30:11 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:30:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:30:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:30:11 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:30:11 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:30:11 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:30:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:30:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:30:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:30:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:30:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:30:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:30:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:30:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:30:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:30:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:30:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:30:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:30:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:30:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:30:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:30:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:30:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:30:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:30:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:30:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:30:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:30:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:30:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:30:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:30:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:30:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:30:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:30:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:30:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:30:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:30:11 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:30:11 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:30:11 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:30:11 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:30:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:30:11 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:30:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:30:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:30:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:30:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:30:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:30:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:30:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:30:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:30:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:30:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:30:11 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:30:11 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:30:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:30:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:30:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:30:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:30:12 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:30:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:30:12 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:30:12 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:30:12 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:30:12 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:30:13 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:30:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:30:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:30:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:30:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:30:13 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 04:30:14 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 04:30:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:30:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:30:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:30:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:30:14 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 04:30:15 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 04:30:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:30:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:30:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:30:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:30:15 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 04:30:16 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 04:30:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:30:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:30:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:30:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:30:16 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 04:30:16 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 04:30:17 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 04:30:17 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 04:30:18 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 04:30:18 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 04:30:19 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 04:30:19 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 04:30:20 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 04:30:20 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 04:30:21 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 04:30:21 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 04:30:22 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-27 04:30:22 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-27 04:30:23 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-27 04:30:23 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-27 04:30:24 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-27 04:30:24 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-27 04:30:25 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-27 04:30:25 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-27 04:30:25 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-27 04:30:26 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-27 04:30:26 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-27 04:30:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:30:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:30:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:30:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:30:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:30:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:30:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:30:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:30:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:30:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:30:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:30:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:30:27 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:30:27 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:30:27 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:30:27 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:30:27 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:30:27 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:30:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:30:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:30:27 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-27 04:30:27 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-27 04:30:28 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-27 04:30:28 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-27 04:30:29 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-27 04:30:29 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2025-04-27 04:30:30 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2025-04-27 04:30:30 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2025-04-27 04:30:31 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2025-04-27 04:30:31 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2025-04-27 04:30:32 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2025-04-27 04:30:32 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2025-04-27 04:30:33 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2025-04-27 04:30:33 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2025-04-27 04:30:33 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2025-04-27 04:30:34 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2025-04-27 04:30:34 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2025-04-27 04:30:35 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2025-04-27 04:30:35 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2025-04-27 04:30:36 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2025-04-27 04:30:36 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2025-04-27 04:30:37 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2025-04-27 04:30:37 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2025-04-27 04:30:38 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2025-04-27 04:30:38 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2025-04-27 04:30:39 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2025-04-27 04:30:39 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2025-04-27 04:30:40 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2025-04-27 04:30:40 [DEBUG] clck_gen.py:102 IND CLOCK 6324
2025-04-27 04:30:41 [DEBUG] clck_gen.py:102 IND CLOCK 6426
2025-04-27 04:30:41 [DEBUG] clck_gen.py:102 IND CLOCK 6528
2025-04-27 04:30:42 [DEBUG] clck_gen.py:102 IND CLOCK 6630
2025-04-27 04:30:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:30:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:30:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:30:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:30:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:30:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:30:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:30:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:30:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:30:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:30:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:30:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:30:42 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:30:42 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:30:42 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:30:42 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:30:42 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:30:42 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:30:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:30:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:30:42 [DEBUG] clck_gen.py:102 IND CLOCK 6732
2025-04-27 04:30:42 [DEBUG] clck_gen.py:102 IND CLOCK 6834
2025-04-27 04:30:43 [DEBUG] clck_gen.py:102 IND CLOCK 6936
2025-04-27 04:30:43 [DEBUG] clck_gen.py:102 IND CLOCK 7038
2025-04-27 04:30:44 [DEBUG] clck_gen.py:102 IND CLOCK 7140
2025-04-27 04:30:44 [DEBUG] clck_gen.py:102 IND CLOCK 7242
2025-04-27 04:30:45 [DEBUG] clck_gen.py:102 IND CLOCK 7344
2025-04-27 04:30:45 [DEBUG] clck_gen.py:102 IND CLOCK 7446
2025-04-27 04:30:46 [DEBUG] clck_gen.py:102 IND CLOCK 7548
2025-04-27 04:30:46 [DEBUG] clck_gen.py:102 IND CLOCK 7650
2025-04-27 04:30:47 [DEBUG] clck_gen.py:102 IND CLOCK 7752
2025-04-27 04:30:47 [DEBUG] clck_gen.py:102 IND CLOCK 7854
2025-04-27 04:30:48 [DEBUG] clck_gen.py:102 IND CLOCK 7956
2025-04-27 04:30:48 [DEBUG] clck_gen.py:102 IND CLOCK 8058
2025-04-27 04:30:49 [DEBUG] clck_gen.py:102 IND CLOCK 8160
2025-04-27 04:30:49 [DEBUG] clck_gen.py:102 IND CLOCK 8262
2025-04-27 04:30:49 [DEBUG] clck_gen.py:102 IND CLOCK 8364
2025-04-27 04:30:50 [DEBUG] clck_gen.py:102 IND CLOCK 8466
2025-04-27 04:30:50 [DEBUG] clck_gen.py:102 IND CLOCK 8568
2025-04-27 04:30:51 [DEBUG] clck_gen.py:102 IND CLOCK 8670
2025-04-27 04:30:51 [DEBUG] clck_gen.py:102 IND CLOCK 8772
2025-04-27 04:30:52 [DEBUG] clck_gen.py:102 IND CLOCK 8874
2025-04-27 04:30:52 [DEBUG] clck_gen.py:102 IND CLOCK 8976
2025-04-27 04:30:53 [DEBUG] clck_gen.py:102 IND CLOCK 9078
2025-04-27 04:30:53 [DEBUG] clck_gen.py:102 IND CLOCK 9180
2025-04-27 04:30:54 [DEBUG] clck_gen.py:102 IND CLOCK 9282
2025-04-27 04:30:54 [DEBUG] clck_gen.py:102 IND CLOCK 9384
2025-04-27 04:30:55 [DEBUG] clck_gen.py:102 IND CLOCK 9486
2025-04-27 04:30:55 [DEBUG] clck_gen.py:102 IND CLOCK 9588
2025-04-27 04:30:56 [DEBUG] clck_gen.py:102 IND CLOCK 9690
2025-04-27 04:30:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:30:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:30:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:30:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:30:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:30:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:30:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:30:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:30:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:30:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:30:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:30:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:30:56 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:30:56 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:30:56 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:30:56 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:30:56 [DEBUG] clck_gen.py:102 IND CLOCK 9792
2025-04-27 04:30:56 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:30:56 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:30:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:30:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:30:57 [DEBUG] clck_gen.py:102 IND CLOCK 9894
2025-04-27 04:30:57 [DEBUG] clck_gen.py:102 IND CLOCK 9996
2025-04-27 04:30:58 [DEBUG] clck_gen.py:102 IND CLOCK 10098
2025-04-27 04:30:58 [DEBUG] clck_gen.py:102 IND CLOCK 10200
2025-04-27 04:30:58 [DEBUG] clck_gen.py:102 IND CLOCK 10302
2025-04-27 04:30:59 [DEBUG] clck_gen.py:102 IND CLOCK 10404
2025-04-27 04:30:59 [DEBUG] clck_gen.py:102 IND CLOCK 10506
2025-04-27 04:31:00 [DEBUG] clck_gen.py:102 IND CLOCK 10608
2025-04-27 04:31:00 [DEBUG] clck_gen.py:102 IND CLOCK 10710
2025-04-27 04:31:01 [DEBUG] clck_gen.py:102 IND CLOCK 10812
2025-04-27 04:31:01 [DEBUG] clck_gen.py:102 IND CLOCK 10914
2025-04-27 04:31:02 [DEBUG] clck_gen.py:102 IND CLOCK 11016
2025-04-27 04:31:02 [DEBUG] clck_gen.py:102 IND CLOCK 11118
2025-04-27 04:31:03 [DEBUG] clck_gen.py:102 IND CLOCK 11220
2025-04-27 04:31:03 [DEBUG] clck_gen.py:102 IND CLOCK 11322
2025-04-27 04:31:04 [DEBUG] clck_gen.py:102 IND CLOCK 11424
2025-04-27 04:31:04 [DEBUG] clck_gen.py:102 IND CLOCK 11526
2025-04-27 04:31:05 [DEBUG] clck_gen.py:102 IND CLOCK 11628
2025-04-27 04:31:05 [DEBUG] clck_gen.py:102 IND CLOCK 11730
2025-04-27 04:31:06 [DEBUG] clck_gen.py:102 IND CLOCK 11832
2025-04-27 04:31:06 [DEBUG] clck_gen.py:102 IND CLOCK 11934
2025-04-27 04:31:07 [DEBUG] clck_gen.py:102 IND CLOCK 12036
2025-04-27 04:31:07 [DEBUG] clck_gen.py:102 IND CLOCK 12138
2025-04-27 04:31:07 [DEBUG] clck_gen.py:102 IND CLOCK 12240
2025-04-27 04:31:08 [DEBUG] clck_gen.py:102 IND CLOCK 12342
2025-04-27 04:31:08 [DEBUG] clck_gen.py:102 IND CLOCK 12444
2025-04-27 04:31:09 [DEBUG] clck_gen.py:102 IND CLOCK 12546
2025-04-27 04:31:09 [DEBUG] clck_gen.py:102 IND CLOCK 12648
2025-04-27 04:31:10 [DEBUG] clck_gen.py:102 IND CLOCK 12750
2025-04-27 04:31:10 [DEBUG] clck_gen.py:102 IND CLOCK 12852
2025-04-27 04:31:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:31:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:31:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:31:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:31:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:31:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:31:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:31:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:31:11 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:31:11 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:31:11 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:31:11 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:31:11 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:31:11 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:31:11 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:31:11 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=12943 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:31:11 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=12943 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:31:11 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=12943 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:31:11 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=12943 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:31:11 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=12943 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:31:11 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=12943 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:31:11 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=12943 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:31:16 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:31:16 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:31:16 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:31:16 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:31:16 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:31:16 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:31:16 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:31:16 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:31:16 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:31:16 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:31:16 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:31:16 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:31:16 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:31:16 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:31:16 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:31:16 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:31:16 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:31:16 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:31:16 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:31:16 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:31:16 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:31:16 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:31:16 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:31:16 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:31:16 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:31:16 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:31:16 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:31:16 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:31:16 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:31:16 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:31:16 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:31:16 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:31:16 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:31:16 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:31:16 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:31:16 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:31:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:31:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:31:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:31:16 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:31:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:31:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:31:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:31:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:31:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:31:16 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:31:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:31:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:31:16 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:31:16 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:31:16 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:31:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:31:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:31:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:31:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:31:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:31:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:31:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:31:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:31:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:31:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:31:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:31:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:31:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:31:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:31:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:31:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:31:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:31:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:31:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:31:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:31:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:31:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:31:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:31:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:31:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:31:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:31:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:31:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:31:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:31:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:31:16 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:31:16 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:31:16 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:31:16 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:31:16 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:31:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:31:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:31:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:31:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:31:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:31:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:31:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:31:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:31:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:31:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:31:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:31:16 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:31:16 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:31:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:31:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:31:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:31:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:31:17 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:31:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:31:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:31:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:31:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:31:17 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:31:18 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:31:18 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:31:18 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:31:18 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:31:18 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:31:18 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 04:31:19 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 04:31:19 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:31:19 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:31:19 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:31:19 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:31:19 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 04:31:20 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 04:31:20 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:31:20 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:31:20 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:31:20 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:31:20 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 04:31:20 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 04:31:21 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:31:21 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:31:21 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:31:21 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:31:21 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 04:31:21 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 04:31:22 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 04:31:22 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 04:31:23 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 04:31:23 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 04:31:24 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 04:31:24 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 04:31:25 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 04:31:25 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 04:31:26 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 04:31:26 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 04:31:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:31:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:31:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:31:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:31:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:31:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:31:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:31:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:31:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:31:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:31:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:31:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:31:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:31:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:31:26 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:31:26 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:31:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:31:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:31:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:31:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:31:27 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-27 04:31:27 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-27 04:31:28 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-27 04:31:28 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-27 04:31:29 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-27 04:31:29 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-27 04:31:29 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-27 04:31:30 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-27 04:31:30 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-27 04:31:31 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-27 04:31:31 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-27 04:31:32 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-27 04:31:32 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-27 04:31:33 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-27 04:31:33 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-27 04:31:34 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-27 04:31:34 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2025-04-27 04:31:35 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2025-04-27 04:31:35 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2025-04-27 04:31:36 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2025-04-27 04:31:36 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2025-04-27 04:31:37 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2025-04-27 04:31:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:31:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:31:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:31:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:31:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:31:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:31:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:31:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:31:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:31:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:31:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:31:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:31:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:31:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:31:37 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:31:37 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:31:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:31:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:31:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:31:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:31:37 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2025-04-27 04:31:38 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2025-04-27 04:31:38 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2025-04-27 04:31:38 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2025-04-27 04:31:39 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2025-04-27 04:31:39 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2025-04-27 04:31:40 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2025-04-27 04:31:40 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2025-04-27 04:31:41 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2025-04-27 04:31:41 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2025-04-27 04:31:42 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2025-04-27 04:31:42 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2025-04-27 04:31:43 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2025-04-27 04:31:43 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2025-04-27 04:31:44 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2025-04-27 04:31:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:31:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:31:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:31:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:31:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:31:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:31:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:31:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:31:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:31:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:31:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:31:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:31:44 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:31:44 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:31:44 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:31:44 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:31:44 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:31:44 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:31:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:31:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:31:44 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2025-04-27 04:31:45 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2025-04-27 04:31:45 [DEBUG] clck_gen.py:102 IND CLOCK 6324
2025-04-27 04:31:46 [DEBUG] clck_gen.py:102 IND CLOCK 6426
2025-04-27 04:31:46 [DEBUG] clck_gen.py:102 IND CLOCK 6528
2025-04-27 04:31:46 [DEBUG] clck_gen.py:102 IND CLOCK 6630
2025-04-27 04:31:47 [DEBUG] clck_gen.py:102 IND CLOCK 6732
2025-04-27 04:31:47 [DEBUG] clck_gen.py:102 IND CLOCK 6834
2025-04-27 04:31:48 [DEBUG] clck_gen.py:102 IND CLOCK 6936
2025-04-27 04:31:48 [DEBUG] clck_gen.py:102 IND CLOCK 7038
2025-04-27 04:31:49 [DEBUG] clck_gen.py:102 IND CLOCK 7140
2025-04-27 04:31:49 [DEBUG] clck_gen.py:102 IND CLOCK 7242
2025-04-27 04:31:50 [DEBUG] clck_gen.py:102 IND CLOCK 7344
2025-04-27 04:31:50 [DEBUG] clck_gen.py:102 IND CLOCK 7446
2025-04-27 04:31:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:31:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:31:51 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:31:51 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:31:51 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:31:51 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:31:51 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:31:51 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:31:51 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:31:51 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:31:51 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:31:51 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:31:51 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:31:51 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:31:51 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:31:56 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:31:56 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:31:56 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:31:56 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:31:56 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:31:56 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:31:56 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:31:56 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:31:56 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:31:56 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:31:56 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:31:56 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:31:56 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:31:56 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:31:56 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:31:56 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:31:56 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:31:56 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:31:56 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:31:56 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:31:56 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:31:56 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:31:56 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:31:56 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:31:56 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:31:56 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:31:56 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:31:56 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:31:56 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:31:56 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:31:56 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:31:56 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:31:56 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:31:56 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:31:56 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:31:56 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:31:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:31:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:31:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:31:56 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:31:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:31:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:31:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:31:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:31:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:31:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:31:56 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:31:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:31:56 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:31:56 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:31:56 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:31:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:31:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:31:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:31:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:31:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:31:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:31:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:31:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:31:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:31:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:31:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:31:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:31:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:31:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:31:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:31:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:31:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:31:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:31:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:31:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:31:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:31:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:31:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:31:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:31:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:31:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:31:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:31:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:31:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:31:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:31:56 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:31:56 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:31:56 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:31:56 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:31:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:31:56 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:31:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:31:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:31:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:31:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:31:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:31:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:31:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:31:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:31:56 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:31:56 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:31:56 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:31:56 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:31:56 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:31:56 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:31:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:31:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:31:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:31:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:31:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:31:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:31:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:31:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:31:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:31:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:31:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:31:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:31:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:31:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:31:57 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:31:57 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:31:57 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:31:57 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:31:57 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:31:57 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:31:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:31:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:31:57 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:31:57 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:31:57 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:31:57 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:31:57 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:31:57 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:31:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:31:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:31:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:31:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:31:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:31:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:31:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:31:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:31:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:31:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:31:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:31:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:31:57 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:31:57 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:31:57 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:31:57 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:31:57 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:31:57 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:31:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:31:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:31:58 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:31:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:31:58 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:31:58 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:31:58 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:31:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:31:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:31:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:31:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:31:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:31:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:31:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:31:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:31:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:31:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:31:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:31:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:31:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:31:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:31:58 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:31:58 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:31:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:31:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:31:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:31:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:31:58 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 04:31:59 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 04:31:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:31:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:31:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:31:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:31:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:31:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:31:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:31:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:31:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:31:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:31:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:31:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:31:59 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:31:59 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:31:59 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:31:59 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:31:59 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:31:59 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:31:59 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:32:04 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:32:04 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:32:04 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:32:04 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:32:04 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:32:04 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:32:04 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:32:04 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:32:04 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:32:04 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:32:04 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:32:04 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:32:04 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:32:04 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:32:04 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:32:04 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:32:04 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:32:04 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:32:04 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:32:04 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:32:04 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:32:04 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:32:04 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:32:04 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:32:04 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:32:04 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:32:04 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:32:04 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:32:04 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:32:04 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:32:04 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:32:04 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:32:04 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:32:04 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:32:04 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:32:04 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:32:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:32:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:32:04 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:32:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:32:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:32:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:32:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:32:04 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:32:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:32:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:32:04 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:32:04 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:32:04 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:32:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:32:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:32:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:32:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:32:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:32:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:32:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:32:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:32:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:32:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:32:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:32:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:32:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:32:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:32:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:32:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:32:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:32:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:32:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:32:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:32:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:32:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:32:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:32:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:32:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:32:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:32:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:32:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:32:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:32:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:32:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:32:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:32:04 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:32:04 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:32:04 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:32:04 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:32:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:32:04 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:32:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:32:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:32:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:32:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:32:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:32:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:32:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:32:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:32:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:32:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:32:04 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:32:04 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:32:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:32:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:32:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:32:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:32:05 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:32:05 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:32:05 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:32:05 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:32:05 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:32:05 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:32:06 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:32:06 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:32:06 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:32:06 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:32:06 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:32:06 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 04:32:07 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 04:32:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:32:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:32:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:32:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:32:07 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 04:32:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:32:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:32:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:32:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:32:08 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 04:32:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:32:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:32:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:32:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:32:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:32:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:32:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:32:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:32:08 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:32:08 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:32:08 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:32:08 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:32:08 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:32:08 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:32:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:32:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:32:08 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:32:08 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:32:08 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:32:08 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:32:08 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 04:32:09 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 04:32:09 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:32:09 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:32:09 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:32:09 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:32:09 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 04:32:10 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 04:32:10 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 04:32:11 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 04:32:11 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 04:32:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:32:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:32:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:32:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:32:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:32:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:32:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:32:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:32:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:32:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:32:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:32:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:32:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:32:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:32:11 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:32:11 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:32:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:32:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:32:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:32:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:32:11 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 04:32:12 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 04:32:12 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 04:32:13 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 04:32:13 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 04:32:14 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 04:32:14 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 04:32:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:32:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:32:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:32:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:32:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:32:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:32:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:32:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:32:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:32:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:32:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:32:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:32:15 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:32:15 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:32:15 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:32:15 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:32:15 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:32:15 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:32:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:32:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:32:15 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-27 04:32:15 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-27 04:32:16 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-27 04:32:16 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-27 04:32:17 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-27 04:32:17 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-27 04:32:18 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-27 04:32:18 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-27 04:32:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:32:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:32:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:32:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:32:18 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:32:18 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:32:18 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:32:18 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:32:18 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:32:18 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:32:18 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:32:18 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:32:18 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:32:18 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:32:18 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:32:23 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:32:23 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:32:23 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:32:23 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:32:23 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:32:23 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:32:23 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:32:23 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:32:23 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:32:23 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:32:23 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:32:23 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:32:23 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:32:23 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:32:23 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:32:23 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:32:23 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:32:23 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:32:23 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:32:23 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:32:23 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:32:23 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:32:23 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:32:23 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:32:23 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:32:23 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:32:23 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:32:23 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:32:23 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:32:23 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:32:23 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:32:23 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:32:23 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:32:23 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:32:23 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:32:23 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:32:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:32:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:32:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:32:23 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:32:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:32:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:32:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:32:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:32:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:32:23 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:32:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:32:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:32:23 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:32:23 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:32:23 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:32:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:32:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:32:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:32:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:32:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:32:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:32:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:32:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:32:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:32:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:32:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:32:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:32:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:32:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:32:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:32:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:32:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:32:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:32:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:32:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:32:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:32:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:32:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:32:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:32:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:32:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:32:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:32:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:32:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:32:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:32:23 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:32:24 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:32:24 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:32:24 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:32:24 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:32:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:32:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:32:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:32:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:32:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:32:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:32:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:32:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:32:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:32:24 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:32:24 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:32:24 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:32:24 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:32:24 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:32:24 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:32:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:32:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:32:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:32:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:32:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:32:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:32:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:32:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:32:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:32:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:32:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:32:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:32:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:32:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:32:24 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:32:24 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:32:24 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:32:24 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:32:24 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:32:24 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:32:24 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:32:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:32:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:32:24 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:32:24 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:32:24 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:32:24 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:32:25 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:32:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:32:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:32:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:32:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:32:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:32:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:32:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:32:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:32:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:32:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:32:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:32:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:32:25 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:32:25 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:32:25 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:32:25 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:32:25 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:32:25 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:32:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:32:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:32:25 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:32:25 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:32:25 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:32:25 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:32:25 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:32:26 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 04:32:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:32:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:32:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:32:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:32:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:32:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:32:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:32:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:32:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:32:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:32:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:32:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:32:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:32:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:32:26 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:32:26 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:32:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:32:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:32:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:32:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:32:26 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 04:32:26 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:32:26 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:32:26 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:32:26 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:32:27 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 04:32:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:32:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:32:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:32:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:32:27 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:32:27 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:32:27 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:32:27 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:32:27 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:32:27 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:32:27 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:32:27 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:32:27 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:32:27 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:32:27 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:32:27 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=785 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:32:27 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=785 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:32:27 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=785 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:32:27 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=785 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:32:27 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=785 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:32:27 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=785 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:32:27 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=785 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:32:32 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:32:32 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:32:32 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:32:32 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:32:32 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:32:32 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:32:32 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:32:32 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:32:32 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:32:32 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:32:32 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:32:32 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:32:32 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:32:32 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:32:32 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:32:32 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:32:32 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:32:32 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:32:32 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:32:32 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:32:32 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:32:32 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:32:32 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:32:32 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:32:32 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:32:32 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:32:32 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:32:32 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:32:32 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:32:32 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:32:32 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:32:32 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:32:32 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:32:32 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:32:32 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:32:32 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:32:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:32:32 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:32:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:32:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:32:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:32:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:32:32 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:32:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:32:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:32:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:32:32 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:32:32 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:32:32 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:32:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:32:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:32:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:32:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:32:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:32:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:32:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:32:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:32:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:32:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:32:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:32:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:32:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:32:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:32:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:32:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:32:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:32:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:32:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:32:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:32:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:32:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:32:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:32:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:32:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:32:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:32:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:32:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:32:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:32:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:32:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:32:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:32:32 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:32:33 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:32:33 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:32:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:32:33 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:32:33 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:32:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:32:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:32:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:32:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:32:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:32:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:32:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:32:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:32:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:32:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:32:33 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:32:33 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:32:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:32:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:32:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:32:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:32:33 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:32:33 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:32:33 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:32:33 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:32:33 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:32:34 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:32:34 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:32:34 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:32:34 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:32:34 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:32:34 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:32:35 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 04:32:35 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 04:32:35 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:32:35 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:32:35 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:32:35 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:32:35 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 04:32:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:32:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:32:36 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:32:36 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:32:36 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:32:36 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:32:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:32:36 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:32:36 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:32:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:32:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:32:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:32:36 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:32:36 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:32:36 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:32:36 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:32:36 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:32:36 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:32:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:32:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:32:36 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 04:32:36 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:32:36 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:32:36 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:32:36 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:32:36 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 04:32:37 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 04:32:37 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:32:37 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:32:37 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:32:37 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:32:37 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 04:32:38 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 04:32:38 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 04:32:39 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 04:32:39 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 04:32:40 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 04:32:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:32:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:32:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:32:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:32:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:32:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:32:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:32:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:32:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:32:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:32:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:32:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:32:40 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:32:40 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:32:40 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:32:40 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:32:40 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:32:40 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:32:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:32:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:32:40 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 04:32:41 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 04:32:41 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 04:32:42 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 04:32:42 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 04:32:43 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 04:32:43 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-27 04:32:43 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-27 04:32:44 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-27 04:32:44 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-27 04:32:45 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-27 04:32:45 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-27 04:32:46 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-27 04:32:46 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-27 04:32:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:32:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:32:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:32:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:32:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:32:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:32:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:32:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:32:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:32:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:32:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:32:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:32:47 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:32:47 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:32:47 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:32:47 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:32:47 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:32:47 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:32:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:32:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:32:47 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-27 04:32:47 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-27 04:32:48 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-27 04:32:48 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-27 04:32:49 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-27 04:32:49 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-27 04:32:50 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-27 04:32:50 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-27 04:32:51 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2025-04-27 04:32:51 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2025-04-27 04:32:52 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2025-04-27 04:32:52 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2025-04-27 04:32:52 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2025-04-27 04:32:53 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2025-04-27 04:32:53 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2025-04-27 04:32:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:32:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:32:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:32:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:32:54 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:32:54 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:32:54 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:32:54 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:32:54 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:32:54 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:32:54 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:32:54 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:32:54 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:32:54 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:32:54 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:32:59 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:32:59 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:32:59 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:32:59 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:32:59 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:32:59 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:32:59 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:32:59 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:32:59 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:32:59 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:32:59 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:32:59 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:32:59 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:32:59 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:32:59 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:32:59 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:32:59 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:32:59 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:32:59 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:32:59 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:32:59 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:32:59 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:32:59 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:32:59 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:32:59 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:32:59 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:32:59 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:32:59 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:32:59 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:32:59 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:32:59 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:32:59 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:32:59 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:32:59 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:32:59 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:32:59 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:32:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:32:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:32:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:32:59 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:32:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:32:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:32:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:32:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:32:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:32:59 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:32:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:32:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:32:59 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:32:59 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:32:59 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:32:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:32:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:32:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:32:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:32:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:32:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:32:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:32:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:32:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:32:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:32:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:32:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:32:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:32:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:32:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:32:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:32:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:32:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:32:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:32:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:32:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:32:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:32:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:32:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:32:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:32:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:32:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:32:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:32:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:32:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:32:59 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:32:59 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:32:59 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:32:59 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:32:59 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:32:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:32:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:32:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:32:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:32:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:32:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:32:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:32:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:32:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:32:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:32:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:32:59 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:32:59 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:32:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:32:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:32:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:32:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:32:59 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:33:00 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:33:00 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:33:00 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:33:00 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:33:00 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:33:00 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:33:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:33:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:33:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:33:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:33:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:33:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:33:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:33:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:33:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:33:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:33:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:33:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:33:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:33:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:33:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:33:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:33:01 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:33:01 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:33:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:33:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:33:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:33:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:33:01 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 04:33:01 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 04:33:02 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:33:02 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:33:02 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:33:02 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:33:02 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 04:33:02 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 04:33:03 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:33:03 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:33:03 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:33:03 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:33:03 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 04:33:03 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 04:33:04 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:33:04 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:33:04 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:33:04 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:33:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:33:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:33:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:33:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:33:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:33:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:33:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:33:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:33:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:33:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:33:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:33:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:33:04 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:33:04 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:33:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:33:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:33:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:33:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:33:04 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 04:33:04 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 04:33:05 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 04:33:05 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 04:33:06 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 04:33:06 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 04:33:07 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 04:33:07 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 04:33:08 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 04:33:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:33:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:33:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:33:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:33:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:33:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:33:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:33:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:33:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:33:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:33:08 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:33:08 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:33:08 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:33:08 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:33:08 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:33:08 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:33:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:33:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:33:08 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 04:33:09 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 04:33:09 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 04:33:09 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-27 04:33:10 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-27 04:33:10 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-27 04:33:11 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-27 04:33:11 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-27 04:33:12 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-27 04:33:12 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-27 04:33:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:33:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:33:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:33:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:33:12 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:33:12 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:33:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:33:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:33:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:33:12 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:33:12 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:33:12 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:33:12 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:33:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:33:12 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2980 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:33:12 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2980 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:33:12 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2980 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:33:12 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2980 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:33:12 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2980 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:33:12 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2980 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:33:17 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:33:17 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:33:17 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:33:17 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:33:17 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:33:17 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:33:17 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:33:17 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:33:17 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:33:17 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:33:17 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:33:17 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:33:17 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:33:17 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:33:17 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:33:17 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:33:17 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:33:17 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:33:17 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:33:17 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:33:17 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:33:17 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:33:17 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:33:17 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:33:17 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:33:17 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:33:17 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:33:17 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:33:17 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:33:17 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:33:17 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:33:17 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:33:17 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:33:17 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:33:17 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:33:17 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:33:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:33:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:33:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:33:17 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:33:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:33:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:33:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:33:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:33:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:33:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:33:17 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:33:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:33:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:33:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:33:17 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:33:17 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:33:17 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:33:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:33:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:33:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:33:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:33:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:33:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:33:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:33:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:33:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:33:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:33:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:33:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:33:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:33:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:33:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:33:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:33:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:33:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:33:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:33:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:33:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:33:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:33:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:33:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:33:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:33:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:33:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:33:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:33:17 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:33:18 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:33:18 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:33:18 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:33:18 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:33:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:18 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:33:18 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:33:18 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:33:18 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:33:18 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:33:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:19 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:33:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:19 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:33:19 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:33:19 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:33:19 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:33:19 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:33:19 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:33:19 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:33:19 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:33:19 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:33:19 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:33:19 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:33:19 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=398 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:33:19 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=398 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:33:19 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=398 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:33:19 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=398 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:33:19 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=398 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:33:19 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=398 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:33:24 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:33:24 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:33:24 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:33:24 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:33:24 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:33:24 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:33:24 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:33:24 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:33:24 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:33:24 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:33:24 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:33:24 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:33:24 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:33:24 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:33:24 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:33:24 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:33:24 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:33:24 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:33:24 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:33:24 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:33:24 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:33:24 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:33:24 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:33:24 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:33:24 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:33:24 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:33:24 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:33:24 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:33:24 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:33:24 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:33:24 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:33:24 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:33:24 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:33:24 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:33:24 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:33:24 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:33:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:33:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:33:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:33:24 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:33:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:33:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:33:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:33:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:33:24 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:33:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:33:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:33:24 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:33:24 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:33:24 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:33:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:33:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:33:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:33:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:33:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:33:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:33:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:33:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:33:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:33:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:33:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:33:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:33:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:33:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:33:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:33:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:33:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:33:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:33:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:33:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:33:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:33:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:33:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:33:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:33:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:33:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:33:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:33:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:33:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:33:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:33:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:33:24 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:33:25 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:33:25 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:33:25 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:33:25 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:33:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:25 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:33:25 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:33:25 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:33:25 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:33:25 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:33:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:26 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:33:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:26 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:33:26 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:33:26 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:33:26 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:33:26 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:33:26 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:33:26 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:33:26 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:33:26 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:33:26 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:33:26 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:33:31 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:33:31 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:33:31 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:33:31 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:33:31 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:33:31 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:33:31 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:33:31 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:33:31 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:33:31 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:33:31 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:33:31 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:33:31 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:33:31 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:33:31 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:33:31 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:33:31 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:33:31 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:33:31 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:33:31 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:33:31 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:33:31 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:33:31 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:33:31 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:33:31 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:33:31 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:33:31 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:33:31 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:33:31 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:33:31 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:33:31 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:33:31 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:33:31 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:33:31 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:33:31 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:33:31 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:33:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:33:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:33:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:33:31 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:33:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:33:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:33:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:33:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:33:31 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:33:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:33:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:33:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:33:31 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:33:31 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:33:31 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:33:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:33:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:33:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:33:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:33:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:33:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:33:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:33:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:33:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:33:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:33:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:33:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:33:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:33:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:33:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:33:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:33:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:33:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:33:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:33:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:33:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:33:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:33:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:33:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:33:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:33:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:33:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:33:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:33:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:33:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:33:31 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:33:32 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:33:32 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:33:32 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:33:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:32 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:33:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:32 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:33:32 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:33:32 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:33:32 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:33:32 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:33:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:33 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:33:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:33 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:33:33 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:33:33 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:33:33 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:33:33 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:33:33 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:33:33 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:33:33 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:33:33 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:33:33 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:33:33 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:33:33 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=398 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:33:33 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=399 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:33:33 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=399 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:33:33 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=399 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:33:33 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=399 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:33:33 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=399 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:33:33 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=399 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:33:33 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=399 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:33:33 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=399 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:33:38 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:33:38 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:33:38 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:33:38 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:33:38 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:33:38 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:33:38 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:33:38 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:33:38 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:33:38 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:33:38 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:33:38 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:33:38 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:33:38 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:33:38 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:33:38 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:33:38 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:33:38 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:33:38 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:33:38 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:33:38 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:33:38 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:33:38 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:33:38 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:33:38 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:33:38 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:33:38 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:33:38 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:33:38 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:33:38 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:33:38 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:33:38 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:33:38 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:33:38 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:33:38 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:33:38 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:33:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:33:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:33:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:33:38 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:33:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:33:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:33:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:33:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:33:38 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:33:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:33:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:33:38 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:33:38 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:33:38 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:33:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:33:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:33:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:33:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:33:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:33:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:33:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:33:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:33:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:33:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:33:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:33:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:33:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:33:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:33:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:33:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:33:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:33:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:33:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:33:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:33:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:33:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:33:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:33:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:33:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:33:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:33:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:33:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:33:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:33:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:33:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:33:38 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:33:39 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:33:39 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:33:39 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:33:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:39 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:33:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:39 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:33:39 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:33:39 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:33:39 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:33:39 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:33:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:40 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:33:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:33:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:33:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:33:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:33:40 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:33:40 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:33:40 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:33:40 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:33:40 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:33:40 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:33:40 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:33:40 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=399 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:33:40 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=399 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:33:40 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=399 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:33:40 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=399 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:33:40 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=399 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:33:40 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=399 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:33:40 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=399 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:33:45 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:33:45 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:33:45 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:33:45 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:33:45 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:33:45 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:33:45 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:33:45 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:33:45 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:33:45 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:33:45 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:33:45 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:33:45 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:33:45 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:33:45 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:33:45 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:33:45 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:33:45 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:33:45 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:33:45 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:33:45 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:33:45 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:33:45 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:33:45 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:33:45 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:33:45 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:33:45 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:33:45 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:33:45 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:33:45 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:33:45 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:33:45 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:33:45 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:33:45 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:33:45 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:33:45 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:33:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:33:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:33:45 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:33:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:33:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:33:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:33:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:33:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:33:45 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:33:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:33:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:33:45 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:33:45 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:33:45 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:33:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:33:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:33:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:33:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:33:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:33:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:33:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:33:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:33:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:33:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:33:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:33:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:33:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:33:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:33:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:33:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:33:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:33:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:33:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:33:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:33:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:33:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:33:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:33:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:33:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:33:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:33:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:33:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:33:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:33:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:33:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:33:45 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:33:46 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:33:46 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:33:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:46 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:33:46 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:33:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:33:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:46 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:33:46 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:33:46 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:33:46 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:33:46 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:33:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:46 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:33:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:47 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:33:47 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:33:47 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:33:47 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:33:47 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:33:47 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:33:47 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:33:47 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:33:47 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=397 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:33:47 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:33:47 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:33:47 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:33:47 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=397 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:33:47 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=397 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:33:47 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=397 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:33:47 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=397 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:33:47 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=397 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:33:52 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:33:52 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:33:52 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:33:52 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:33:52 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:33:52 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:33:52 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:33:52 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:33:52 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:33:52 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:33:52 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:33:52 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:33:52 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:33:52 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:33:52 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:33:52 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:33:52 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:33:52 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:33:52 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:33:52 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:33:52 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:33:52 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:33:52 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:33:52 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:33:52 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:33:52 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:33:52 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:33:52 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:33:52 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:33:52 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:33:52 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:33:52 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:33:52 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:33:52 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:33:52 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:33:52 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:33:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:33:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:33:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:33:52 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:33:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:33:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:33:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:33:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:33:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:33:52 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:33:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:33:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:33:52 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:33:52 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:33:52 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:33:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:33:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:33:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:33:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:33:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:33:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:33:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:33:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:33:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:33:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:33:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:33:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:33:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:33:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:33:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:33:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:33:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:33:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:33:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:33:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:33:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:33:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:33:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:33:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:33:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:33:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:33:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:33:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:33:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:33:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:33:52 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:33:52 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:33:52 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:33:52 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:33:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:52 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:33:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:33:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:53 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:33:53 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:33:53 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:33:53 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:33:53 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:33:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:53 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:33:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:54 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:33:54 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:33:54 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:33:54 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:33:54 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:33:54 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:33:54 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:33:54 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:33:54 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:33:54 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=406 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:33:54 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:33:54 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:33:54 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=406 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:33:54 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=406 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:33:54 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=406 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:33:54 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=406 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:33:54 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=406 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:33:54 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=407 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:33:54 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=407 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:33:54 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=407 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:33:54 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=407 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:33:54 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=407 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:33:54 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=407 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:33:54 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=407 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:33:54 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=407 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:33:54 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=408 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:33:54 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=408 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:33:54 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=408 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:33:54 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=408 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:33:54 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=408 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:33:54 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=408 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:33:54 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=408 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:33:54 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=408 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:33:59 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:33:59 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:33:59 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:33:59 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:33:59 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:33:59 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:33:59 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:33:59 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:33:59 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:33:59 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:33:59 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:33:59 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:33:59 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:33:59 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:33:59 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:33:59 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:33:59 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:33:59 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:33:59 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:33:59 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:33:59 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:33:59 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:33:59 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:33:59 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:33:59 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:33:59 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:33:59 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:33:59 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:33:59 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:33:59 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:33:59 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:33:59 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:33:59 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:33:59 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:33:59 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:33:59 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:33:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:33:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:33:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:33:59 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:33:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:33:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:33:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:33:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:33:59 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:33:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:33:59 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:33:59 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:33:59 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:33:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:33:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:33:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:33:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:33:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:33:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:33:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:33:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:33:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:33:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:33:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:33:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:33:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:33:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:33:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:33:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:33:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:33:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:33:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:33:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:33:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:33:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:33:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:33:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:33:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:33:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:33:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:33:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:33:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:33:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:33:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:33:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:33:59 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:33:59 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:33:59 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:33:59 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:33:59 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:33:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:33:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:33:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:00 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:34:00 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:34:00 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:34:00 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:34:00 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:34:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:00 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:34:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:34:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:34:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:34:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:34:01 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:34:01 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:34:01 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:34:01 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:34:01 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:34:01 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:34:01 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:34:06 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:34:06 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:34:06 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:34:06 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:34:06 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:34:06 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:34:06 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:34:06 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:34:06 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:34:06 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:34:06 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:34:06 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:34:06 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:34:06 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:34:06 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:34:06 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:34:06 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:34:06 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:34:06 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:34:06 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:34:06 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:34:06 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:34:06 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:34:06 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:34:06 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:34:06 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:34:06 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:34:06 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:34:06 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:34:06 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:34:06 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:34:06 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:34:06 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:34:06 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:34:06 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:34:06 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:34:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:34:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:34:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:34:06 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:34:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:34:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:34:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:34:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:34:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:34:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:34:06 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:34:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:34:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:34:06 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:34:06 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:34:06 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:34:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:34:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:34:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:34:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:34:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:34:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:34:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:34:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:34:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:34:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:34:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:34:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:34:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:34:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:34:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:34:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:34:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:34:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:34:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:34:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:34:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:34:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:34:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:34:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:34:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:34:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:34:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:34:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:34:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:34:06 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:34:06 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:34:06 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:34:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:06 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:34:06 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:34:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:06 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:34:06 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:34:06 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:34:06 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:34:06 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:34:06 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:34:06 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:34:06 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:34:06 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:34:06 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:34:06 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:34:06 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=133 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:34:06 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=133 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:34:06 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=133 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:34:06 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=133 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:34:06 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=133 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:34:06 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=133 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:34:06 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=133 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:34:11 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:34:11 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:34:11 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:34:11 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:34:11 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:34:11 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:34:11 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:34:11 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:34:11 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:34:11 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:34:11 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:34:11 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:34:11 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:34:11 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:34:11 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:34:11 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:34:11 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:34:11 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:34:11 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:34:11 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:34:11 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:34:11 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:34:11 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:34:11 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:34:11 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:34:11 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:34:11 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:34:11 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:34:11 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:34:11 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:34:11 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:34:11 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:34:11 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:34:11 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:34:11 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:34:11 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:34:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:34:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:34:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:34:11 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:34:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:34:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:34:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:34:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:34:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:34:11 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:34:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:34:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:34:11 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:34:11 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:34:11 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:34:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:34:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:34:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:34:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:34:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:34:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:34:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:34:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:34:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:34:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:34:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:34:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:34:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:34:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:34:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:34:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:34:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:34:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:34:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:34:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:34:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:34:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:34:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:34:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:34:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:34:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:34:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:34:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:34:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:34:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:34:11 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:34:12 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:34:12 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:34:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:12 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:34:12 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:34:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:34:12 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:34:12 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:34:12 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:34:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:34:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:34:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:34:12 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:34:12 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:34:12 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:34:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:34:12 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=140 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:34:12 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=140 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:34:12 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=140 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:34:12 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=140 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:34:12 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=140 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:34:12 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=140 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:34:17 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:34:17 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:34:17 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:34:17 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:34:17 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:34:17 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:34:17 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:34:17 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:34:17 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:34:17 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:34:17 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:34:17 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:34:17 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:34:17 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:34:17 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:34:17 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:34:17 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:34:17 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:34:17 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:34:17 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:34:17 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:34:17 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:34:17 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:34:17 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:34:17 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:34:17 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:34:17 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:34:17 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:34:17 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:34:17 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:34:17 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:34:17 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:34:17 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:34:17 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:34:17 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:34:17 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:34:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:34:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:34:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:34:17 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:34:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:34:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:34:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:34:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:34:17 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:34:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:34:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:34:17 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:34:17 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:34:17 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:34:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:34:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:34:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:34:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:34:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:34:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:34:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:34:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:34:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:34:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:34:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:34:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:34:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:34:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:34:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:34:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:34:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:34:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:34:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:34:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:34:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:34:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:34:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:34:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:34:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:34:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:34:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:34:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:34:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:34:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:34:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:34:17 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:34:18 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:34:18 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:34:18 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:34:18 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:34:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:18 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:34:18 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:34:18 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:34:18 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:34:18 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:34:18 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:34:18 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:34:18 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:34:18 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:34:18 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:34:18 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:34:18 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=138 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:34:18 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=138 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:34:18 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=138 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:34:18 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=138 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:34:18 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=138 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:34:18 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=138 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:34:18 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=138 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:34:23 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:34:23 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:34:23 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:34:23 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:34:23 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:34:23 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:34:23 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:34:23 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:34:23 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:34:23 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:34:23 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:34:23 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:34:23 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:34:23 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:34:23 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:34:23 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:34:23 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:34:23 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:34:23 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:34:23 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:34:23 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:34:23 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:34:23 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:34:23 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:34:23 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:34:23 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:34:23 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:34:23 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:34:23 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:34:23 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:34:23 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:34:23 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:34:23 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:34:23 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:34:23 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:34:23 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:34:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:34:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:34:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:34:23 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:34:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:34:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:34:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:34:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:34:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:34:23 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:34:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:34:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:34:23 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:34:23 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:34:23 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:34:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:34:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:34:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:34:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:34:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:34:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:34:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:34:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:34:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:34:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:34:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:34:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:34:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:34:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:34:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:34:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:34:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:34:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:34:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:34:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:34:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:34:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:34:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:34:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:34:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:34:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:34:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:34:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:34:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:34:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:34:23 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:34:23 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:34:23 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:34:23 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:34:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:23 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:34:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:23 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:34:23 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:34:23 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:34:23 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:34:23 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:34:23 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:34:23 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:34:23 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:34:23 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:34:23 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:34:23 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:34:28 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:34:28 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:34:28 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:34:28 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:34:28 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:34:28 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:34:28 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:34:28 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:34:28 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:34:28 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:34:28 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:34:28 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:34:28 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:34:28 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:34:28 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:34:28 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:34:28 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:34:28 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:34:28 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:34:28 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:34:28 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:34:28 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:34:28 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:34:28 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:34:28 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:34:28 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:34:28 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:34:28 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:34:28 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:34:28 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:34:28 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:34:28 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:34:28 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:34:28 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:34:28 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:34:28 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:34:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:34:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:34:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:34:28 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:34:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:34:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:34:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:34:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:34:28 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:34:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:34:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:34:28 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:34:28 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:34:28 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:34:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:34:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:34:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:34:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:34:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:34:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:34:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:34:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:34:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:34:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:34:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:34:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:34:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:34:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:34:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:34:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:34:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:34:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:34:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:34:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:34:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:34:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:34:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:34:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:34:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:34:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:34:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:34:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:34:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:34:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:34:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:34:28 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:34:29 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:34:29 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:34:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:29 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:34:29 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:34:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:34:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:34:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:34:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:34:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:34:29 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:34:29 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:34:29 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:34:29 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:34:29 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=134 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:34:29 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:34:29 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:34:29 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:34:29 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=134 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:34:29 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=134 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:34:34 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:34:34 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:34:34 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:34:34 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:34:34 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:34:34 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:34:34 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:34:34 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:34:34 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:34:34 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:34:34 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:34:34 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:34:34 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:34:34 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:34:34 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:34:34 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:34:34 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:34:34 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:34:34 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:34:34 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:34:34 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:34:34 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:34:34 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:34:34 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:34:34 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:34:34 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:34:34 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:34:34 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:34:34 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:34:34 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:34:34 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:34:34 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:34:34 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:34:34 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:34:34 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:34:34 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:34:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:34:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:34:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:34:34 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:34:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:34:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:34:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:34:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:34:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:34:34 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:34:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:34:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:34:34 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:34:34 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:34:34 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:34:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:34:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:34:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:34:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:34:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:34:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:34:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:34:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:34:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:34:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:34:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:34:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:34:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:34:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:34:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:34:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:34:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:34:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:34:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:34:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:34:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:34:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:34:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:34:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:34:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:34:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:34:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:34:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:34:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:34:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:34:34 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:34:35 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:34:35 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:34:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:35 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:34:35 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:34:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:34:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:35 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:34:35 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:34:35 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:34:35 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:34:35 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:34:35 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:34:35 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:34:35 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:34:35 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=140 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:34:35 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:34:35 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:34:35 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:34:40 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:34:40 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:34:40 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:34:40 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:34:40 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:34:40 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:34:40 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:34:40 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:34:40 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:34:40 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:34:40 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:34:40 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:34:40 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:34:40 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:34:40 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:34:40 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:34:40 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:34:40 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:34:40 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:34:40 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:34:40 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:34:40 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:34:40 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:34:40 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:34:40 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:34:40 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:34:40 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:34:40 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:34:40 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:34:40 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:34:40 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:34:40 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:34:40 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:34:40 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:34:40 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:34:40 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:34:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:34:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:34:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:34:40 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:34:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:34:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:34:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:34:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:34:40 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:34:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:34:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:34:40 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:34:40 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:34:40 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:34:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:34:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:34:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:34:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:34:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:34:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:34:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:34:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:34:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:34:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:34:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:34:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:34:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:34:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:34:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:34:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:34:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:34:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:34:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:34:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:34:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:34:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:34:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:34:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:34:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:34:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:34:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:34:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:34:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:34:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:34:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:34:40 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:34:40 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:34:40 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:34:40 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:34:40 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:34:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:34:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:34:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:34:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:34:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:34:40 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:34:40 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:34:40 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:34:40 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:34:40 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:34:40 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:34:40 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:34:45 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:34:45 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:34:45 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:34:45 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:34:46 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:34:46 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:34:46 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:34:46 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:34:46 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:34:46 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:34:46 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:34:46 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:34:46 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:34:46 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:34:46 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:34:46 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:34:46 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:34:46 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:34:46 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:34:46 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:34:46 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:34:46 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:34:46 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:34:46 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:34:46 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:34:46 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:34:46 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:34:46 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:34:46 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:34:46 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:34:46 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:34:46 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:34:46 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:34:46 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:34:46 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:34:46 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:34:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:34:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:34:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:34:46 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:34:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:34:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:34:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:34:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:34:46 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:34:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:34:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:34:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:34:46 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:34:46 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:34:46 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:34:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:34:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:34:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:34:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:34:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:34:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:34:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:34:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:34:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:34:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:34:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:34:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:34:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:34:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:34:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:34:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:34:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:34:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:34:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:34:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:34:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:34:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:34:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:34:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:34:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:34:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:34:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:34:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:34:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:34:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:34:46 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:34:46 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:34:46 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:34:46 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:34:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:46 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:34:46 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:34:46 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:34:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:34:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:34:46 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:34:46 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:34:46 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:34:46 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:34:46 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:34:47 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:34:47 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:34:47 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:34:47 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:34:47 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:34:47 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:34:48 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:34:48 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:34:48 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:34:48 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:34:48 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 04:34:48 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 04:34:49 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:34:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:34:49 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:34:49 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:34:49 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 04:34:49 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 04:34:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:34:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:34:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:34:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:34:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:34:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:34:50 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:34:50 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:34:50 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:34:50 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:34:50 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:34:50 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:34:50 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:34:55 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:34:55 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:34:55 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:34:55 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:34:55 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:34:55 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:34:55 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:34:55 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:34:55 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:34:55 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:34:55 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:34:55 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:34:55 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:34:55 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:34:55 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:34:55 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:34:55 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:34:55 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:34:55 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:34:55 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:34:55 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:34:55 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:34:55 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:34:55 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:34:55 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:34:55 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:34:55 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:34:55 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:34:55 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:34:55 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:34:55 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:34:55 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:34:55 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:34:55 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:34:55 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:34:55 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:34:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:34:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:34:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:34:55 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:34:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:34:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:34:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:34:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:34:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:34:55 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:34:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:34:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:34:55 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:34:55 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:34:55 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:34:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:34:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:34:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:34:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:34:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:34:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:34:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:34:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:34:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:34:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:34:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:34:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:34:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:34:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:34:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:34:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:34:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:34:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:34:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:34:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:34:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:34:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:34:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:34:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:34:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:34:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:34:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:34:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:34:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:34:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:34:55 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:34:55 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:34:55 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:34:55 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:34:55 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:34:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:55 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:34:55 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:34:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:34:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:34:55 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:34:55 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:34:55 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:34:55 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:34:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD HANDOVER
2025-04-27 04:34:55 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:34:55 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:34:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:34:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:34:56 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:34:56 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:34:56 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:34:56 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:34:56 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:34:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:34:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:34:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:34:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:34:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:34:56 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:34:56 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:34:56 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:34:56 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:34:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:34:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:34:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:34:56 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:34:56 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:34:56 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:34:56 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:34:56 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:34:56 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:34:56 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:34:56 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:34:56 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:34:56 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:34:56 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:34:56 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=237 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:34:56 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=237 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:34:56 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=237 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:34:56 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=237 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:34:56 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=237 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:34:56 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=237 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:34:56 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=238 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:34:56 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=238 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:34:56 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=238 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:34:56 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=238 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:34:56 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=238 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:34:56 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=238 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:34:56 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=238 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:34:56 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=238 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:34:56 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=239 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:34:56 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=239 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:34:56 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=239 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:34:56 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=239 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:34:56 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=239 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:34:56 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=239 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:34:56 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=239 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:34:56 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=239 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:35:01 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:35:01 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:35:01 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:35:01 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:35:01 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:35:01 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:35:01 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:35:01 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:35:01 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:35:01 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:35:01 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:35:01 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:35:01 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:35:01 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:35:01 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:35:01 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:35:01 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:35:01 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:35:01 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:35:01 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:35:01 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:35:01 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:35:01 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:35:01 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:35:01 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:35:01 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:35:01 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:35:01 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:35:01 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:35:01 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:35:01 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:35:01 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:35:01 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:35:01 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:35:01 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:35:01 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:35:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:35:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:35:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:35:01 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:35:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:35:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:35:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:35:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:35:01 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:35:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:35:01 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:35:01 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:35:01 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:35:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:35:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:35:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:35:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:35:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:35:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:35:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:35:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:35:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:35:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:35:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:35:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:35:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:35:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:35:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:35:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:35:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:35:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:35:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:35:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:35:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:35:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:35:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:35:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:35:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:35:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:35:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:35:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:35:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:35:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:35:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:35:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:35:01 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:35:01 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:35:01 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:35:01 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:35:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:35:01 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:35:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:35:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:35:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:35:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:35:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:35:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:35:01 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:35:01 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:35:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD HANDOVER
2025-04-27 04:35:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:35:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:35:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:35:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:35:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:35:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:35:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:35:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:35:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:35:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:35:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:35:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:35:01 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:35:01 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:35:02 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:35:02 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:35:02 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:35:02 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:35:02 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:35:02 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:35:03 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:35:03 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:35:03 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:35:03 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:35:03 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:35:03 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 04:35:04 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 04:35:04 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:35:04 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:35:04 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:35:04 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:35:04 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 04:35:05 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 04:35:05 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:35:05 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:35:05 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:35:05 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:35:05 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 04:35:05 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 04:35:06 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:35:06 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:35:06 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:35:06 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:35:06 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 04:35:06 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 04:35:07 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 04:35:07 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 04:35:08 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 04:35:08 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 04:35:09 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 04:35:09 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 04:35:10 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 04:35:10 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 04:35:11 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 04:35:11 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 04:35:12 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-27 04:35:12 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-27 04:35:13 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-27 04:35:13 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-27 04:35:14 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-27 04:35:14 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-27 04:35:15 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-27 04:35:15 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-27 04:35:16 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-27 04:35:16 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-27 04:35:16 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-27 04:35:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:35:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:35:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:35:17 [WARNING] transceiver.py:250 (MS@172.18.127.22:6700) RX TRXD message (fn=3432 tn=4 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:35:17 [WARNING] transceiver.py:250 (MS@172.18.127.22:6700) RX TRXD message (fn=3432 tn=5 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:35:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:35:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:35:17 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:35:17 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:35:17 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:35:17 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:35:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:35:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:35:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:35:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:35:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:35:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:35:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:35:17 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:35:17 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:35:17 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:35:17 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:35:17 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:35:17 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:35:17 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:35:22 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:35:22 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:35:22 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:35:22 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:35:22 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:35:22 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:35:22 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:35:22 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:35:22 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:35:22 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:35:22 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:35:22 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:35:22 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:35:22 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:35:22 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:35:22 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:35:22 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:35:22 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:35:22 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:35:22 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:35:22 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:35:22 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:35:22 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:35:22 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:35:22 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:35:22 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:35:22 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:35:22 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:35:22 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:35:22 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:35:22 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:35:22 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:35:22 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:35:22 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:35:22 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:35:22 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:35:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:35:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:35:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:35:22 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:35:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:35:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:35:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:35:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:35:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:35:22 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:35:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:35:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:35:22 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:35:22 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:35:22 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:35:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:35:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:35:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:35:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:35:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:35:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:35:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:35:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:35:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:35:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:35:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:35:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:35:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:35:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:35:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:35:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:35:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:35:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:35:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:35:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:35:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:35:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:35:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:35:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:35:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:35:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:35:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:35:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:35:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:35:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:35:22 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:35:22 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:35:22 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:35:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:35:22 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:35:22 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:35:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:35:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:35:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:35:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:35:22 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:35:22 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:35:22 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:35:22 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:35:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD HANDOVER
2025-04-27 04:35:22 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:35:22 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:35:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:35:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:35:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:35:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD HANDOVER
2025-04-27 04:35:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:35:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:35:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:35:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:35:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:35:23 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:35:23 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:35:23 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:35:23 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:35:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:35:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:35:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:35:23 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:35:23 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:35:23 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:35:23 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:35:23 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:35:23 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:35:23 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:35:23 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:35:23 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:35:23 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:35:23 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:35:28 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:35:28 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:35:28 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:35:28 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:35:28 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:35:28 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:35:28 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:35:28 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:35:28 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:35:28 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:35:28 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:35:28 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:35:28 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:35:28 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:35:28 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:35:28 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:35:28 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:35:28 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:35:28 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:35:28 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:35:28 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:35:28 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:35:28 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:35:28 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:35:28 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:35:28 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:35:28 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:35:28 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:35:28 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:35:28 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:35:28 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:35:28 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:35:28 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:35:28 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:35:28 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:35:28 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:35:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:35:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:35:28 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:35:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:35:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:35:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:35:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:35:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:35:28 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:35:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:35:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:35:28 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:35:28 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:35:28 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:35:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:35:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:35:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:35:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:35:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:35:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:35:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:35:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:35:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:35:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:35:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:35:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:35:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:35:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:35:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:35:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:35:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:35:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:35:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:35:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:35:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:35:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:35:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:35:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:35:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:35:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:35:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:35:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:35:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:35:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:35:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:35:28 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:35:28 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:35:28 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:35:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:35:28 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:35:28 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:35:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:35:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:35:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:35:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:35:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:35:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:35:28 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:35:28 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:35:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD HANDOVER
2025-04-27 04:35:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:35:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:35:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:35:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:35:29 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:35:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:35:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:35:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:35:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:35:29 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:35:30 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:35:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:35:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:35:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:35:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:35:30 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 04:35:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:35:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:35:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:35:30 [WARNING] transceiver.py:250 (MS@172.18.127.22:6700) RX TRXD message (fn=558 tn=2 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:35:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:35:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:35:30 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:35:30 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:35:30 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:35:30 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:35:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:35:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:35:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:35:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:35:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:35:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:35:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:35:30 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:35:30 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:35:30 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:35:30 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:35:30 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:35:30 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:35:30 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:35:30 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=565 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:35:30 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=565 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:35:30 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=565 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:35:30 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=565 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:35:30 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=565 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:35:30 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=565 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:35:30 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=565 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:35:30 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=565 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:35:35 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:35:35 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:35:35 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:35:35 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:35:35 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:35:35 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:35:35 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:35:35 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:35:35 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:35:35 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:35:35 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:35:35 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:35:35 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:35:35 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:35:35 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:35:35 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:35:35 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:35:35 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:35:35 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:35:35 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:35:35 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:35:35 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:35:35 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:35:35 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:35:35 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:35:35 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:35:35 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:35:35 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:35:35 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:35:35 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:35:35 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:35:35 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:35:35 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:35:35 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:35:35 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:35:35 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:35:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:35:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:35:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:35:35 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:35:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:35:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:35:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:35:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:35:35 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:35:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:35:35 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:35:35 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:35:35 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:35:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:35:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:35:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:35:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:35:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:35:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:35:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:35:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:35:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:35:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:35:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:35:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:35:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:35:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:35:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:35:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:35:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:35:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:35:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:35:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:35:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:35:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:35:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:35:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:35:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:35:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:35:35 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:35:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:35:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:35:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:35:35 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:35:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:35:35 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:35:35 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:35:35 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:35:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:35:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:35:42 [INFO] transceiver.py:125 Init transceiver 'BTS@172.18.127.20:5700'
2025-04-27 04:35:42 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:5702 <-> R:172.18.127.20:5802)
2025-04-27 04:35:42 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:5701 <-> R:172.18.127.20:5801)
2025-04-27 04:35:42 [INFO] transceiver.py:125 Init transceiver 'MS@172.18.127.22:6700'
2025-04-27 04:35:42 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:6702 <-> R:172.18.127.22:6802)
2025-04-27 04:35:42 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:6701 <-> R:172.18.127.22:6801)
2025-04-27 04:35:42 [INFO] transceiver.py:125 Init transceiver 'TRX1@172.18.127.20:5700/1'
2025-04-27 04:35:42 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:5704 <-> R:172.18.127.20:5804)
2025-04-27 04:35:42 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:5703 <-> R:172.18.127.20:5803)
2025-04-27 04:35:42 [INFO] transceiver.py:125 Init transceiver 'TRX2@172.18.127.20:5700/2'
2025-04-27 04:35:42 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:5706 <-> R:172.18.127.20:5806)
2025-04-27 04:35:42 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:5705 <-> R:172.18.127.20:5805)
2025-04-27 04:35:42 [INFO] transceiver.py:125 Init transceiver 'TRX3@172.18.127.20:5700/3'
2025-04-27 04:35:42 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:5708 <-> R:172.18.127.20:5808)
2025-04-27 04:35:42 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:5707 <-> R:172.18.127.20:5807)
2025-04-27 04:35:42 [INFO] fake_trx.py:423 Init complete
2025-04-27 04:35:43 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:35:43 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:35:43 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:35:43 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:35:43 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:35:43 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:35:55 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:35:55 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:35:55 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:35:55 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:36:00 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:36:00 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:36:00 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:36:00 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:36:00 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:36:00 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:36:00 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:36:00 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:36:00 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:36:00 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:36:05 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:36:05 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:36:05 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:36:05 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:36:05 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:36:05 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:36:05 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:36:05 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:36:05 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:36:05 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:36:10 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:36:10 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:36:10 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:36:10 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:36:10 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:36:10 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:36:10 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:36:10 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:36:10 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:36:10 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:36:15 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:36:15 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:36:15 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:36:15 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:36:15 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:36:15 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:36:15 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:36:15 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:36:15 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:36:15 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:36:20 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:36:20 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:36:20 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:36:20 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:36:20 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:36:20 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:36:20 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:36:20 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:36:20 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:36:20 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:36:25 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:36:25 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:36:25 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:36:25 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:36:25 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:36:25 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:36:25 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:36:25 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:36:25 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:36:25 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:36:30 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:36:30 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:36:30 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:36:30 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:36:30 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:36:30 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:36:30 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:36:30 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:36:30 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:36:30 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:36:35 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:36:35 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:36:35 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:36:35 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:36:35 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:36:35 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:36:35 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:36:35 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:36:35 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:36:35 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:36:40 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:36:40 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:36:40 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:36:40 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:36:40 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:36:40 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:36:40 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:36:40 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:36:40 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:36:40 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:36:45 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:36:45 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:36:45 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:36:45 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:36:45 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:36:45 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:36:45 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:36:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:36:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:36:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:36:45 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:36:45 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:36:45 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:36:45 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:36:45 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:36:45 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:36:45 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:36:45 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:36:45 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:36:45 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:36:45 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 0 -> 1
2025-04-27 04:36:45 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:36:45 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 0 -> 1
2025-04-27 04:36:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:36:45 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:36:45 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 0 -> 1
2025-04-27 04:36:45 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:36:45 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:36:45 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 0 -> 1
2025-04-27 04:36:45 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:36:45 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:36:45 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:36:45 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:36:50 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:36:50 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:36:50 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:36:50 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:36:50 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:36:50 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:36:50 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:36:50 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:36:50 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:36:50 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:36:55 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:36:55 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:36:55 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:36:55 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:36:55 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:36:55 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:36:55 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:36:55 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:36:55 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:36:55 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:36:55 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:36:55 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:36:55 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:36:55 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:37:00 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:37:00 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:37:00 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:37:00 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:37:00 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:37:00 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:37:00 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:37:00 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:37:00 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:37:00 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:37:05 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:37:05 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:37:05 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:37:05 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:37:05 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:37:05 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:37:05 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:37:05 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:37:05 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:37:05 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:37:10 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:37:10 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:37:10 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:37:10 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:37:10 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:37:10 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:37:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:37:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:37:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:37:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:37:17 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:37:17 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:37:17 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:37:17 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:37:17 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:37:17 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:37:17 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:37:17 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:37:17 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:37:17 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:37:24 [INFO] transceiver.py:125 Init transceiver 'BTS@172.18.127.20:5700'
2025-04-27 04:37:24 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:5702 <-> R:172.18.127.20:5802)
2025-04-27 04:37:24 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:5701 <-> R:172.18.127.20:5801)
2025-04-27 04:37:24 [INFO] transceiver.py:125 Init transceiver 'MS@172.18.127.22:6700'
2025-04-27 04:37:24 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:6702 <-> R:172.18.127.22:6802)
2025-04-27 04:37:24 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:6701 <-> R:172.18.127.22:6801)
2025-04-27 04:37:24 [INFO] transceiver.py:125 Init transceiver 'TRX1@172.18.127.20:5700/1'
2025-04-27 04:37:24 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:5704 <-> R:172.18.127.20:5804)
2025-04-27 04:37:24 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:5703 <-> R:172.18.127.20:5803)
2025-04-27 04:37:24 [INFO] transceiver.py:125 Init transceiver 'TRX2@172.18.127.20:5700/2'
2025-04-27 04:37:24 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:5706 <-> R:172.18.127.20:5806)
2025-04-27 04:37:24 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:5705 <-> R:172.18.127.20:5805)
2025-04-27 04:37:24 [INFO] transceiver.py:125 Init transceiver 'TRX3@172.18.127.20:5700/3'
2025-04-27 04:37:24 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:5708 <-> R:172.18.127.20:5808)
2025-04-27 04:37:24 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:5707 <-> R:172.18.127.20:5807)
2025-04-27 04:37:24 [INFO] fake_trx.py:423 Init complete
2025-04-27 04:37:24 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:37:24 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:37:24 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:37:24 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:37:24 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:37:24 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:37:28 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:37:28 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:37:28 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:37:28 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:37:28 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 0 -> 1
2025-04-27 04:37:28 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:37:28 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:37:28 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:37:28 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:37:28 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:37:28 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:37:28 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:37:28 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 0 -> 1
2025-04-27 04:37:28 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:37:28 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:37:28 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:37:28 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:37:28 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:37:28 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:37:28 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:37:28 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 0 -> 1
2025-04-27 04:37:28 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:37:28 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:37:28 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:37:28 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:37:28 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:37:28 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:37:28 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:37:28 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 0 -> 1
2025-04-27 04:37:28 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:37:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:37:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:37:28 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:37:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:37:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:37:28 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:37:28 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:37:28 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:37:28 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:37:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:37:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:37:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:37:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:37:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:37:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:37:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:37:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:37:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:37:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:37:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:37:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:37:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:37:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:37:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:37:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:37:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:37:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:37:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:37:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:37:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:37:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:37:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:37:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:37:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:37:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:37:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:37:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:37:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:37:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:37:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:37:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:37:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:37:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:37:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:37:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:37:28 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:37:29 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:37:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:29 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:37:29 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:37:29 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:37:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:37:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:37:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:37:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:37:29 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:37:29 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:37:29 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:37:29 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:37:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:29 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:37:29 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:37:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:37:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:37:29 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:37:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:37:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:37:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:37:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:37:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:37:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:37:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:37:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:37:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:37:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:37:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:37:29 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:37:29 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:37:29 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:37:29 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:37:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:29 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:37:29 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:37:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:37:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:37:30 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:37:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:37:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:37:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:37:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:37:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:37:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:37:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:37:30 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:37:30 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:37:30 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:37:30 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:37:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:30 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:37:30 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:37:30 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:37:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:37:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:37:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:37:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:37:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:37:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:37:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:37:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:37:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:37:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:37:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:37:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:37:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:37:31 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:37:31 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:37:31 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:37:31 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:37:31 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 04:37:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:31 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:37:31 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:37:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:37:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:37:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:37:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:37:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:37:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:37:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:37:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:37:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:37:31 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:37:31 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:37:31 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:37:31 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:37:31 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 04:37:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:37:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:37:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:37:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:37:31 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:37:31 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:37:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:37:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:37:32 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 04:37:32 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 04:37:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:37:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:37:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:37:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:37:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:37:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:37:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:37:32 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:37:32 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:37:32 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:37:32 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:37:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:32 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:37:32 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:37:32 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:37:32 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:37:32 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 04:37:32 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2025-04-27 04:37:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:37:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:37:32 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 04:37:33 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 04:37:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:37:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:37:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:37:33 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 04:37:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:37:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:37:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:37:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:37:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:37:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:37:33 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:37:33 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:37:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:33 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 04:37:33 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=3, maio=3, ma_len=4
2025-04-27 04:37:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:37:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:37:33 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 04:37:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:37:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:37:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:37:34 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 04:37:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:37:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:37:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:37:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:37:34 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:37:34 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:37:34 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:37:34 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:37:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:37:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:34 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 04:37:34 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:37:34 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:37:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:37:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:37:34 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 04:37:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:37:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:37:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:37:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:37:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:37:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:37:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:37:35 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:37:35 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:37:35 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:37:35 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:37:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:35 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 04:37:35 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:37:35 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:37:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:37:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:37:35 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 04:37:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:37:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:36 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:37:36 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:37:36 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:37:36 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:37:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:37:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:37:36 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:37:36 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:37:36 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:37:36 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:37:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:37:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:36 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 04:37:36 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:37:36 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:37:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:37:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:37:36 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 04:37:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:37:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:37:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:37:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:37:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:37:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:37:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:37:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:37:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:37:37 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:37:37 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:37:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:37 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 04:37:37 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 04:37:37 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-27 04:37:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:37:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:37:37 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 04:37:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:37:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:37:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:37:38 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 04:37:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:37:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:37:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:37:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:37:38 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:37:38 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:37:38 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:37:38 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:37:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:38 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 04:37:38 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 04:37:38 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-27 04:37:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:37:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:37:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:37:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:37:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:37:38 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 04:37:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:37:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:37:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:37:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:37:38 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:37:38 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:37:38 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:37:38 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:37:38 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 04:37:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:38 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 04:37:38 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-27 04:37:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:37:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:37:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:37:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:37:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:37:38 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 04:37:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:37:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:37:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:37:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:37:38 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:37:38 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:37:38 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:37:38 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:37:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:39 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 04:37:39 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-27 04:37:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:37:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:37:39 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 04:37:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:37:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:37:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:37:39 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 04:37:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:37:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:37:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:37:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:37:39 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:37:39 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:37:39 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:37:39 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:37:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:39 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 04:37:39 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-27 04:37:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:37:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:37:39 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-27 04:37:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:37:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:37:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:37:39 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 04:37:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:37:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:37:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:37:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:37:39 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:37:39 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:37:39 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:37:39 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:37:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:39 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 04:37:39 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-27 04:37:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:37:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:37:40 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-27 04:37:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:37:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:37:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:37:40 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 04:37:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:37:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:37:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:37:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:37:40 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:37:40 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:37:40 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:37:40 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:37:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:40 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 04:37:40 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-27 04:37:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:37:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:37:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:37:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:37:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:37:40 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 04:37:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:37:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:37:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:37:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:37:40 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:37:40 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:37:40 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:37:40 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:37:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:40 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-27 04:37:40 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 04:37:40 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-27 04:37:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:37:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:37:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:37:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:37:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:37:41 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 04:37:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:37:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:37:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:37:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:37:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:37:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:37:41 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:37:41 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:37:41 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-27 04:37:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:41 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 04:37:41 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-27 04:37:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:37:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:37:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:37:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:37:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:37:41 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 04:37:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:37:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:37:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:37:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:37:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:37:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:37:41 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:37:41 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:37:41 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-27 04:37:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:41 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 04:37:41 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-27 04:37:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:37:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:37:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:37:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:37:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:37:42 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 04:37:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:37:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:37:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:37:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:37:42 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:37:42 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:37:42 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:37:42 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:37:42 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:37:42 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:37:42 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:37:42 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2857 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:37:42 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2857 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:37:42 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2857 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:37:42 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2857 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:37:42 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2857 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:37:42 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2857 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:37:42 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2858 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:37:42 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2858 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:37:42 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2858 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:37:42 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2858 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:37:42 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2858 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:37:42 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2858 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:37:42 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2858 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:37:42 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2858 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:37:47 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:37:47 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:37:47 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:37:47 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:37:47 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:37:47 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:37:47 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:37:47 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:37:47 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:37:47 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:37:47 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:37:47 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:37:47 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:37:47 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:37:47 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:37:47 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:37:47 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:37:47 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:37:47 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:37:47 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:37:47 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:37:47 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:37:47 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:37:47 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:37:47 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:37:47 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:37:47 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:37:47 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:37:47 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:37:47 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:37:47 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:37:47 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:37:47 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:37:47 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:37:47 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:37:47 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:37:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:37:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:37:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:37:47 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:37:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:37:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:37:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:37:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:37:47 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:37:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:37:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:37:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:37:47 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:37:47 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:37:47 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:37:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:37:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:37:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:37:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:37:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:37:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:37:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:37:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:37:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:37:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:37:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:37:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:37:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:37:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:37:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:37:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:37:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:37:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:37:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:37:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:37:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:37:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:37:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:37:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:37:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:37:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:37:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:37:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:37:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:37:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:37:47 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:37:47 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:37:47 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:37:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:47 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:37:47 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:37:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:37:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:37:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:37:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
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2025-04-27 04:37:48 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:37:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
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2025-04-27 04:37:48 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:37:48 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:37:48 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:37:48 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:37:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
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2025-04-27 04:37:48 [DEBUG] clck_gen.py:102 IND CLOCK 306
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2025-04-27 04:37:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
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2025-04-27 04:37:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:48 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:37:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:37:49 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:37:49 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:37:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:49 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:37:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:37:49 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:37:49 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:37:49 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:37:49 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:37:49 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:37:49 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:37:49 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:37:49 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:37:49 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=437 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:37:49 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:37:49 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:37:49 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=437 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:37:49 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=437 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:37:49 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=437 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:37:49 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=438 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:37:49 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=438 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:37:49 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=438 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:37:49 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=438 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:37:49 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=438 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:37:49 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=438 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:37:49 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=438 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:37:49 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=438 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:37:54 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:37:54 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:37:54 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:37:54 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:37:54 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:37:54 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:37:54 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:37:54 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:37:54 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:37:54 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:37:54 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:37:54 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:37:54 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:37:54 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:37:54 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:37:54 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:37:54 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:37:54 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:37:54 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:37:54 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:37:54 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:37:54 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:37:54 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:37:54 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:37:54 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:37:54 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:37:54 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:37:54 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:37:54 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:37:54 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:37:54 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:37:54 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:37:54 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:37:54 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:37:54 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:37:54 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:37:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:37:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:37:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:37:54 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:37:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:37:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:37:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:37:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:37:54 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:37:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:37:54 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:37:54 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:37:54 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:37:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:37:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:37:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:37:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:37:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:37:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:37:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:37:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:37:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:37:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:37:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:37:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:37:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:37:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:37:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:37:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:37:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:37:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:37:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:37:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:37:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:37:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:37:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:37:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:37:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:37:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:37:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:37:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:37:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:37:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:37:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:37:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:37:54 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:37:54 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:37:54 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:37:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:54 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:37:54 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:37:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:37:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:37:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:37:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:37:54 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:37:54 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:37:54 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:37:54 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:37:54 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:37:54 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:37:54 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:37:54 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:37:54 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:37:54 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:37:54 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:37:54 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=125 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:37:54 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=125 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:37:54 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=125 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:37:54 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=125 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:37:54 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=125 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:37:54 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=125 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:37:59 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:37:59 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:37:59 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:37:59 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:37:59 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:37:59 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:37:59 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:37:59 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:37:59 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:37:59 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:37:59 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:37:59 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:37:59 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:37:59 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:37:59 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:37:59 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:37:59 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:37:59 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:37:59 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:37:59 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:37:59 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:37:59 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:37:59 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:37:59 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:37:59 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:37:59 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:37:59 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:37:59 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:37:59 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:37:59 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:37:59 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:37:59 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:37:59 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:37:59 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:37:59 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:37:59 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:37:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:37:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:37:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:37:59 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:37:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:37:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:37:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:37:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:37:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:37:59 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:37:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:37:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:37:59 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:37:59 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:37:59 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:37:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:37:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:37:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:37:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:37:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:37:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:37:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:37:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:37:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:37:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:37:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:37:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:37:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:37:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:37:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:37:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:37:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:37:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:37:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:37:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:37:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:37:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:37:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:37:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:37:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:37:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:37:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:37:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:37:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:37:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:37:59 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:38:00 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:38:00 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:38:00 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:38:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:38:00 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:38:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:38:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:38:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:38:00 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:38:00 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:38:00 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:38:00 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:38:00 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:38:00 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:38:00 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:38:00 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:38:00 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:38:00 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=124 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:38:00 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:38:00 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:38:00 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=124 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:38:00 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=124 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:38:00 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=124 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:38:00 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=125 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:38:00 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=125 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:38:00 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=125 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:38:00 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=125 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:38:00 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=125 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:38:00 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=125 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:38:00 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=125 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:38:00 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=125 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:38:05 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:38:05 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:38:05 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:38:05 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:38:05 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:38:05 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:38:05 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:38:05 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:38:05 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:38:05 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:38:05 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:38:05 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:38:05 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:38:05 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:38:05 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:38:05 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:38:05 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:38:05 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:38:05 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:38:05 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:38:05 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:38:05 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:38:05 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:38:05 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:38:05 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:38:05 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:38:05 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:38:05 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:38:05 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:38:05 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:38:05 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:38:05 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:38:05 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:38:05 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:38:05 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:38:05 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:38:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:38:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:38:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:38:05 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:38:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:38:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:38:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:38:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:38:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:38:05 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:38:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:38:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:38:05 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:38:05 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:38:05 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:38:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:38:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:38:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:38:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:38:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:38:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:38:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:38:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:38:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:38:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:38:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:38:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:38:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:38:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:38:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:38:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:38:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:38:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:38:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:38:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:38:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:38:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:38:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:38:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:38:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:38:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:38:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:38:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:38:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:38:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:38:05 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:38:05 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:38:05 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:38:05 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:38:05 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:38:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:38:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:38:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:38:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:38:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:38:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:38:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:38:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:38:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:38:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:38:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:38:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:38:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:38:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:38:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:38:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:38:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:38:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:38:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:38:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:38:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:38:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:38:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:38:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:38:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:38:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:38:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:38:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:38:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:38:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:38:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:38:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:38:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:38:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:38:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:38:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:38:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:38:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:38:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:38:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:38:06 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:38:06 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:38:06 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:38:06 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:38:06 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:38:06 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:38:06 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:38:06 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:38:06 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:38:06 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:38:06 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:38:11 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:38:11 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:38:11 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:38:11 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:38:11 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:38:11 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:38:11 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:38:11 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:38:11 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:38:11 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:38:11 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:38:11 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:38:11 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:38:11 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:38:11 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:38:11 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:38:11 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:38:11 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:38:11 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:38:11 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:38:11 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:38:11 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:38:11 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:38:11 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:38:11 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:38:11 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:38:11 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:38:11 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:38:11 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:38:11 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:38:11 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:38:11 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:38:11 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:38:11 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:38:11 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:38:11 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:38:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:38:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:38:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:38:11 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:38:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:38:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:38:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:38:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:38:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:38:11 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:38:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:38:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:38:11 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:38:11 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:38:11 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:38:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:38:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:38:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:38:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:38:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:38:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:38:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:38:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:38:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:38:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:38:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:38:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:38:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:38:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:38:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:38:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:38:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:38:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:38:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:38:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:38:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:38:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:38:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:38:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:38:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:38:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:38:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:38:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:38:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:38:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:38:11 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:38:11 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:38:11 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:38:11 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:38:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:38:11 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:38:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:38:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:38:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:38:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:38:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:38:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:38:11 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:38:11 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:38:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:38:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:38:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:38:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:38:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:38:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:38:12 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:38:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:38:12 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:38:12 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:38:12 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:38:12 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:38:13 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:38:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:38:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:38:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:38:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:38:13 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 04:38:13 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 04:38:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:38:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:38:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:38:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:38:14 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 04:38:14 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 04:38:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:38:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:38:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:38:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:38:15 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 04:38:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:38:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:38:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:38:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:38:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:38:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:38:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:38:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:38:15 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:38:15 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:38:15 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:38:15 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:38:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:38:15 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:38:15 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:38:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:38:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:38:15 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 04:38:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:38:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:38:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:38:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:38:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:38:16 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 04:38:16 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 04:38:17 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 04:38:17 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 04:38:18 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 04:38:18 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 04:38:19 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 04:38:19 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 04:38:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:38:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:38:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:38:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:38:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:38:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:38:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:38:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:38:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:38:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:38:20 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:38:20 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:38:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:38:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:38:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:38:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:38:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:38:20 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 04:38:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:38:20 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 04:38:21 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 04:38:21 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 04:38:22 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-27 04:38:22 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-27 04:38:23 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-27 04:38:23 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-27 04:38:23 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-27 04:38:24 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-27 04:38:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:38:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:38:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:38:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:38:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:38:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:38:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:38:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:38:24 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:38:24 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:38:24 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:38:24 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:38:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:38:24 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:38:24 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:38:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:38:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:38:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:38:24 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-27 04:38:25 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-27 04:38:25 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-27 04:38:26 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-27 04:38:26 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-27 04:38:27 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-27 04:38:27 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-27 04:38:28 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-27 04:38:28 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-27 04:38:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:38:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:38:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:38:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:38:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:38:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:38:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:38:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:38:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:38:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:38:28 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:38:28 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:38:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:38:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:38:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:38:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:38:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:38:29 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-27 04:38:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:38:29 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2025-04-27 04:38:30 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2025-04-27 04:38:30 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2025-04-27 04:38:31 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2025-04-27 04:38:31 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2025-04-27 04:38:32 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2025-04-27 04:38:32 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2025-04-27 04:38:32 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2025-04-27 04:38:33 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2025-04-27 04:38:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:38:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:38:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:38:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:38:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:38:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:38:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:38:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:38:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:38:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:38:33 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:38:33 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:38:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:38:33 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 04:38:33 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2025-04-27 04:38:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:38:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:38:33 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2025-04-27 04:38:34 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2025-04-27 04:38:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:38:34 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2025-04-27 04:38:35 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2025-04-27 04:38:35 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2025-04-27 04:38:36 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2025-04-27 04:38:36 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2025-04-27 04:38:37 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2025-04-27 04:38:37 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2025-04-27 04:38:38 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2025-04-27 04:38:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:38:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:38:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:38:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:38:38 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 04:38:38 [WARNING] transceiver.py:250 (MS@172.18.127.22:6700) RX TRXD message (fn=5870 tn=3 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:38:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:38:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:38:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:38:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:38:38 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:38:38 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:38:38 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:38:38 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:38:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:38:38 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 04:38:38 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=3, maio=3, ma_len=4
2025-04-27 04:38:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:38:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:38:38 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2025-04-27 04:38:39 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2025-04-27 04:38:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:38:39 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2025-04-27 04:38:40 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2025-04-27 04:38:40 [DEBUG] clck_gen.py:102 IND CLOCK 6324
2025-04-27 04:38:41 [DEBUG] clck_gen.py:102 IND CLOCK 6426
2025-04-27 04:38:41 [DEBUG] clck_gen.py:102 IND CLOCK 6528
2025-04-27 04:38:41 [DEBUG] clck_gen.py:102 IND CLOCK 6630
2025-04-27 04:38:42 [DEBUG] clck_gen.py:102 IND CLOCK 6732
2025-04-27 04:38:42 [DEBUG] clck_gen.py:102 IND CLOCK 6834
2025-04-27 04:38:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:38:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:38:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:38:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:38:43 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 04:38:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:38:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:38:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:38:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:38:43 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:38:43 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:38:43 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:38:43 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:38:43 [DEBUG] clck_gen.py:102 IND CLOCK 6936
2025-04-27 04:38:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:38:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:38:43 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:38:43 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:38:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:38:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:38:43 [DEBUG] clck_gen.py:102 IND CLOCK 7038
2025-04-27 04:38:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:38:44 [DEBUG] clck_gen.py:102 IND CLOCK 7140
2025-04-27 04:38:44 [DEBUG] clck_gen.py:102 IND CLOCK 7242
2025-04-27 04:38:45 [DEBUG] clck_gen.py:102 IND CLOCK 7344
2025-04-27 04:38:45 [DEBUG] clck_gen.py:102 IND CLOCK 7446
2025-04-27 04:38:46 [DEBUG] clck_gen.py:102 IND CLOCK 7548
2025-04-27 04:38:46 [DEBUG] clck_gen.py:102 IND CLOCK 7650
2025-04-27 04:38:47 [DEBUG] clck_gen.py:102 IND CLOCK 7752
2025-04-27 04:38:47 [DEBUG] clck_gen.py:102 IND CLOCK 7854
2025-04-27 04:38:48 [DEBUG] clck_gen.py:102 IND CLOCK 7956
2025-04-27 04:38:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:38:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:38:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:38:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:38:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:38:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:38:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:38:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:38:48 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:38:48 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:38:48 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:38:48 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:38:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:38:48 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:38:48 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:38:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:38:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:38:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:38:48 [DEBUG] clck_gen.py:102 IND CLOCK 8058
2025-04-27 04:38:49 [DEBUG] clck_gen.py:102 IND CLOCK 8160
2025-04-27 04:38:49 [DEBUG] clck_gen.py:102 IND CLOCK 8262
2025-04-27 04:38:50 [DEBUG] clck_gen.py:102 IND CLOCK 8364
2025-04-27 04:38:50 [DEBUG] clck_gen.py:102 IND CLOCK 8466
2025-04-27 04:38:51 [DEBUG] clck_gen.py:102 IND CLOCK 8568
2025-04-27 04:38:51 [DEBUG] clck_gen.py:102 IND CLOCK 8670
2025-04-27 04:38:51 [DEBUG] clck_gen.py:102 IND CLOCK 8772
2025-04-27 04:38:52 [DEBUG] clck_gen.py:102 IND CLOCK 8874
2025-04-27 04:38:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:38:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:38:52 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:38:52 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:38:52 [WARNING] transceiver.py:250 (MS@172.18.127.22:6700) RX TRXD message (fn=8916 tn=1 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:38:52 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:38:52 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:38:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:38:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:38:52 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:38:52 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:38:52 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:38:52 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:38:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:38:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:38:52 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:38:52 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:38:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:38:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:38:52 [DEBUG] clck_gen.py:102 IND CLOCK 8976
2025-04-27 04:38:53 [DEBUG] clck_gen.py:102 IND CLOCK 9078
2025-04-27 04:38:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:38:53 [DEBUG] clck_gen.py:102 IND CLOCK 9180
2025-04-27 04:38:54 [DEBUG] clck_gen.py:102 IND CLOCK 9282
2025-04-27 04:38:54 [DEBUG] clck_gen.py:102 IND CLOCK 9384
2025-04-27 04:38:55 [DEBUG] clck_gen.py:102 IND CLOCK 9486
2025-04-27 04:38:55 [DEBUG] clck_gen.py:102 IND CLOCK 9588
2025-04-27 04:38:56 [DEBUG] clck_gen.py:102 IND CLOCK 9690
2025-04-27 04:38:56 [DEBUG] clck_gen.py:102 IND CLOCK 9792
2025-04-27 04:38:57 [DEBUG] clck_gen.py:102 IND CLOCK 9894
2025-04-27 04:38:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:38:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:38:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:38:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:38:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:38:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:38:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:38:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:38:57 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:38:57 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:38:57 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:38:57 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:38:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:38:57 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 04:38:57 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-27 04:38:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:38:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:38:57 [DEBUG] clck_gen.py:102 IND CLOCK 9996
2025-04-27 04:38:58 [DEBUG] clck_gen.py:102 IND CLOCK 10098
2025-04-27 04:38:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:38:58 [DEBUG] clck_gen.py:102 IND CLOCK 10200
2025-04-27 04:38:59 [DEBUG] clck_gen.py:102 IND CLOCK 10302
2025-04-27 04:38:59 [DEBUG] clck_gen.py:102 IND CLOCK 10404
2025-04-27 04:39:00 [DEBUG] clck_gen.py:102 IND CLOCK 10506
2025-04-27 04:39:00 [DEBUG] clck_gen.py:102 IND CLOCK 10608
2025-04-27 04:39:01 [DEBUG] clck_gen.py:102 IND CLOCK 10710
2025-04-27 04:39:01 [DEBUG] clck_gen.py:102 IND CLOCK 10812
2025-04-27 04:39:01 [DEBUG] clck_gen.py:102 IND CLOCK 10914
2025-04-27 04:39:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:39:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:39:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:39:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:39:02 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 04:39:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:39:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:39:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:39:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:39:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:39:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:39:02 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:39:02 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:39:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:39:02 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 04:39:02 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-27 04:39:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:39:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:39:02 [DEBUG] clck_gen.py:102 IND CLOCK 11016
2025-04-27 04:39:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:39:02 [DEBUG] clck_gen.py:102 IND CLOCK 11118
2025-04-27 04:39:03 [DEBUG] clck_gen.py:102 IND CLOCK 11220
2025-04-27 04:39:03 [DEBUG] clck_gen.py:102 IND CLOCK 11322
2025-04-27 04:39:04 [DEBUG] clck_gen.py:102 IND CLOCK 11424
2025-04-27 04:39:04 [DEBUG] clck_gen.py:102 IND CLOCK 11526
2025-04-27 04:39:05 [DEBUG] clck_gen.py:102 IND CLOCK 11628
2025-04-27 04:39:05 [DEBUG] clck_gen.py:102 IND CLOCK 11730
2025-04-27 04:39:06 [DEBUG] clck_gen.py:102 IND CLOCK 11832
2025-04-27 04:39:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:39:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:39:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:39:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:39:06 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 04:39:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:39:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:39:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:39:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:39:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:39:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:39:06 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:39:06 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:39:06 [DEBUG] clck_gen.py:102 IND CLOCK 11934
2025-04-27 04:39:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:39:06 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 04:39:06 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-27 04:39:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:39:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:39:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:39:07 [DEBUG] clck_gen.py:102 IND CLOCK 12036
2025-04-27 04:39:07 [DEBUG] clck_gen.py:102 IND CLOCK 12138
2025-04-27 04:39:08 [DEBUG] clck_gen.py:102 IND CLOCK 12240
2025-04-27 04:39:08 [DEBUG] clck_gen.py:102 IND CLOCK 12342
2025-04-27 04:39:09 [DEBUG] clck_gen.py:102 IND CLOCK 12444
2025-04-27 04:39:09 [DEBUG] clck_gen.py:102 IND CLOCK 12546
2025-04-27 04:39:10 [DEBUG] clck_gen.py:102 IND CLOCK 12648
2025-04-27 04:39:10 [DEBUG] clck_gen.py:102 IND CLOCK 12750
2025-04-27 04:39:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:39:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:39:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:39:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:39:10 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 04:39:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:39:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:39:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:39:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:39:10 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:39:10 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:39:10 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:39:10 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:39:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:39:10 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 04:39:10 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-27 04:39:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:39:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:39:11 [DEBUG] clck_gen.py:102 IND CLOCK 12852
2025-04-27 04:39:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:39:11 [DEBUG] clck_gen.py:102 IND CLOCK 12954
2025-04-27 04:39:12 [DEBUG] clck_gen.py:102 IND CLOCK 13056
2025-04-27 04:39:12 [DEBUG] clck_gen.py:102 IND CLOCK 13158
2025-04-27 04:39:12 [DEBUG] clck_gen.py:102 IND CLOCK 13260
2025-04-27 04:39:13 [DEBUG] clck_gen.py:102 IND CLOCK 13362
2025-04-27 04:39:13 [DEBUG] clck_gen.py:102 IND CLOCK 13464
2025-04-27 04:39:14 [DEBUG] clck_gen.py:102 IND CLOCK 13566
2025-04-27 04:39:14 [DEBUG] clck_gen.py:102 IND CLOCK 13668
2025-04-27 04:39:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:39:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:39:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:39:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:39:15 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 04:39:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:39:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:39:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:39:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:39:15 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:39:15 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:39:15 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:39:15 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:39:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:39:15 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 04:39:15 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-27 04:39:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:39:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:39:15 [DEBUG] clck_gen.py:102 IND CLOCK 13770
2025-04-27 04:39:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:39:15 [DEBUG] clck_gen.py:102 IND CLOCK 13872
2025-04-27 04:39:16 [DEBUG] clck_gen.py:102 IND CLOCK 13974
2025-04-27 04:39:16 [DEBUG] clck_gen.py:102 IND CLOCK 14076
2025-04-27 04:39:17 [DEBUG] clck_gen.py:102 IND CLOCK 14178
2025-04-27 04:39:17 [DEBUG] clck_gen.py:102 IND CLOCK 14280
2025-04-27 04:39:18 [DEBUG] clck_gen.py:102 IND CLOCK 14382
2025-04-27 04:39:18 [DEBUG] clck_gen.py:102 IND CLOCK 14484
2025-04-27 04:39:19 [DEBUG] clck_gen.py:102 IND CLOCK 14586
2025-04-27 04:39:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:39:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:39:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:39:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:39:19 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 04:39:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:39:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:39:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:39:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:39:19 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:39:19 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:39:19 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:39:19 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:39:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:39:19 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 04:39:19 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-27 04:39:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:39:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:39:19 [DEBUG] clck_gen.py:102 IND CLOCK 14688
2025-04-27 04:39:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:39:20 [DEBUG] clck_gen.py:102 IND CLOCK 14790
2025-04-27 04:39:20 [DEBUG] clck_gen.py:102 IND CLOCK 14892
2025-04-27 04:39:21 [DEBUG] clck_gen.py:102 IND CLOCK 14994
2025-04-27 04:39:21 [DEBUG] clck_gen.py:102 IND CLOCK 15096
2025-04-27 04:39:22 [DEBUG] clck_gen.py:102 IND CLOCK 15198
2025-04-27 04:39:22 [DEBUG] clck_gen.py:102 IND CLOCK 15300
2025-04-27 04:39:23 [DEBUG] clck_gen.py:102 IND CLOCK 15402
2025-04-27 04:39:23 [DEBUG] clck_gen.py:102 IND CLOCK 15504
2025-04-27 04:39:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:39:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:39:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:39:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:39:23 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 04:39:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:39:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:39:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:39:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:39:23 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:39:23 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:39:23 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:39:23 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:39:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:39:23 [DEBUG] clck_gen.py:102 IND CLOCK 15606
2025-04-27 04:39:23 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 04:39:23 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-27 04:39:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:39:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:39:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:39:24 [DEBUG] clck_gen.py:102 IND CLOCK 15708
2025-04-27 04:39:24 [DEBUG] clck_gen.py:102 IND CLOCK 15810
2025-04-27 04:39:25 [DEBUG] clck_gen.py:102 IND CLOCK 15912
2025-04-27 04:39:25 [DEBUG] clck_gen.py:102 IND CLOCK 16014
2025-04-27 04:39:26 [DEBUG] clck_gen.py:102 IND CLOCK 16116
2025-04-27 04:39:26 [DEBUG] clck_gen.py:102 IND CLOCK 16218
2025-04-27 04:39:27 [DEBUG] clck_gen.py:102 IND CLOCK 16320
2025-04-27 04:39:27 [DEBUG] clck_gen.py:102 IND CLOCK 16422
2025-04-27 04:39:28 [DEBUG] clck_gen.py:102 IND CLOCK 16524
2025-04-27 04:39:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:39:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:39:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:39:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:39:28 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 04:39:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:39:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:39:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:39:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:39:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:39:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:39:28 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:39:28 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:39:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:39:28 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 04:39:28 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-27 04:39:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:39:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:39:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:39:28 [DEBUG] clck_gen.py:102 IND CLOCK 16626
2025-04-27 04:39:29 [DEBUG] clck_gen.py:102 IND CLOCK 16728
2025-04-27 04:39:29 [DEBUG] clck_gen.py:102 IND CLOCK 16830
2025-04-27 04:39:30 [DEBUG] clck_gen.py:102 IND CLOCK 16932
2025-04-27 04:39:30 [DEBUG] clck_gen.py:102 IND CLOCK 17034
2025-04-27 04:39:31 [DEBUG] clck_gen.py:102 IND CLOCK 17136
2025-04-27 04:39:31 [DEBUG] clck_gen.py:102 IND CLOCK 17238
2025-04-27 04:39:32 [DEBUG] clck_gen.py:102 IND CLOCK 17340
2025-04-27 04:39:32 [DEBUG] clck_gen.py:102 IND CLOCK 17442
2025-04-27 04:39:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:39:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:39:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:39:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:39:32 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 04:39:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:39:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:39:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:39:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:39:32 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:39:32 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:39:32 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:39:32 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:39:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:39:32 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 04:39:32 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-27 04:39:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:39:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:39:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:39:33 [DEBUG] clck_gen.py:102 IND CLOCK 17544
2025-04-27 04:39:33 [DEBUG] clck_gen.py:102 IND CLOCK 17646
2025-04-27 04:39:33 [DEBUG] clck_gen.py:102 IND CLOCK 17748
2025-04-27 04:39:34 [DEBUG] clck_gen.py:102 IND CLOCK 17850
2025-04-27 04:39:34 [DEBUG] clck_gen.py:102 IND CLOCK 17952
2025-04-27 04:39:35 [DEBUG] clck_gen.py:102 IND CLOCK 18054
2025-04-27 04:39:35 [DEBUG] clck_gen.py:102 IND CLOCK 18156
2025-04-27 04:39:36 [DEBUG] clck_gen.py:102 IND CLOCK 18258
2025-04-27 04:39:36 [DEBUG] clck_gen.py:102 IND CLOCK 18360
2025-04-27 04:39:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:39:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:39:36 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:39:36 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:39:36 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 04:39:36 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:39:36 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:39:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:39:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:39:36 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:39:36 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:39:36 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:39:36 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:39:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:39:37 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 04:39:37 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-27 04:39:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:39:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:39:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:39:37 [DEBUG] clck_gen.py:102 IND CLOCK 18462
2025-04-27 04:39:37 [DEBUG] clck_gen.py:102 IND CLOCK 18564
2025-04-27 04:39:38 [DEBUG] clck_gen.py:102 IND CLOCK 18666
2025-04-27 04:39:38 [DEBUG] clck_gen.py:102 IND CLOCK 18768
2025-04-27 04:39:39 [DEBUG] clck_gen.py:102 IND CLOCK 18870
2025-04-27 04:39:39 [DEBUG] clck_gen.py:102 IND CLOCK 18972
2025-04-27 04:39:40 [DEBUG] clck_gen.py:102 IND CLOCK 19074
2025-04-27 04:39:40 [DEBUG] clck_gen.py:102 IND CLOCK 19176
2025-04-27 04:39:41 [DEBUG] clck_gen.py:102 IND CLOCK 19278
2025-04-27 04:39:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:39:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:39:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:39:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:39:41 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 04:39:41 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:39:41 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:39:41 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:39:41 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:39:41 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:39:41 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:39:41 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:39:41 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:39:41 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:39:41 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:39:41 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:39:41 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=19321 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:39:41 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=19321 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:39:41 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=19321 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:39:41 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=19321 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:39:41 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=19321 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:39:41 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=19321 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:39:41 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=19321 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:39:41 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=19322 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:39:41 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=19322 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:39:41 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=19322 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:39:41 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=19322 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:39:41 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=19322 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:39:41 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=19322 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:39:41 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=19322 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:39:41 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=19322 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:39:46 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:39:46 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:39:46 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:39:46 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:39:46 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:39:46 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:39:46 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:39:46 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:39:46 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:39:46 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:39:46 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:39:46 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:39:46 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:39:46 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:39:46 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:39:46 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:39:46 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:39:46 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:39:46 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:39:46 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:39:46 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:39:46 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:39:46 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:39:46 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:39:46 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:39:46 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:39:46 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:39:46 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:39:46 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:39:46 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:39:46 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:39:46 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:39:46 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:39:46 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:39:46 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:39:46 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:39:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:39:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:39:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:39:46 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:39:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:39:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:39:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:39:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:39:46 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:39:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:39:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:39:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:39:46 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:39:46 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:39:46 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:39:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:39:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:39:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:39:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:39:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:39:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:39:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:39:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:39:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:39:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:39:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:39:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:39:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:39:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:39:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:39:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:39:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:39:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:39:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:39:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:39:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:39:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:39:46 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:39:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:39:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:39:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:39:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:39:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:39:46 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:39:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:39:46 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:39:46 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:39:46 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:39:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:39:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:39:51 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:39:51 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:39:51 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:39:51 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:39:51 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:39:51 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:39:51 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:39:51 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:39:51 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:39:51 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:39:51 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:39:51 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:39:51 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:39:51 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:39:51 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:39:51 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:39:51 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:39:51 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:39:51 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:39:51 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:39:51 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:39:51 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:39:51 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:39:51 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:39:51 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:39:51 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:39:51 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:39:51 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:39:51 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:39:51 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:39:51 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:39:51 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:39:51 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:39:51 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:39:51 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:39:51 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:39:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:39:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:39:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:39:51 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:39:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:39:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:39:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:39:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:39:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:39:51 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:39:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:39:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:39:51 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:39:51 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:39:51 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:39:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:39:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:39:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:39:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:39:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:39:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:39:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:39:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:39:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:39:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:39:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:39:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:39:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:39:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:39:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:39:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:39:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:39:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:39:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:39:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:39:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:39:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:39:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:39:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:39:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:39:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:39:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:39:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:39:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:39:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:39:51 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:39:51 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:39:51 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:39:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:39:51 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:39:51 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:39:51 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:39:51 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:39:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:39:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:39:51 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:39:51 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:39:51 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:39:51 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:39:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:39:51 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:39:51 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:39:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:39:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:39:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:39:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:39:52 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:39:52 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:39:52 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:39:52 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:39:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:39:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:39:52 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:39:52 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:39:52 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:39:52 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:39:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:39:52 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:39:52 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:39:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:39:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:39:52 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:39:52 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:39:52 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:39:52 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:39:52 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:39:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:39:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:39:52 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:39:52 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:39:52 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:39:52 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:39:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:39:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:39:52 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:39:52 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:39:52 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:39:52 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:39:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:39:52 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:39:52 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:39:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:39:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:39:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:39:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:39:52 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:39:52 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:39:52 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:39:52 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:39:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:39:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:39:52 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:39:52 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:39:52 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:39:52 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:39:52 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:39:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:39:52 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:39:52 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:39:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:39:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:39:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:39:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:39:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:39:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:39:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:39:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:39:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:39:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:39:53 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:39:53 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:39:53 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:39:53 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:39:53 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:39:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:39:53 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:39:53 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:39:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:39:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:39:53 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:39:53 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:39:53 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:39:53 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:39:53 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 04:39:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:39:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:39:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:39:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:39:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:39:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:39:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:39:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:39:53 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:39:53 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:39:53 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:39:53 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:39:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:39:53 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 04:39:53 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2025-04-27 04:39:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:39:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:39:54 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 04:39:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:39:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:39:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:39:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:39:54 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 04:39:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:39:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:39:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:39:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:39:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:39:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:39:54 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:39:54 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:39:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:39:54 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:39:54 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:39:54 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:39:54 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:39:54 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 04:39:54 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=3, maio=3, ma_len=4
2025-04-27 04:39:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:39:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:39:54 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 04:39:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:39:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:39:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:39:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:39:54 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 04:39:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:39:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:39:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:39:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:39:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:39:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:39:54 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:39:54 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:39:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:39:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:39:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:39:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:39:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:39:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:39:55 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 04:39:55 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:39:55 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:39:55 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:39:55 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:39:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:39:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:39:55 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:39:55 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:39:55 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:39:55 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:39:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:39:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:39:55 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:39:55 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:39:55 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:39:55 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:39:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:39:55 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:39:55 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:39:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:39:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:39:55 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 04:39:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:39:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:39:55 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:39:55 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:39:55 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:39:55 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:39:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:39:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:39:55 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:39:55 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:39:55 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:39:55 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:39:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:39:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:39:56 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:39:56 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:39:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:39:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:39:56 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 04:39:56 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:39:56 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:39:56 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:39:56 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:39:56 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 04:39:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:39:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:39:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:39:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:39:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:39:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:39:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:39:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:39:56 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:39:56 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:39:56 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:39:56 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:39:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:39:56 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 04:39:56 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-27 04:39:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:39:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:39:57 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 04:39:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:39:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:39:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:39:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:39:57 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 04:39:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:39:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:39:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:39:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:39:57 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:39:57 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:39:57 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:39:57 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:39:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:39:57 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 04:39:57 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-27 04:39:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:39:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:39:57 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 04:39:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:39:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:39:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:39:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:39:57 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 04:39:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:39:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:39:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:39:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:39:57 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:39:57 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:39:57 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:39:57 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:39:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:39:57 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 04:39:57 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-27 04:39:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:39:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:39:58 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 04:39:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:39:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:39:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:39:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:39:58 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 04:39:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:39:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:39:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:39:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:39:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:39:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:39:58 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:39:58 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:39:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:39:58 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 04:39:58 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-27 04:39:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:39:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:39:58 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 04:39:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:39:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:39:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:39:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:39:58 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 04:39:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:39:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:39:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:39:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:39:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:39:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:39:58 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:39:58 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:39:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:39:58 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 04:39:58 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-27 04:39:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:39:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:39:58 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 04:39:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:39:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:39:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:39:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:39:59 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 04:39:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:39:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:39:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:39:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:39:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:39:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:39:59 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:39:59 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:39:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:39:59 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 04:39:59 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-27 04:39:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:39:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:39:59 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 04:39:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:39:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:39:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:39:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:39:59 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 04:39:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:39:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:39:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:39:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:39:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:39:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:39:59 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:39:59 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:39:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:39:59 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 04:39:59 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-27 04:39:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:39:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:39:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:39:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:39:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:39:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:39:59 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 04:39:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:39:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:39:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:39:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:39:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:39:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:39:59 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:39:59 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:39:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:39:59 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 04:39:59 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-27 04:39:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:39:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:39:59 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 04:40:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:40:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:40:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:40:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:40:00 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 04:40:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:40:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:40:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:40:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:40:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:40:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:40:00 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:40:00 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:40:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:40:00 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 04:40:00 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-27 04:40:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:40:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:40:00 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 04:40:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:40:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:40:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:40:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:40:00 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 04:40:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:40:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:40:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:40:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:40:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:40:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:40:00 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:40:00 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:40:00 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 04:40:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:40:00 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 04:40:00 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-27 04:40:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:40:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:40:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:40:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:40:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:40:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:40:01 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 04:40:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:40:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:40:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:40:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:40:01 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:40:01 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:40:01 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:40:01 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:40:01 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:40:01 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:40:01 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:40:01 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2141 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:40:01 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2141 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:40:01 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2141 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:40:01 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2141 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:40:01 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2141 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:40:01 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2141 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:40:01 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2141 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:40:01 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2141 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:40:06 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:40:06 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:40:06 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:40:06 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:40:06 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:40:06 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:40:06 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:40:06 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:40:06 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:40:06 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:40:06 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:40:06 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:40:06 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:40:06 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:40:06 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:40:06 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:40:06 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:40:06 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:40:06 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:40:06 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:40:06 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:40:06 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:40:06 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:40:06 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:40:06 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:40:06 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:40:06 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:40:06 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:40:06 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:40:06 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:40:06 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:40:06 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:40:06 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:40:06 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:40:06 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:40:06 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:40:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:40:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:40:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:40:06 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:40:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:40:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:40:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:40:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:40:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:40:06 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:40:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:40:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:40:06 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:40:06 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:40:06 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:40:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:40:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:40:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:40:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:40:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:40:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:40:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:40:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:40:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:40:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:40:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:40:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:40:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:40:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:40:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:40:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:40:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:40:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:40:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:40:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:40:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:40:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:40:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:40:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:40:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:40:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:40:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:40:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:40:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:40:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:40:06 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:40:06 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:40:06 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:40:06 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:40:06 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:40:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:40:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:40:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:40:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:40:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:40:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:40:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:40:06 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:40:06 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:40:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:40:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:40:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:40:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:40:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:40:07 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:40:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:40:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:40:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:40:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:40:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:40:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:40:07 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:40:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:40:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:40:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:40:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:40:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:40:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:40:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:40:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:40:07 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:40:07 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:40:07 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:40:07 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:40:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:40:08 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:40:08 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:40:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:40:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:40:08 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:40:08 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:40:08 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:40:08 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:40:08 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:40:08 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 04:40:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:40:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:40:09 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 04:40:09 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:40:09 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:40:09 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:40:09 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:40:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:40:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:40:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:40:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:40:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:40:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:40:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:40:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:40:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:40:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:40:09 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:40:09 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:40:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:40:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:40:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:40:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:40:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:40:09 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 04:40:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:40:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:40:10 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 04:40:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:40:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:40:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:40:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:40:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:40:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:40:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:40:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:40:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:40:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:40:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:40:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:40:10 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:40:10 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:40:10 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:40:10 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:40:10 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 04:40:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:40:10 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:40:10 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:40:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:40:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:40:11 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 04:40:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:40:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:40:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:40:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:40:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:40:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:40:11 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 04:40:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:40:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:40:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:40:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:40:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:40:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:40:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:40:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:40:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:40:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:40:12 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:40:12 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:40:12 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 04:40:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:40:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:40:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:40:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:40:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:40:12 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 04:40:12 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 04:40:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:40:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:40:13 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 04:40:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:40:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:40:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:40:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:40:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:40:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:40:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:40:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:40:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:40:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:40:13 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:40:13 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:40:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:40:13 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 04:40:13 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2025-04-27 04:40:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:40:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:40:13 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 04:40:14 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 04:40:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:40:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:40:14 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 04:40:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:40:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:40:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:40:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:40:15 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 04:40:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:40:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:40:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:40:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:40:15 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:40:15 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:40:15 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:40:15 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:40:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:40:15 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 04:40:15 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=3, maio=3, ma_len=4
2025-04-27 04:40:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:40:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:40:15 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 04:40:15 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 04:40:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:40:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:40:16 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 04:40:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:40:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:40:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:40:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:40:16 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 04:40:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:40:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:40:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:40:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:40:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:40:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:40:16 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:40:16 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:40:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:40:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:40:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:40:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:40:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:40:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:40:16 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 04:40:17 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-27 04:40:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:40:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:40:17 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-27 04:40:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:40:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:40:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:40:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:40:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:40:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:40:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:40:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:40:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:40:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:40:18 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:40:18 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:40:18 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-27 04:40:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:40:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:40:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:40:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:40:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:40:18 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-27 04:40:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:40:19 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-27 04:40:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:40:19 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-27 04:40:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:40:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:40:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:40:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:40:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:40:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:40:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:40:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:40:19 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:40:19 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:40:19 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:40:19 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:40:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:40:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:40:19 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:40:19 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:40:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:40:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:40:20 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-27 04:40:20 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-27 04:40:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:40:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:40:21 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-27 04:40:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:40:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:40:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:40:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:40:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:40:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:40:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:40:21 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-27 04:40:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:40:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:40:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:40:21 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:40:21 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:40:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:40:21 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 04:40:21 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-27 04:40:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:40:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:40:21 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-27 04:40:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:40:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:40:22 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-27 04:40:22 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-27 04:40:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:40:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:40:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:40:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:40:22 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 04:40:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:40:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:40:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:40:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:40:22 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:40:22 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:40:22 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:40:22 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:40:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:40:23 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 04:40:23 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-27 04:40:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:40:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:40:23 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-27 04:40:23 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-27 04:40:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:40:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:40:24 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-27 04:40:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:40:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:40:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:40:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:40:24 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 04:40:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:40:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:40:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:40:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:40:24 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:40:24 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:40:24 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:40:24 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:40:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:40:24 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 04:40:24 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-27 04:40:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:40:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:40:24 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2025-04-27 04:40:25 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2025-04-27 04:40:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:40:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:40:25 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2025-04-27 04:40:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:40:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:40:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:40:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:40:25 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 04:40:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:40:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:40:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:40:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:40:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:40:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:40:26 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:40:26 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:40:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:40:26 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 04:40:26 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-27 04:40:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:40:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:40:26 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2025-04-27 04:40:26 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2025-04-27 04:40:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:40:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:40:27 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2025-04-27 04:40:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:40:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:40:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:40:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:40:27 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 04:40:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:40:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:40:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:40:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:40:27 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:40:27 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:40:27 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:40:27 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:40:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:40:27 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 04:40:27 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-27 04:40:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:40:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:40:27 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2025-04-27 04:40:28 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2025-04-27 04:40:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:40:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:40:28 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2025-04-27 04:40:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:40:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:40:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:40:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:40:28 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 04:40:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:40:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:40:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:40:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:40:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:40:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:40:28 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:40:28 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:40:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:40:28 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 04:40:28 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-27 04:40:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:40:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:40:29 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2025-04-27 04:40:29 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2025-04-27 04:40:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:40:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:40:30 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2025-04-27 04:40:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:40:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:40:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:40:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:40:30 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 04:40:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:40:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:40:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:40:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:40:30 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:40:30 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:40:30 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:40:30 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:40:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:40:30 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 04:40:30 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-27 04:40:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:40:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:40:30 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2025-04-27 04:40:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:40:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:40:31 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2025-04-27 04:40:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:40:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:40:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:40:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:40:31 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 04:40:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:40:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:40:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:40:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:40:31 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:40:31 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:40:31 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:40:31 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:40:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:40:31 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 04:40:31 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-27 04:40:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:40:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:40:31 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2025-04-27 04:40:32 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2025-04-27 04:40:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:40:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:40:32 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2025-04-27 04:40:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:40:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:40:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:40:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:40:32 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 04:40:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:40:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:40:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:40:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:40:32 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:40:32 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:40:32 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:40:32 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:40:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:40:32 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2025-04-27 04:40:32 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 04:40:32 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-27 04:40:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:40:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:40:33 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2025-04-27 04:40:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:40:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:40:33 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2025-04-27 04:40:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:40:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:40:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:40:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:40:34 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 04:40:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:40:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:40:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:40:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:40:34 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:40:34 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:40:34 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:40:34 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:40:34 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2025-04-27 04:40:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:40:34 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 04:40:34 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-27 04:40:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:40:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:40:34 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2025-04-27 04:40:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:40:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:40:35 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2025-04-27 04:40:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:40:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:40:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:40:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:40:35 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 04:40:35 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:40:35 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:40:35 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:40:35 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:40:35 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:40:35 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:40:35 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:40:35 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:40:35 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:40:35 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:40:35 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:40:35 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=6323 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:40:35 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=6323 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:40:35 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=6323 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:40:35 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=6323 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:40:35 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=6323 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:40:40 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:40:40 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:40:40 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:40:40 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:40:40 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:40:40 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:40:40 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:40:40 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:40:40 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:40:40 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:40:40 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:40:40 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:40:40 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:40:40 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:40:40 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:40:40 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:40:40 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:40:40 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:40:40 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:40:40 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:40:40 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:40:40 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:40:40 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:40:40 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:40:40 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:40:40 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:40:40 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:40:40 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:40:40 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:40:40 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:40:40 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:40:40 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:40:40 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:40:40 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:40:40 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:40:40 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:40:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:40:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:40:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:40:40 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:40:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:40:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:40:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:40:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:40:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:40:40 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:40:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:40:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:40:40 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:40:40 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:40:40 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:40:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:40:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:40:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:40:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:40:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:40:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:40:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:40:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:40:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:40:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:40:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:40:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:40:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:40:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:40:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:40:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:40:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:40:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:40:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:40:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:40:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:40:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:40:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:40:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:40:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:40:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:40:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:40:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:40:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:40:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:40:40 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:40:41 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:40:41 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:40:41 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:40:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:40:41 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:40:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:40:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:40:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:40:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:40:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:40:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:40:41 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:40:41 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:40:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:40:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:40:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:40:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:40:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:40:41 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:40:41 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:40:41 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:40:41 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:40:41 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:40:42 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:40:42 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:40:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:40:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:40:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:40:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:40:43 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 04:40:43 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 04:40:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:40:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:40:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:40:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:40:44 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 04:40:44 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 04:40:44 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:40:44 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:40:44 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:40:44 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:40:45 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 04:40:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:40:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:40:45 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:40:45 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:40:45 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:40:45 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:40:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:40:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:40:45 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:40:45 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:40:45 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:40:45 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:40:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:40:45 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:40:45 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:40:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:40:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:40:45 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 04:40:45 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:40:45 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:40:45 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:40:45 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:40:46 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 04:40:46 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 04:40:47 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 04:40:47 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 04:40:47 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 04:40:48 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 04:40:48 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 04:40:49 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 04:40:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:40:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:40:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:40:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:40:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:40:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:40:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:40:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:40:49 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:40:49 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:40:49 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:40:49 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:40:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:40:49 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:40:49 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:40:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:40:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:40:49 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 04:40:50 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 04:40:50 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 04:40:51 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 04:40:51 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-27 04:40:52 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-27 04:40:52 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-27 04:40:53 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-27 04:40:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:40:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:40:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:40:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:40:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:40:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:40:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:40:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:40:53 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:40:53 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:40:53 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:40:53 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:40:53 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-27 04:40:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:40:53 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:40:53 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:40:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:40:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:40:54 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-27 04:40:54 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-27 04:40:55 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-27 04:40:55 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-27 04:40:56 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-27 04:40:56 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-27 04:40:57 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-27 04:40:57 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-27 04:40:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:40:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:40:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:40:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:40:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:40:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:40:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:40:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:40:57 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:40:57 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:40:57 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:40:57 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:40:57 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-27 04:40:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:40:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:40:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:40:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:40:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:40:58 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-27 04:40:58 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-27 04:40:59 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2025-04-27 04:40:59 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2025-04-27 04:41:00 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2025-04-27 04:41:00 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2025-04-27 04:41:01 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2025-04-27 04:41:01 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2025-04-27 04:41:02 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2025-04-27 04:41:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:41:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:41:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:41:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:41:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:41:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:41:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:41:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:41:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:41:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:41:02 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:41:02 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:41:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:41:02 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2025-04-27 04:41:02 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 04:41:02 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2025-04-27 04:41:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:41:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:41:03 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2025-04-27 04:41:03 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2025-04-27 04:41:04 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2025-04-27 04:41:04 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2025-04-27 04:41:05 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2025-04-27 04:41:05 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2025-04-27 04:41:06 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2025-04-27 04:41:06 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2025-04-27 04:41:07 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2025-04-27 04:41:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:41:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:41:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:41:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:41:07 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 04:41:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:41:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:41:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:41:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:41:07 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:41:07 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:41:07 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:41:07 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:41:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:41:07 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 04:41:07 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=3, maio=3, ma_len=4
2025-04-27 04:41:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:41:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:41:07 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2025-04-27 04:41:07 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2025-04-27 04:41:08 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2025-04-27 04:41:08 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2025-04-27 04:41:09 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2025-04-27 04:41:09 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2025-04-27 04:41:10 [DEBUG] clck_gen.py:102 IND CLOCK 6324
2025-04-27 04:41:10 [DEBUG] clck_gen.py:102 IND CLOCK 6426
2025-04-27 04:41:11 [DEBUG] clck_gen.py:102 IND CLOCK 6528
2025-04-27 04:41:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:41:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:41:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:41:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:41:11 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 04:41:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:41:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:41:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:41:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:41:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:41:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:41:11 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:41:11 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:41:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:41:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:41:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:41:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:41:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:41:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:41:11 [DEBUG] clck_gen.py:102 IND CLOCK 6630
2025-04-27 04:41:12 [DEBUG] clck_gen.py:102 IND CLOCK 6732
2025-04-27 04:41:12 [DEBUG] clck_gen.py:102 IND CLOCK 6834
2025-04-27 04:41:13 [DEBUG] clck_gen.py:102 IND CLOCK 6936
2025-04-27 04:41:13 [DEBUG] clck_gen.py:102 IND CLOCK 7038
2025-04-27 04:41:14 [DEBUG] clck_gen.py:102 IND CLOCK 7140
2025-04-27 04:41:14 [DEBUG] clck_gen.py:102 IND CLOCK 7242
2025-04-27 04:41:15 [DEBUG] clck_gen.py:102 IND CLOCK 7344
2025-04-27 04:41:15 [DEBUG] clck_gen.py:102 IND CLOCK 7446
2025-04-27 04:41:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:41:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:41:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:41:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:41:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:41:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:41:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:41:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:41:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:41:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:41:16 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:41:16 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:41:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:41:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:41:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:41:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:41:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:41:16 [DEBUG] clck_gen.py:102 IND CLOCK 7548
2025-04-27 04:41:16 [DEBUG] clck_gen.py:102 IND CLOCK 7650
2025-04-27 04:41:17 [DEBUG] clck_gen.py:102 IND CLOCK 7752
2025-04-27 04:41:17 [DEBUG] clck_gen.py:102 IND CLOCK 7854
2025-04-27 04:41:18 [DEBUG] clck_gen.py:102 IND CLOCK 7956
2025-04-27 04:41:18 [DEBUG] clck_gen.py:102 IND CLOCK 8058
2025-04-27 04:41:18 [DEBUG] clck_gen.py:102 IND CLOCK 8160
2025-04-27 04:41:19 [DEBUG] clck_gen.py:102 IND CLOCK 8262
2025-04-27 04:41:19 [DEBUG] clck_gen.py:102 IND CLOCK 8364
2025-04-27 04:41:20 [DEBUG] clck_gen.py:102 IND CLOCK 8466
2025-04-27 04:41:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:41:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:41:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:41:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:41:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:41:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:41:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:41:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:41:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:41:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:41:20 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:41:20 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:41:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:41:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:41:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:41:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:41:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:41:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:41:20 [DEBUG] clck_gen.py:102 IND CLOCK 8568
2025-04-27 04:41:21 [DEBUG] clck_gen.py:102 IND CLOCK 8670
2025-04-27 04:41:21 [DEBUG] clck_gen.py:102 IND CLOCK 8772
2025-04-27 04:41:22 [DEBUG] clck_gen.py:102 IND CLOCK 8874
2025-04-27 04:41:22 [DEBUG] clck_gen.py:102 IND CLOCK 8976
2025-04-27 04:41:23 [DEBUG] clck_gen.py:102 IND CLOCK 9078
2025-04-27 04:41:23 [DEBUG] clck_gen.py:102 IND CLOCK 9180
2025-04-27 04:41:24 [DEBUG] clck_gen.py:102 IND CLOCK 9282
2025-04-27 04:41:24 [DEBUG] clck_gen.py:102 IND CLOCK 9384
2025-04-27 04:41:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:41:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:41:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:41:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:41:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:41:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:41:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:41:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:41:24 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:41:24 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:41:24 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:41:24 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:41:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:41:24 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 04:41:24 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-27 04:41:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:41:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:41:25 [DEBUG] clck_gen.py:102 IND CLOCK 9486
2025-04-27 04:41:25 [DEBUG] clck_gen.py:102 IND CLOCK 9588
2025-04-27 04:41:26 [DEBUG] clck_gen.py:102 IND CLOCK 9690
2025-04-27 04:41:26 [DEBUG] clck_gen.py:102 IND CLOCK 9792
2025-04-27 04:41:27 [DEBUG] clck_gen.py:102 IND CLOCK 9894
2025-04-27 04:41:27 [DEBUG] clck_gen.py:102 IND CLOCK 9996
2025-04-27 04:41:28 [DEBUG] clck_gen.py:102 IND CLOCK 10098
2025-04-27 04:41:28 [DEBUG] clck_gen.py:102 IND CLOCK 10200
2025-04-27 04:41:29 [DEBUG] clck_gen.py:102 IND CLOCK 10302
2025-04-27 04:41:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:41:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:41:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:41:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:41:29 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 04:41:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:41:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:41:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:41:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:41:29 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:41:29 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:41:29 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:41:29 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:41:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:41:29 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 04:41:29 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-27 04:41:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:41:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:41:29 [DEBUG] clck_gen.py:102 IND CLOCK 10404
2025-04-27 04:41:30 [DEBUG] clck_gen.py:102 IND CLOCK 10506
2025-04-27 04:41:30 [DEBUG] clck_gen.py:102 IND CLOCK 10608
2025-04-27 04:41:30 [DEBUG] clck_gen.py:102 IND CLOCK 10710
2025-04-27 04:41:31 [DEBUG] clck_gen.py:102 IND CLOCK 10812
2025-04-27 04:41:31 [DEBUG] clck_gen.py:102 IND CLOCK 10914
2025-04-27 04:41:32 [DEBUG] clck_gen.py:102 IND CLOCK 11016
2025-04-27 04:41:32 [DEBUG] clck_gen.py:102 IND CLOCK 11118
2025-04-27 04:41:33 [DEBUG] clck_gen.py:102 IND CLOCK 11220
2025-04-27 04:41:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:41:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:41:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:41:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:41:33 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 04:41:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:41:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:41:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:41:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:41:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:41:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:41:33 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:41:33 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:41:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:41:33 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 04:41:33 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-27 04:41:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:41:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:41:33 [DEBUG] clck_gen.py:102 IND CLOCK 11322
2025-04-27 04:41:34 [DEBUG] clck_gen.py:102 IND CLOCK 11424
2025-04-27 04:41:34 [DEBUG] clck_gen.py:102 IND CLOCK 11526
2025-04-27 04:41:35 [DEBUG] clck_gen.py:102 IND CLOCK 11628
2025-04-27 04:41:35 [DEBUG] clck_gen.py:102 IND CLOCK 11730
2025-04-27 04:41:36 [DEBUG] clck_gen.py:102 IND CLOCK 11832
2025-04-27 04:41:36 [DEBUG] clck_gen.py:102 IND CLOCK 11934
2025-04-27 04:41:37 [DEBUG] clck_gen.py:102 IND CLOCK 12036
2025-04-27 04:41:37 [DEBUG] clck_gen.py:102 IND CLOCK 12138
2025-04-27 04:41:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:41:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:41:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:41:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:41:37 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 04:41:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:41:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:41:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:41:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:41:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:41:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:41:37 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:41:37 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:41:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:41:37 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 04:41:37 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-27 04:41:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:41:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:41:38 [DEBUG] clck_gen.py:102 IND CLOCK 12240
2025-04-27 04:41:38 [DEBUG] clck_gen.py:102 IND CLOCK 12342
2025-04-27 04:41:39 [DEBUG] clck_gen.py:102 IND CLOCK 12444
2025-04-27 04:41:39 [DEBUG] clck_gen.py:102 IND CLOCK 12546
2025-04-27 04:41:39 [DEBUG] clck_gen.py:102 IND CLOCK 12648
2025-04-27 04:41:40 [DEBUG] clck_gen.py:102 IND CLOCK 12750
2025-04-27 04:41:40 [DEBUG] clck_gen.py:102 IND CLOCK 12852
2025-04-27 04:41:41 [DEBUG] clck_gen.py:102 IND CLOCK 12954
2025-04-27 04:41:41 [DEBUG] clck_gen.py:102 IND CLOCK 13056
2025-04-27 04:41:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:41:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:41:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:41:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:41:42 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 04:41:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:41:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:41:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:41:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:41:42 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:41:42 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:41:42 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:41:42 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:41:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:41:42 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 04:41:42 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-27 04:41:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:41:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:41:42 [DEBUG] clck_gen.py:102 IND CLOCK 13158
2025-04-27 04:41:42 [DEBUG] clck_gen.py:102 IND CLOCK 13260
2025-04-27 04:41:43 [DEBUG] clck_gen.py:102 IND CLOCK 13362
2025-04-27 04:41:43 [DEBUG] clck_gen.py:102 IND CLOCK 13464
2025-04-27 04:41:44 [DEBUG] clck_gen.py:102 IND CLOCK 13566
2025-04-27 04:41:44 [DEBUG] clck_gen.py:102 IND CLOCK 13668
2025-04-27 04:41:45 [DEBUG] clck_gen.py:102 IND CLOCK 13770
2025-04-27 04:41:45 [DEBUG] clck_gen.py:102 IND CLOCK 13872
2025-04-27 04:41:46 [DEBUG] clck_gen.py:102 IND CLOCK 13974
2025-04-27 04:41:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:41:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:41:46 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:41:46 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:41:46 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 04:41:46 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:41:46 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:41:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:41:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:41:46 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:41:46 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:41:46 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:41:46 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:41:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:41:46 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 04:41:46 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-27 04:41:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:41:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:41:46 [DEBUG] clck_gen.py:102 IND CLOCK 14076
2025-04-27 04:41:47 [DEBUG] clck_gen.py:102 IND CLOCK 14178
2025-04-27 04:41:47 [DEBUG] clck_gen.py:102 IND CLOCK 14280
2025-04-27 04:41:48 [DEBUG] clck_gen.py:102 IND CLOCK 14382
2025-04-27 04:41:48 [DEBUG] clck_gen.py:102 IND CLOCK 14484
2025-04-27 04:41:49 [DEBUG] clck_gen.py:102 IND CLOCK 14586
2025-04-27 04:41:49 [DEBUG] clck_gen.py:102 IND CLOCK 14688
2025-04-27 04:41:50 [DEBUG] clck_gen.py:102 IND CLOCK 14790
2025-04-27 04:41:50 [DEBUG] clck_gen.py:102 IND CLOCK 14892
2025-04-27 04:41:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:41:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:41:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:41:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:41:50 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 04:41:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:41:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:41:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:41:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:41:50 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:41:50 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:41:50 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:41:50 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:41:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:41:50 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 04:41:50 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-27 04:41:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:41:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:41:50 [DEBUG] clck_gen.py:102 IND CLOCK 14994
2025-04-27 04:41:51 [DEBUG] clck_gen.py:102 IND CLOCK 15096
2025-04-27 04:41:51 [DEBUG] clck_gen.py:102 IND CLOCK 15198
2025-04-27 04:41:52 [DEBUG] clck_gen.py:102 IND CLOCK 15300
2025-04-27 04:41:52 [DEBUG] clck_gen.py:102 IND CLOCK 15402
2025-04-27 04:41:53 [DEBUG] clck_gen.py:102 IND CLOCK 15504
2025-04-27 04:41:53 [DEBUG] clck_gen.py:102 IND CLOCK 15606
2025-04-27 04:41:54 [DEBUG] clck_gen.py:102 IND CLOCK 15708
2025-04-27 04:41:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:41:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:41:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:41:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:41:54 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 04:41:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:41:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:41:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:41:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:41:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:41:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:41:54 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:41:54 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:41:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:41:54 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 04:41:54 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-27 04:41:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:41:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:41:54 [DEBUG] clck_gen.py:102 IND CLOCK 15810
2025-04-27 04:41:55 [DEBUG] clck_gen.py:102 IND CLOCK 15912
2025-04-27 04:41:55 [DEBUG] clck_gen.py:102 IND CLOCK 16014
2025-04-27 04:41:56 [DEBUG] clck_gen.py:102 IND CLOCK 16116
2025-04-27 04:41:56 [DEBUG] clck_gen.py:102 IND CLOCK 16218
2025-04-27 04:41:57 [DEBUG] clck_gen.py:102 IND CLOCK 16320
2025-04-27 04:41:57 [DEBUG] clck_gen.py:102 IND CLOCK 16422
2025-04-27 04:41:58 [DEBUG] clck_gen.py:102 IND CLOCK 16524
2025-04-27 04:41:58 [DEBUG] clck_gen.py:102 IND CLOCK 16626
2025-04-27 04:41:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:41:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:41:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:41:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:41:59 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 04:41:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:41:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:41:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:41:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:41:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:41:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:41:59 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:41:59 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:41:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:41:59 [DEBUG] clck_gen.py:102 IND CLOCK 16728
2025-04-27 04:41:59 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 04:41:59 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-27 04:41:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:41:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:41:59 [DEBUG] clck_gen.py:102 IND CLOCK 16830
2025-04-27 04:42:00 [DEBUG] clck_gen.py:102 IND CLOCK 16932
2025-04-27 04:42:00 [DEBUG] clck_gen.py:102 IND CLOCK 17034
2025-04-27 04:42:01 [DEBUG] clck_gen.py:102 IND CLOCK 17136
2025-04-27 04:42:01 [DEBUG] clck_gen.py:102 IND CLOCK 17238
2025-04-27 04:42:01 [DEBUG] clck_gen.py:102 IND CLOCK 17340
2025-04-27 04:42:02 [DEBUG] clck_gen.py:102 IND CLOCK 17442
2025-04-27 04:42:02 [DEBUG] clck_gen.py:102 IND CLOCK 17544
2025-04-27 04:42:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:42:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:42:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:42:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:42:03 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 04:42:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:42:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:42:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:42:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:42:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:42:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:42:03 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:42:03 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:42:03 [DEBUG] clck_gen.py:102 IND CLOCK 17646
2025-04-27 04:42:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:42:03 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 04:42:03 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-27 04:42:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:42:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:42:03 [DEBUG] clck_gen.py:102 IND CLOCK 17748
2025-04-27 04:42:04 [DEBUG] clck_gen.py:102 IND CLOCK 17850
2025-04-27 04:42:04 [DEBUG] clck_gen.py:102 IND CLOCK 17952
2025-04-27 04:42:05 [DEBUG] clck_gen.py:102 IND CLOCK 18054
2025-04-27 04:42:05 [DEBUG] clck_gen.py:102 IND CLOCK 18156
2025-04-27 04:42:06 [DEBUG] clck_gen.py:102 IND CLOCK 18258
2025-04-27 04:42:06 [DEBUG] clck_gen.py:102 IND CLOCK 18360
2025-04-27 04:42:07 [DEBUG] clck_gen.py:102 IND CLOCK 18462
2025-04-27 04:42:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:42:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:42:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:42:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:42:07 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 04:42:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:42:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:42:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:42:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:42:07 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:42:07 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:42:07 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:42:07 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:42:07 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:42:07 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:42:07 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:42:07 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=18563 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:42:07 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=18563 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:42:07 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=18563 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:42:07 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=18563 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:42:07 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=18563 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:42:07 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=18563 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:42:12 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:42:12 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:42:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:42:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:42:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:42:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:42:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:42:12 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:42:12 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:42:12 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:42:12 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:42:12 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:42:12 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:42:12 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:42:12 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:42:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:42:12 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:42:12 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:42:12 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:42:12 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:42:12 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:42:12 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:42:12 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:42:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:42:12 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:42:12 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:42:12 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:42:12 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:42:12 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:42:12 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:42:12 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:42:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:42:12 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:42:12 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:42:12 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:42:12 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:42:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:42:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:42:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:42:12 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:42:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:42:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:42:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:42:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:42:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:42:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:42:12 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:42:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:42:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:42:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:42:12 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:42:12 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:42:12 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:42:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:42:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:42:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:42:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:42:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:42:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:42:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:42:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:42:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:42:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:42:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:42:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:42:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:42:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:42:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:42:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:42:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:42:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:42:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:42:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:42:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:42:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:42:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:42:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:42:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:42:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:42:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:42:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:42:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:42:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:42:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:42:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:42:12 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:42:12 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:42:12 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:42:17 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:42:17 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:42:17 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:42:17 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:42:17 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:42:17 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:42:17 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:42:17 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:42:17 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:42:17 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:42:17 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:42:17 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:42:17 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:42:17 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:42:17 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:42:17 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:42:17 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:42:17 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:42:17 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:42:17 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:42:17 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:42:17 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:42:17 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:42:17 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:42:17 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:42:17 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:42:17 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:42:17 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:42:17 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:42:17 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:42:17 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:42:17 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:42:17 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:42:17 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:42:17 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:42:17 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:42:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:42:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:42:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:42:17 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:42:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:42:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:42:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:42:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:42:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:42:17 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:42:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:42:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:42:17 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:42:17 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:42:17 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:42:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:42:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:42:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:42:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:42:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:42:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:42:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:42:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:42:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:42:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:42:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:42:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:42:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:42:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:42:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:42:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:42:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:42:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:42:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:42:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:42:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:42:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:42:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:42:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:42:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:42:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:42:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:42:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:42:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:42:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:42:17 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:42:18 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:42:18 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:42:18 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:42:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:42:18 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:42:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:42:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:42:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:42:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:42:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:42:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:42:18 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:42:18 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:42:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:42:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:42:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:42:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:42:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:42:18 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:42:18 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:42:18 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:42:18 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:42:18 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:42:19 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:42:19 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:42:19 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:42:19 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:42:19 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:42:19 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:42:20 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 04:42:20 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 04:42:20 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:42:20 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:42:20 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:42:20 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:42:21 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 04:42:21 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 04:42:21 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:42:21 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:42:21 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:42:21 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:42:22 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 04:42:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:42:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:42:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:42:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:42:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:42:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:42:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:42:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:42:22 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:42:22 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:42:22 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:42:22 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:42:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:42:22 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:42:22 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:42:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:42:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:42:22 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 04:42:22 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:42:22 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:42:22 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:42:22 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:42:22 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 04:42:23 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 04:42:23 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 04:42:24 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 04:42:24 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 04:42:25 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 04:42:25 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 04:42:26 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 04:42:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:42:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:42:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:42:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:42:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:42:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:42:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:42:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:42:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:42:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:42:26 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:42:26 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:42:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:42:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:42:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:42:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:42:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:42:26 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 04:42:27 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 04:42:27 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 04:42:28 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 04:42:28 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-27 04:42:29 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-27 04:42:29 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-27 04:42:30 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-27 04:42:30 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-27 04:42:31 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-27 04:42:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:42:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:42:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:42:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:42:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:42:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:42:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:42:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:42:31 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:42:31 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:42:31 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:42:31 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:42:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:42:31 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:42:31 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:42:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:42:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:42:31 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-27 04:42:32 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-27 04:42:32 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-27 04:42:32 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-27 04:42:33 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-27 04:42:33 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-27 04:42:34 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-27 04:42:34 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-27 04:42:35 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-27 04:42:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:42:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:42:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:42:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:42:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:42:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:42:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:42:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:42:35 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:42:35 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:42:35 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:42:35 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:42:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:42:35 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:42:35 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:42:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:42:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:42:35 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-27 04:42:36 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2025-04-27 04:42:36 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2025-04-27 04:42:37 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2025-04-27 04:42:37 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2025-04-27 04:42:38 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2025-04-27 04:42:38 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2025-04-27 04:42:39 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2025-04-27 04:42:39 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2025-04-27 04:42:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:42:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:42:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:42:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:42:40 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2025-04-27 04:42:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:42:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:42:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:42:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:42:40 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:42:40 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:42:40 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:42:40 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:42:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:42:40 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 04:42:40 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2025-04-27 04:42:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:42:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:42:40 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2025-04-27 04:42:41 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2025-04-27 04:42:41 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2025-04-27 04:42:42 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2025-04-27 04:42:42 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2025-04-27 04:42:43 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2025-04-27 04:42:43 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2025-04-27 04:42:43 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2025-04-27 04:42:44 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2025-04-27 04:42:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:42:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:42:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:42:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:42:44 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 04:42:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:42:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:42:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:42:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:42:44 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:42:44 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:42:44 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:42:44 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:42:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:42:44 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 04:42:44 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=3, maio=3, ma_len=4
2025-04-27 04:42:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:42:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:42:44 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2025-04-27 04:42:45 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2025-04-27 04:42:45 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2025-04-27 04:42:46 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2025-04-27 04:42:46 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2025-04-27 04:42:47 [DEBUG] clck_gen.py:102 IND CLOCK 6324
2025-04-27 04:42:47 [DEBUG] clck_gen.py:102 IND CLOCK 6426
2025-04-27 04:42:48 [DEBUG] clck_gen.py:102 IND CLOCK 6528
2025-04-27 04:42:48 [DEBUG] clck_gen.py:102 IND CLOCK 6630
2025-04-27 04:42:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:42:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:42:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:42:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:42:49 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 04:42:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:42:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:42:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:42:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:42:49 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:42:49 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:42:49 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:42:49 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:42:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:42:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:42:49 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:42:49 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:42:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:42:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:42:49 [DEBUG] clck_gen.py:102 IND CLOCK 6732
2025-04-27 04:42:49 [DEBUG] clck_gen.py:102 IND CLOCK 6834
2025-04-27 04:42:50 [DEBUG] clck_gen.py:102 IND CLOCK 6936
2025-04-27 04:42:50 [DEBUG] clck_gen.py:102 IND CLOCK 7038
2025-04-27 04:42:51 [DEBUG] clck_gen.py:102 IND CLOCK 7140
2025-04-27 04:42:51 [DEBUG] clck_gen.py:102 IND CLOCK 7242
2025-04-27 04:42:52 [DEBUG] clck_gen.py:102 IND CLOCK 7344
2025-04-27 04:42:52 [DEBUG] clck_gen.py:102 IND CLOCK 7446
2025-04-27 04:42:53 [DEBUG] clck_gen.py:102 IND CLOCK 7548
2025-04-27 04:42:53 [DEBUG] clck_gen.py:102 IND CLOCK 7650
2025-04-27 04:42:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:42:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:42:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:42:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:42:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:42:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:42:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:42:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:42:53 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:42:53 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:42:53 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:42:53 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:42:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:42:53 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:42:53 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:42:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:42:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:42:53 [DEBUG] clck_gen.py:102 IND CLOCK 7752
2025-04-27 04:42:54 [DEBUG] clck_gen.py:102 IND CLOCK 7854
2025-04-27 04:42:54 [DEBUG] clck_gen.py:102 IND CLOCK 7956
2025-04-27 04:42:55 [DEBUG] clck_gen.py:102 IND CLOCK 8058
2025-04-27 04:42:55 [DEBUG] clck_gen.py:102 IND CLOCK 8160
2025-04-27 04:42:56 [DEBUG] clck_gen.py:102 IND CLOCK 8262
2025-04-27 04:42:56 [DEBUG] clck_gen.py:102 IND CLOCK 8364
2025-04-27 04:42:57 [DEBUG] clck_gen.py:102 IND CLOCK 8466
2025-04-27 04:42:57 [DEBUG] clck_gen.py:102 IND CLOCK 8568
2025-04-27 04:42:58 [DEBUG] clck_gen.py:102 IND CLOCK 8670
2025-04-27 04:42:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:42:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:42:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:42:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:42:58 [WARNING] transceiver.py:250 (MS@172.18.127.22:6700) RX TRXD message (fn=8696 tn=1 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:42:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:42:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:42:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:42:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:42:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:42:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:42:58 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:42:58 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:42:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:42:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:42:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:42:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:42:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:42:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:42:58 [DEBUG] clck_gen.py:102 IND CLOCK 8772
2025-04-27 04:42:59 [DEBUG] clck_gen.py:102 IND CLOCK 8874
2025-04-27 04:42:59 [DEBUG] clck_gen.py:102 IND CLOCK 8976
2025-04-27 04:43:00 [DEBUG] clck_gen.py:102 IND CLOCK 9078
2025-04-27 04:43:00 [DEBUG] clck_gen.py:102 IND CLOCK 9180
2025-04-27 04:43:01 [DEBUG] clck_gen.py:102 IND CLOCK 9282
2025-04-27 04:43:01 [DEBUG] clck_gen.py:102 IND CLOCK 9384
2025-04-27 04:43:02 [DEBUG] clck_gen.py:102 IND CLOCK 9486
2025-04-27 04:43:02 [DEBUG] clck_gen.py:102 IND CLOCK 9588
2025-04-27 04:43:03 [DEBUG] clck_gen.py:102 IND CLOCK 9690
2025-04-27 04:43:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:43:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:43:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:43:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:43:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:43:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:43:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:43:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:43:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:43:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:43:03 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:43:03 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:43:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:43:03 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 04:43:03 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-27 04:43:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:43:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:43:03 [DEBUG] clck_gen.py:102 IND CLOCK 9792
2025-04-27 04:43:04 [DEBUG] clck_gen.py:102 IND CLOCK 9894
2025-04-27 04:43:04 [DEBUG] clck_gen.py:102 IND CLOCK 9996
2025-04-27 04:43:04 [DEBUG] clck_gen.py:102 IND CLOCK 10098
2025-04-27 04:43:05 [DEBUG] clck_gen.py:102 IND CLOCK 10200
2025-04-27 04:43:05 [DEBUG] clck_gen.py:102 IND CLOCK 10302
2025-04-27 04:43:06 [DEBUG] clck_gen.py:102 IND CLOCK 10404
2025-04-27 04:43:06 [DEBUG] clck_gen.py:102 IND CLOCK 10506
2025-04-27 04:43:07 [DEBUG] clck_gen.py:102 IND CLOCK 10608
2025-04-27 04:43:07 [DEBUG] clck_gen.py:102 IND CLOCK 10710
2025-04-27 04:43:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:43:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:43:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:43:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:43:08 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 04:43:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:43:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:43:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:43:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:43:08 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:43:08 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:43:08 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:43:08 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:43:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:43:08 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 04:43:08 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-27 04:43:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:43:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:43:08 [DEBUG] clck_gen.py:102 IND CLOCK 10812
2025-04-27 04:43:08 [DEBUG] clck_gen.py:102 IND CLOCK 10914
2025-04-27 04:43:09 [DEBUG] clck_gen.py:102 IND CLOCK 11016
2025-04-27 04:43:09 [DEBUG] clck_gen.py:102 IND CLOCK 11118
2025-04-27 04:43:10 [DEBUG] clck_gen.py:102 IND CLOCK 11220
2025-04-27 04:43:10 [DEBUG] clck_gen.py:102 IND CLOCK 11322
2025-04-27 04:43:11 [DEBUG] clck_gen.py:102 IND CLOCK 11424
2025-04-27 04:43:11 [DEBUG] clck_gen.py:102 IND CLOCK 11526
2025-04-27 04:43:12 [DEBUG] clck_gen.py:102 IND CLOCK 11628
2025-04-27 04:43:12 [DEBUG] clck_gen.py:102 IND CLOCK 11730
2025-04-27 04:43:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:43:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:43:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:43:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:43:13 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 04:43:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:43:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:43:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:43:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:43:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:43:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:43:13 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:43:13 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:43:13 [DEBUG] clck_gen.py:102 IND CLOCK 11832
2025-04-27 04:43:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:43:13 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 04:43:13 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-27 04:43:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:43:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:43:13 [DEBUG] clck_gen.py:102 IND CLOCK 11934
2025-04-27 04:43:14 [DEBUG] clck_gen.py:102 IND CLOCK 12036
2025-04-27 04:43:14 [DEBUG] clck_gen.py:102 IND CLOCK 12138
2025-04-27 04:43:14 [DEBUG] clck_gen.py:102 IND CLOCK 12240
2025-04-27 04:43:15 [DEBUG] clck_gen.py:102 IND CLOCK 12342
2025-04-27 04:43:15 [DEBUG] clck_gen.py:102 IND CLOCK 12444
2025-04-27 04:43:16 [DEBUG] clck_gen.py:102 IND CLOCK 12546
2025-04-27 04:43:16 [DEBUG] clck_gen.py:102 IND CLOCK 12648
2025-04-27 04:43:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:43:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:43:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:43:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:43:17 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 04:43:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:43:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:43:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:43:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:43:17 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:43:17 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:43:17 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:43:17 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:43:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:43:17 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 04:43:17 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-27 04:43:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:43:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:43:17 [DEBUG] clck_gen.py:102 IND CLOCK 12750
2025-04-27 04:43:17 [DEBUG] clck_gen.py:102 IND CLOCK 12852
2025-04-27 04:43:18 [DEBUG] clck_gen.py:102 IND CLOCK 12954
2025-04-27 04:43:18 [DEBUG] clck_gen.py:102 IND CLOCK 13056
2025-04-27 04:43:19 [DEBUG] clck_gen.py:102 IND CLOCK 13158
2025-04-27 04:43:19 [DEBUG] clck_gen.py:102 IND CLOCK 13260
2025-04-27 04:43:20 [DEBUG] clck_gen.py:102 IND CLOCK 13362
2025-04-27 04:43:20 [DEBUG] clck_gen.py:102 IND CLOCK 13464
2025-04-27 04:43:21 [DEBUG] clck_gen.py:102 IND CLOCK 13566
2025-04-27 04:43:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:43:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:43:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:43:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:43:21 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 04:43:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:43:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:43:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:43:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:43:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:43:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:43:21 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:43:21 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:43:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:43:21 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 04:43:21 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-27 04:43:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:43:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:43:21 [DEBUG] clck_gen.py:102 IND CLOCK 13668
2025-04-27 04:43:22 [DEBUG] clck_gen.py:102 IND CLOCK 13770
2025-04-27 04:43:22 [DEBUG] clck_gen.py:102 IND CLOCK 13872
2025-04-27 04:43:23 [DEBUG] clck_gen.py:102 IND CLOCK 13974
2025-04-27 04:43:23 [DEBUG] clck_gen.py:102 IND CLOCK 14076
2025-04-27 04:43:24 [DEBUG] clck_gen.py:102 IND CLOCK 14178
2025-04-27 04:43:24 [DEBUG] clck_gen.py:102 IND CLOCK 14280
2025-04-27 04:43:25 [DEBUG] clck_gen.py:102 IND CLOCK 14382
2025-04-27 04:43:25 [DEBUG] clck_gen.py:102 IND CLOCK 14484
2025-04-27 04:43:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:43:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:43:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:43:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:43:25 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 04:43:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:43:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:43:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:43:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:43:25 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:43:25 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:43:25 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:43:25 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:43:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:43:25 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 04:43:25 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-27 04:43:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:43:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:43:25 [DEBUG] clck_gen.py:102 IND CLOCK 14586
2025-04-27 04:43:26 [DEBUG] clck_gen.py:102 IND CLOCK 14688
2025-04-27 04:43:26 [DEBUG] clck_gen.py:102 IND CLOCK 14790
2025-04-27 04:43:27 [DEBUG] clck_gen.py:102 IND CLOCK 14892
2025-04-27 04:43:27 [DEBUG] clck_gen.py:102 IND CLOCK 14994
2025-04-27 04:43:28 [DEBUG] clck_gen.py:102 IND CLOCK 15096
2025-04-27 04:43:28 [DEBUG] clck_gen.py:102 IND CLOCK 15198
2025-04-27 04:43:29 [DEBUG] clck_gen.py:102 IND CLOCK 15300
2025-04-27 04:43:29 [DEBUG] clck_gen.py:102 IND CLOCK 15402
2025-04-27 04:43:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:43:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:43:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:43:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:43:30 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 04:43:30 [WARNING] transceiver.py:250 (MS@172.18.127.22:6700) RX TRXD message (fn=15479 tn=3 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:43:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:43:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:43:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:43:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:43:30 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:43:30 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:43:30 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:43:30 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:43:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:43:30 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 04:43:30 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-27 04:43:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:43:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:43:30 [DEBUG] clck_gen.py:102 IND CLOCK 15504
2025-04-27 04:43:30 [DEBUG] clck_gen.py:102 IND CLOCK 15606
2025-04-27 04:43:31 [DEBUG] clck_gen.py:102 IND CLOCK 15708
2025-04-27 04:43:31 [DEBUG] clck_gen.py:102 IND CLOCK 15810
2025-04-27 04:43:32 [DEBUG] clck_gen.py:102 IND CLOCK 15912
2025-04-27 04:43:32 [DEBUG] clck_gen.py:102 IND CLOCK 16014
2025-04-27 04:43:33 [DEBUG] clck_gen.py:102 IND CLOCK 16116
2025-04-27 04:43:33 [DEBUG] clck_gen.py:102 IND CLOCK 16218
2025-04-27 04:43:34 [DEBUG] clck_gen.py:102 IND CLOCK 16320
2025-04-27 04:43:34 [DEBUG] clck_gen.py:102 IND CLOCK 16422
2025-04-27 04:43:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:43:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:43:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:43:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:43:34 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 04:43:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:43:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:43:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:43:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:43:34 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:43:34 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:43:34 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:43:34 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:43:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:43:34 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 04:43:34 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-27 04:43:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:43:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:43:35 [DEBUG] clck_gen.py:102 IND CLOCK 16524
2025-04-27 04:43:35 [DEBUG] clck_gen.py:102 IND CLOCK 16626
2025-04-27 04:43:36 [DEBUG] clck_gen.py:102 IND CLOCK 16728
2025-04-27 04:43:36 [DEBUG] clck_gen.py:102 IND CLOCK 16830
2025-04-27 04:43:36 [DEBUG] clck_gen.py:102 IND CLOCK 16932
2025-04-27 04:43:37 [DEBUG] clck_gen.py:102 IND CLOCK 17034
2025-04-27 04:43:37 [DEBUG] clck_gen.py:102 IND CLOCK 17136
2025-04-27 04:43:38 [DEBUG] clck_gen.py:102 IND CLOCK 17238
2025-04-27 04:43:38 [DEBUG] clck_gen.py:102 IND CLOCK 17340
2025-04-27 04:43:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:43:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:43:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:43:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:43:38 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 04:43:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:43:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:43:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:43:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:43:38 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:43:38 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:43:38 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:43:38 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:43:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:43:39 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 04:43:39 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-27 04:43:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:43:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:43:39 [DEBUG] clck_gen.py:102 IND CLOCK 17442
2025-04-27 04:43:39 [DEBUG] clck_gen.py:102 IND CLOCK 17544
2025-04-27 04:43:40 [DEBUG] clck_gen.py:102 IND CLOCK 17646
2025-04-27 04:43:40 [DEBUG] clck_gen.py:102 IND CLOCK 17748
2025-04-27 04:43:41 [DEBUG] clck_gen.py:102 IND CLOCK 17850
2025-04-27 04:43:41 [DEBUG] clck_gen.py:102 IND CLOCK 17952
2025-04-27 04:43:42 [DEBUG] clck_gen.py:102 IND CLOCK 18054
2025-04-27 04:43:42 [DEBUG] clck_gen.py:102 IND CLOCK 18156
2025-04-27 04:43:43 [DEBUG] clck_gen.py:102 IND CLOCK 18258
2025-04-27 04:43:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:43:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:43:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:43:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:43:43 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 04:43:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:43:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:43:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:43:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:43:43 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:43:43 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:43:43 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:43:43 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:43:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:43:43 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 04:43:43 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-27 04:43:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:43:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:43:43 [DEBUG] clck_gen.py:102 IND CLOCK 18360
2025-04-27 04:43:44 [DEBUG] clck_gen.py:102 IND CLOCK 18462
2025-04-27 04:43:44 [DEBUG] clck_gen.py:102 IND CLOCK 18564
2025-04-27 04:43:45 [DEBUG] clck_gen.py:102 IND CLOCK 18666
2025-04-27 04:43:45 [DEBUG] clck_gen.py:102 IND CLOCK 18768
2025-04-27 04:43:46 [DEBUG] clck_gen.py:102 IND CLOCK 18870
2025-04-27 04:43:46 [DEBUG] clck_gen.py:102 IND CLOCK 18972
2025-04-27 04:43:46 [DEBUG] clck_gen.py:102 IND CLOCK 19074
2025-04-27 04:43:47 [DEBUG] clck_gen.py:102 IND CLOCK 19176
2025-04-27 04:43:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:43:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:43:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:43:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:43:47 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 04:43:47 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:43:47 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:43:47 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:43:47 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:43:47 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:43:47 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:43:47 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:43:47 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:43:47 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:43:47 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:43:47 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:43:52 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:43:52 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:43:52 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:43:52 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:43:52 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:43:52 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:43:52 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:43:52 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:43:52 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:43:52 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:43:52 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:43:52 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:43:52 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:43:52 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:43:52 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:43:52 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:43:52 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:43:52 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:43:52 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:43:52 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:43:52 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:43:52 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:43:52 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:43:52 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:43:52 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:43:52 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:43:52 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:43:52 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:43:52 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:43:52 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:43:52 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:43:52 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:43:52 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:43:52 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:43:52 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:43:52 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:43:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:43:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:43:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:43:52 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:43:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:43:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:43:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:43:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:43:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:43:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:43:52 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:43:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:43:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:43:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:43:52 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:43:52 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:43:52 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:43:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:43:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:43:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:43:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:43:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:43:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:43:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:43:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:43:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:43:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:43:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:43:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:43:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:43:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:43:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:43:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:43:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:43:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:43:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:43:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:43:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:43:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:43:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:43:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:43:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:43:52 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:43:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:43:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:43:52 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:43:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:43:52 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:43:52 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:43:52 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:43:52 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:43:52 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:43:57 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:43:57 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:43:57 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:43:57 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:43:57 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:43:57 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:43:57 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:43:57 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:43:57 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:43:57 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:43:57 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:43:57 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:43:57 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:43:57 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:43:57 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:43:57 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:43:57 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:43:57 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:43:57 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:43:57 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:43:57 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:43:57 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:43:57 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:43:57 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:43:57 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:43:57 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:43:57 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:43:57 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:43:57 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:43:57 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:43:57 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:43:57 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:43:57 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:43:57 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:43:57 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:43:57 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:43:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:43:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:43:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:43:57 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:43:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:43:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:43:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:43:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:43:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:43:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:43:57 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:43:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:43:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:43:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:43:57 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:43:57 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:43:57 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:43:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:43:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:43:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:43:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:43:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:43:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:43:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:43:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:43:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:43:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:43:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:43:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:43:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:43:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:43:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:43:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:43:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:43:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:43:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:43:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:43:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:43:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:43:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:43:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:43:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:43:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:43:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:43:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:43:57 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:43:58 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:43:58 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:43:58 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:43:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:43:58 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:43:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:43:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:43:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:43:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:43:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:43:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:43:58 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:43:58 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:43:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:43:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:43:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:43:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:43:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:43:58 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:43:58 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:43:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:43:58 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:43:58 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:43:59 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:43:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:43:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:43:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:43:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:43:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:43:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:43:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:43:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:43:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:43:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:43:59 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:43:59 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:43:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:43:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:43:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:43:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:43:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:43:59 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:43:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:43:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:43:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:43:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:44:00 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 04:44:00 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 04:44:00 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:44:00 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:44:00 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:44:00 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:44:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:44:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:44:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:44:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:44:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:44:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:44:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:44:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:44:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:44:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:44:00 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:44:00 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:44:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:44:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:44:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:44:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:44:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:44:00 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 04:44:01 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 04:44:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:44:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:44:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:44:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:44:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:44:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:44:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:44:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:44:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:44:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:44:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:44:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:44:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:44:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:44:01 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:44:01 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:44:01 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 04:44:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:44:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:44:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:44:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:44:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:44:02 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 04:44:02 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:44:02 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:44:02 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:44:02 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:44:02 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 04:44:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:44:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:44:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:44:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:44:03 [WARNING] transceiver.py:250 (MS@172.18.127.22:6700) RX TRXD message (fn=1223 tn=4 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:44:03 [WARNING] transceiver.py:250 (MS@172.18.127.22:6700) RX TRXD message (fn=1223 tn=5 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:44:03 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 04:44:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:44:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:44:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:44:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:44:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:44:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:44:03 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:44:03 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:44:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:44:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:44:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:44:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:44:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:44:03 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 04:44:04 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 04:44:04 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 04:44:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:44:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:44:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:44:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:44:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:44:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:44:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:44:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:44:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:44:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:44:04 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:44:04 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:44:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:44:04 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 04:44:04 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2025-04-27 04:44:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:44:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:44:05 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 04:44:05 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 04:44:06 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 04:44:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:44:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:44:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:44:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:44:06 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 04:44:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:44:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:44:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:44:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:44:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:44:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:44:06 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:44:06 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:44:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:44:06 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 04:44:06 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=3, maio=3, ma_len=4
2025-04-27 04:44:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:44:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:44:06 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 04:44:07 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 04:44:07 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 04:44:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:44:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:44:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:44:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:44:07 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 04:44:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:44:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:44:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:44:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:44:07 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:44:07 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:44:07 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:44:07 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:44:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:44:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:44:08 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:44:08 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:44:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:44:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:44:08 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 04:44:08 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-27 04:44:09 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-27 04:44:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:44:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:44:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:44:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:44:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:44:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:44:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:44:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:44:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:44:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:44:09 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:44:09 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:44:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:44:09 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-27 04:44:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:44:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:44:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:44:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:44:10 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-27 04:44:10 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-27 04:44:10 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-27 04:44:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:44:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:44:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:44:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:44:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:44:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:44:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:44:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:44:10 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:44:10 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:44:10 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:44:10 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:44:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:44:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:44:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:44:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:44:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:44:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:44:11 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-27 04:44:11 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-27 04:44:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:44:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:44:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:44:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:44:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:44:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:44:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:44:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:44:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:44:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:44:12 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:44:12 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:44:12 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-27 04:44:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:44:12 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 04:44:12 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-27 04:44:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:44:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:44:12 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-27 04:44:13 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-27 04:44:13 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-27 04:44:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:44:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:44:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:44:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:44:13 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 04:44:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:44:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:44:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:44:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:44:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:44:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:44:13 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:44:13 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:44:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:44:13 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 04:44:13 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-27 04:44:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:44:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:44:14 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-27 04:44:14 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-27 04:44:15 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-27 04:44:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:44:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:44:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:44:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:44:15 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 04:44:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:44:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:44:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:44:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:44:15 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:44:15 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:44:15 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:44:15 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:44:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:44:15 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 04:44:15 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-27 04:44:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:44:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:44:15 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-27 04:44:16 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2025-04-27 04:44:16 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2025-04-27 04:44:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:44:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:44:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:44:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:44:16 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 04:44:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:44:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:44:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:44:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:44:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:44:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:44:16 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:44:16 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:44:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:44:16 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 04:44:16 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-27 04:44:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:44:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:44:17 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2025-04-27 04:44:17 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2025-04-27 04:44:18 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2025-04-27 04:44:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:44:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:44:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:44:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:44:18 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 04:44:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:44:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:44:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:44:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:44:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:44:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:44:18 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:44:18 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:44:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:44:18 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 04:44:18 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-27 04:44:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:44:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:44:18 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2025-04-27 04:44:19 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2025-04-27 04:44:19 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2025-04-27 04:44:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:44:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:44:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:44:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:44:19 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 04:44:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:44:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:44:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:44:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:44:19 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:44:19 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:44:19 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:44:19 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:44:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:44:19 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 04:44:19 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-27 04:44:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:44:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:44:19 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2025-04-27 04:44:20 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2025-04-27 04:44:20 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2025-04-27 04:44:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:44:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:44:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:44:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:44:21 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 04:44:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:44:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:44:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:44:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:44:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:44:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:44:21 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:44:21 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:44:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:44:21 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 04:44:21 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-27 04:44:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:44:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:44:21 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2025-04-27 04:44:21 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2025-04-27 04:44:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:44:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:44:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:44:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:44:22 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 04:44:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:44:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:44:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:44:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:44:22 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:44:22 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:44:22 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:44:22 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:44:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:44:22 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 04:44:22 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-27 04:44:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:44:22 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2025-04-27 04:44:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:44:22 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2025-04-27 04:44:23 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2025-04-27 04:44:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:44:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:44:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:44:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:44:23 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 04:44:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:44:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:44:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:44:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:44:23 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:44:23 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:44:23 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:44:23 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:44:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:44:23 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 04:44:23 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-27 04:44:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:44:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:44:23 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2025-04-27 04:44:24 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2025-04-27 04:44:24 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2025-04-27 04:44:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:44:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:44:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:44:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:44:25 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 04:44:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:44:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:44:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:44:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:44:25 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:44:25 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:44:25 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:44:25 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:44:25 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2025-04-27 04:44:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:44:25 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 04:44:25 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-27 04:44:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:44:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:44:25 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2025-04-27 04:44:26 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2025-04-27 04:44:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:44:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:44:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:44:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:44:26 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 04:44:26 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:44:26 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:44:26 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:44:26 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:44:26 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:44:26 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:44:26 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:44:26 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:44:26 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:44:26 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:44:26 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:44:26 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=6222 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:44:26 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=6222 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:44:26 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=6222 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:44:26 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=6222 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:44:26 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=6222 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:44:26 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=6222 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:44:26 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=6223 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:44:26 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=6223 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:44:26 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=6223 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:44:26 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=6223 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:44:26 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=6223 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:44:26 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=6223 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:44:26 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=6223 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:44:26 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=6223 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:44:31 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:44:31 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:44:31 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:44:31 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:44:31 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:44:31 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:44:31 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:44:31 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:44:31 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:44:31 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:44:31 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:44:31 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:44:31 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:44:31 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:44:31 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:44:31 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:44:31 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:44:31 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:44:31 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:44:31 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:44:31 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:44:31 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:44:31 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:44:31 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:44:31 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:44:31 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:44:31 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:44:31 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:44:31 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:44:31 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:44:31 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:44:31 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:44:31 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:44:31 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:44:31 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:44:31 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:44:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:44:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:44:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:44:31 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:44:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:44:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:44:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:44:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:44:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:44:31 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:44:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:44:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:44:31 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:44:31 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:44:31 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:44:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:44:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:44:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:44:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:44:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:44:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:44:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:44:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:44:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:44:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:44:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:44:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:44:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:44:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:44:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:44:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:44:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:44:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:44:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:44:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:44:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:44:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:44:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:44:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:44:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:44:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:44:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:44:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:44:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:44:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:44:31 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:44:32 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:44:32 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:44:32 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:44:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:44:32 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:44:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:44:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:44:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:44:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:44:32 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:44:32 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:44:32 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:44:32 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:44:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD HANDOVER
2025-04-27 04:44:32 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:44:32 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:44:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:44:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:44:32 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:44:32 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:44:32 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:44:32 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:44:32 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:44:33 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:44:33 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:44:33 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:44:33 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:44:33 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:44:33 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:44:34 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 04:44:34 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 04:44:34 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:44:34 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:44:34 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:44:34 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:44:35 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 04:44:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:44:35 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 04:44:35 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:44:35 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:44:35 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:44:35 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:44:35 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 04:44:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:44:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:44:36 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:44:36 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:44:36 [WARNING] transceiver.py:250 (MS@172.18.127.22:6700) RX TRXD message (fn=939 tn=3 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:44:36 [WARNING] transceiver.py:250 (MS@172.18.127.22:6700) RX TRXD message (fn=939 tn=4 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:44:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:44:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:44:36 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:44:36 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:44:36 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:44:36 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:44:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD HANDOVER
2025-04-27 04:44:36 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:44:36 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:44:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:44:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:44:36 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 04:44:36 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:44:36 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:44:36 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:44:36 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:44:36 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 04:44:37 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 04:44:37 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 04:44:38 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 04:44:38 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 04:44:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:44:39 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 04:44:39 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 04:44:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:44:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:44:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:44:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:44:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:44:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:44:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:44:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:44:39 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:44:39 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:44:39 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:44:39 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:44:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD HANDOVER
2025-04-27 04:44:39 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 04:44:39 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-27 04:44:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:44:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:44:40 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 04:44:40 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 04:44:41 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 04:44:41 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 04:44:42 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 04:44:42 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-27 04:44:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:44:43 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-27 04:44:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:44:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:44:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:44:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:44:43 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 04:44:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:44:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:44:43 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:44:43 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:44:43 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:44:43 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:44:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD HANDOVER
2025-04-27 04:44:43 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 04:44:43 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-27 04:44:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:44:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:44:43 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-27 04:44:44 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-27 04:44:44 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-27 04:44:45 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-27 04:44:45 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-27 04:44:45 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-27 04:44:46 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-27 04:44:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:44:46 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-27 04:44:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:44:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:44:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:44:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:44:47 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 04:44:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:44:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:44:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:44:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:44:47 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:44:47 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:44:47 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:44:47 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:44:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD HANDOVER
2025-04-27 04:44:47 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:44:47 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:44:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:44:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:44:47 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-27 04:44:47 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-27 04:44:48 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-27 04:44:48 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-27 04:44:49 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-27 04:44:49 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-27 04:44:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:44:50 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2025-04-27 04:44:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:44:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:44:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:44:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:44:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:44:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:44:50 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:44:50 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:44:50 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:44:50 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:44:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD HANDOVER
2025-04-27 04:44:50 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:44:50 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:44:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:44:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:44:50 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2025-04-27 04:44:51 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2025-04-27 04:44:51 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2025-04-27 04:44:52 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2025-04-27 04:44:52 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2025-04-27 04:44:53 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2025-04-27 04:44:53 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2025-04-27 04:44:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:44:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:44:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:44:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:44:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:44:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:44:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:44:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:44:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:44:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:44:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:44:54 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:44:54 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:44:54 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2025-04-27 04:44:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD HANDOVER
2025-04-27 04:44:54 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 04:44:54 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-27 04:44:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:44:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:44:54 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2025-04-27 04:44:55 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2025-04-27 04:44:55 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2025-04-27 04:44:56 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2025-04-27 04:44:56 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2025-04-27 04:44:56 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2025-04-27 04:44:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:44:57 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2025-04-27 04:44:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:44:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:44:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:44:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:44:57 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 04:44:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:44:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:44:57 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:44:57 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:44:57 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:44:57 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:44:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD HANDOVER
2025-04-27 04:44:57 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 04:44:57 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-27 04:44:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:44:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:44:57 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2025-04-27 04:44:58 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2025-04-27 04:44:58 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2025-04-27 04:44:59 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2025-04-27 04:44:59 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2025-04-27 04:45:00 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2025-04-27 04:45:00 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2025-04-27 04:45:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:45:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:45:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:45:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:45:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:45:01 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 04:45:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:45:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:45:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:45:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:45:01 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:45:01 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:45:01 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:45:01 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:45:01 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:45:01 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:45:01 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:45:01 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=6310 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:45:01 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=6310 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:45:01 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=6310 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:45:01 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=6310 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:45:01 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=6310 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:45:06 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:45:06 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:45:06 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:45:06 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:45:06 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:45:06 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:45:06 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:45:06 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:45:06 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:45:06 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:45:06 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:45:06 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:45:06 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:45:06 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:45:06 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:45:06 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:45:06 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:45:06 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:45:06 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:45:06 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:45:06 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:45:06 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:45:06 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:45:06 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:45:06 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:45:06 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:45:06 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:45:06 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:45:06 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:45:06 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:45:06 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:45:06 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:45:06 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:45:06 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:45:06 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:45:06 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:45:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:45:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:45:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:45:06 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:45:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:45:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:45:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:45:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:45:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:45:06 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:45:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:45:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:45:06 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:45:06 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:45:06 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:45:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:45:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:45:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:45:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:45:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:45:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:45:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:45:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:45:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:45:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:45:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:45:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:45:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:45:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:45:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:45:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:45:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:45:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:45:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:45:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:45:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:45:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:45:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:45:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:45:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:45:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:45:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:45:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:45:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:45:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:45:06 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:45:06 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:45:06 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:45:06 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:45:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:45:06 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:45:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:45:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:45:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:45:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:45:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:45:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:45:06 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:45:06 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:45:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD HANDOVER
2025-04-27 04:45:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:45:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:45:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:45:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:45:07 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:45:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:45:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:45:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:45:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:45:07 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:45:08 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:45:08 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:45:08 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:45:08 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:45:08 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:45:08 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 04:45:09 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 04:45:09 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:45:09 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:45:09 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:45:09 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:45:09 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 04:45:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:45:10 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 04:45:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:45:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:45:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:45:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:45:10 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 04:45:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:45:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:45:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:45:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:45:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:45:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:45:10 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:45:10 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:45:10 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:45:10 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:45:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD HANDOVER
2025-04-27 04:45:10 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:45:10 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:45:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:45:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:45:10 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 04:45:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:45:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:45:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:45:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:45:11 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 04:45:11 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 04:45:12 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 04:45:12 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 04:45:13 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 04:45:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:45:13 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 04:45:14 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 04:45:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:45:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:45:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:45:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:45:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:45:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:45:14 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:45:14 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:45:14 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:45:14 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:45:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD HANDOVER
2025-04-27 04:45:14 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:45:14 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:45:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:45:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:45:14 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 04:45:15 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 04:45:15 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 04:45:16 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 04:45:16 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 04:45:17 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-27 04:45:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:45:17 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-27 04:45:18 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-27 04:45:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:45:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:45:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:45:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:45:18 [WARNING] transceiver.py:250 (MS@172.18.127.22:6700) RX TRXD message (fn=2600 tn=6 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:45:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:45:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:45:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:45:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:45:18 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:45:18 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:45:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD HANDOVER
2025-04-27 04:45:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:45:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:45:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:45:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:45:18 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-27 04:45:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:45:19 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-27 04:45:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:45:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:45:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:45:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:45:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:45:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:45:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:45:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:45:19 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:45:19 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:45:19 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:45:19 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:45:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD HANDOVER
2025-04-27 04:45:19 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 04:45:19 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-27 04:45:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:45:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:45:19 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-27 04:45:20 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-27 04:45:20 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-27 04:45:20 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-27 04:45:21 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-27 04:45:21 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-27 04:45:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:45:22 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-27 04:45:22 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-27 04:45:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:45:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:45:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:45:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:45:22 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 04:45:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:45:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:45:22 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:45:22 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:45:22 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:45:22 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:45:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD HANDOVER
2025-04-27 04:45:22 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 04:45:22 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-27 04:45:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:45:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:45:23 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-27 04:45:23 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-27 04:45:24 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-27 04:45:24 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2025-04-27 04:45:25 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2025-04-27 04:45:25 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2025-04-27 04:45:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:45:26 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2025-04-27 04:45:26 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2025-04-27 04:45:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:45:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:45:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:45:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:45:26 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 04:45:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:45:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:45:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:45:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:45:26 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:45:26 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:45:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD HANDOVER
2025-04-27 04:45:26 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 04:45:26 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-27 04:45:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:45:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:45:27 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2025-04-27 04:45:27 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2025-04-27 04:45:28 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2025-04-27 04:45:28 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2025-04-27 04:45:29 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2025-04-27 04:45:29 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2025-04-27 04:45:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:45:30 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2025-04-27 04:45:30 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2025-04-27 04:45:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:45:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:45:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:45:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:45:30 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 04:45:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:45:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:45:30 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:45:30 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:45:30 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:45:30 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:45:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD HANDOVER
2025-04-27 04:45:30 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 04:45:30 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-27 04:45:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:45:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:45:30 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2025-04-27 04:45:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:45:31 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2025-04-27 04:45:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:45:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:45:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:45:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:45:31 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 04:45:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:45:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:45:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:45:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:45:31 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:45:31 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:45:31 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:45:31 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:45:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD HANDOVER
2025-04-27 04:45:31 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:45:31 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:45:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:45:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:45:31 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2025-04-27 04:45:32 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2025-04-27 04:45:32 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2025-04-27 04:45:33 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2025-04-27 04:45:33 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2025-04-27 04:45:34 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2025-04-27 04:45:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:45:34 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2025-04-27 04:45:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:45:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:45:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:45:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:45:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:45:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:45:35 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:45:35 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:45:35 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:45:35 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:45:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD HANDOVER
2025-04-27 04:45:35 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:45:35 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:45:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:45:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:45:35 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2025-04-27 04:45:35 [DEBUG] clck_gen.py:102 IND CLOCK 6324
2025-04-27 04:45:36 [DEBUG] clck_gen.py:102 IND CLOCK 6426
2025-04-27 04:45:36 [DEBUG] clck_gen.py:102 IND CLOCK 6528
2025-04-27 04:45:37 [DEBUG] clck_gen.py:102 IND CLOCK 6630
2025-04-27 04:45:37 [DEBUG] clck_gen.py:102 IND CLOCK 6732
2025-04-27 04:45:38 [DEBUG] clck_gen.py:102 IND CLOCK 6834
2025-04-27 04:45:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:45:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:45:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:45:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:45:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:45:38 [WARNING] transceiver.py:250 (MS@172.18.127.22:6700) RX TRXD message (fn=6931 tn=7 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:45:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:45:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:45:38 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:45:38 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:45:38 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:45:38 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:45:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD HANDOVER
2025-04-27 04:45:38 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:45:38 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:45:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:45:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:45:38 [DEBUG] clck_gen.py:102 IND CLOCK 6936
2025-04-27 04:45:39 [DEBUG] clck_gen.py:102 IND CLOCK 7038
2025-04-27 04:45:39 [DEBUG] clck_gen.py:102 IND CLOCK 7140
2025-04-27 04:45:40 [DEBUG] clck_gen.py:102 IND CLOCK 7242
2025-04-27 04:45:40 [DEBUG] clck_gen.py:102 IND CLOCK 7344
2025-04-27 04:45:41 [DEBUG] clck_gen.py:102 IND CLOCK 7446
2025-04-27 04:45:41 [DEBUG] clck_gen.py:102 IND CLOCK 7548
2025-04-27 04:45:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:45:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:45:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:45:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:45:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:45:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:45:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:45:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:45:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:45:41 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:45:41 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:45:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD HANDOVER
2025-04-27 04:45:41 [DEBUG] clck_gen.py:102 IND CLOCK 7650
2025-04-27 04:45:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:45:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:45:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:45:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:45:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:45:42 [DEBUG] clck_gen.py:102 IND CLOCK 7752
2025-04-27 04:45:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:45:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:45:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:45:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:45:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:45:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:45:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:45:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:45:42 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:45:42 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:45:42 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:45:42 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:45:42 [DEBUG] clck_gen.py:102 IND CLOCK 7854
2025-04-27 04:45:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD HANDOVER
2025-04-27 04:45:42 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 04:45:42 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-27 04:45:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:45:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:45:43 [DEBUG] clck_gen.py:102 IND CLOCK 7956
2025-04-27 04:45:43 [DEBUG] clck_gen.py:102 IND CLOCK 8058
2025-04-27 04:45:44 [DEBUG] clck_gen.py:102 IND CLOCK 8160
2025-04-27 04:45:44 [DEBUG] clck_gen.py:102 IND CLOCK 8262
2025-04-27 04:45:45 [DEBUG] clck_gen.py:102 IND CLOCK 8364
2025-04-27 04:45:45 [DEBUG] clck_gen.py:102 IND CLOCK 8466
2025-04-27 04:45:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:45:46 [DEBUG] clck_gen.py:102 IND CLOCK 8568
2025-04-27 04:45:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:45:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:45:46 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:45:46 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:45:46 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 04:45:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:45:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:45:46 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:45:46 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:45:46 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:45:46 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:45:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD HANDOVER
2025-04-27 04:45:46 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 04:45:46 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-27 04:45:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:45:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:45:46 [DEBUG] clck_gen.py:102 IND CLOCK 8670
2025-04-27 04:45:47 [DEBUG] clck_gen.py:102 IND CLOCK 8772
2025-04-27 04:45:47 [DEBUG] clck_gen.py:102 IND CLOCK 8874
2025-04-27 04:45:48 [DEBUG] clck_gen.py:102 IND CLOCK 8976
2025-04-27 04:45:48 [DEBUG] clck_gen.py:102 IND CLOCK 9078
2025-04-27 04:45:49 [DEBUG] clck_gen.py:102 IND CLOCK 9180
2025-04-27 04:45:49 [DEBUG] clck_gen.py:102 IND CLOCK 9282
2025-04-27 04:45:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:45:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:45:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:45:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:45:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:45:49 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 04:45:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:45:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:45:49 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:45:49 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:45:49 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:45:49 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:45:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD HANDOVER
2025-04-27 04:45:50 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 04:45:50 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-27 04:45:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:45:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:45:50 [DEBUG] clck_gen.py:102 IND CLOCK 9384
2025-04-27 04:45:50 [DEBUG] clck_gen.py:102 IND CLOCK 9486
2025-04-27 04:45:51 [DEBUG] clck_gen.py:102 IND CLOCK 9588
2025-04-27 04:45:51 [DEBUG] clck_gen.py:102 IND CLOCK 9690
2025-04-27 04:45:51 [DEBUG] clck_gen.py:102 IND CLOCK 9792
2025-04-27 04:45:52 [DEBUG] clck_gen.py:102 IND CLOCK 9894
2025-04-27 04:45:52 [DEBUG] clck_gen.py:102 IND CLOCK 9996
2025-04-27 04:45:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:45:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:45:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:45:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:45:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:45:53 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 04:45:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:45:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:45:53 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:45:53 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:45:53 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:45:53 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:45:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD HANDOVER
2025-04-27 04:45:53 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 04:45:53 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-27 04:45:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:45:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:45:53 [DEBUG] clck_gen.py:102 IND CLOCK 10098
2025-04-27 04:45:53 [DEBUG] clck_gen.py:102 IND CLOCK 10200
2025-04-27 04:45:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:45:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:45:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:45:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:45:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:45:54 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 04:45:54 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:45:54 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:45:54 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:45:54 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:45:54 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:45:54 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:45:54 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:45:54 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:45:54 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=10290 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:45:54 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:45:54 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:45:54 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:45:54 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=10290 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:45:54 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=10290 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:45:54 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=10290 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:45:54 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=10291 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:45:54 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=10291 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:45:54 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=10291 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:45:54 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=10291 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:45:54 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=10291 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:45:54 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=10291 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:45:54 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=10291 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:45:54 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=10291 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:45:59 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:45:59 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:45:59 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:45:59 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:45:59 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:45:59 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:45:59 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:45:59 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:45:59 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:45:59 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:45:59 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:45:59 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:45:59 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:45:59 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:45:59 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:45:59 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:45:59 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:45:59 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:45:59 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:45:59 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:45:59 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:45:59 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:45:59 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:45:59 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:45:59 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:45:59 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:45:59 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:45:59 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:45:59 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:45:59 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:45:59 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:45:59 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:45:59 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:45:59 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:45:59 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:45:59 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:45:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:45:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:45:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:45:59 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:45:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:45:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:45:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:45:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:45:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:45:59 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:45:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:45:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:45:59 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:45:59 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:45:59 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:45:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:45:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:45:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:45:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:45:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:45:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:45:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:45:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:45:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:45:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:45:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:45:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:45:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:45:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:45:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:45:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:45:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:45:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:45:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:45:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:45:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:45:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:45:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:45:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:45:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:45:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:45:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:45:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:45:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:45:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:45:59 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:45:59 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:45:59 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:45:59 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:45:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:45:59 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:45:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:45:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:45:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:45:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:45:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:45:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:45:59 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:45:59 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:46:00 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:46:00 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:46:00 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:46:00 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:46:00 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:46:00 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:46:01 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:46:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:46:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:46:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:46:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:46:01 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 04:46:02 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 04:46:02 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:46:02 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:46:02 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:46:02 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:46:02 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 04:46:03 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 04:46:03 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:46:03 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:46:03 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:46:03 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:46:03 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 04:46:04 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 04:46:04 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:46:04 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:46:04 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:46:04 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:46:04 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 04:46:05 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 04:46:05 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 04:46:05 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 04:46:06 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 04:46:06 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 04:46:07 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 04:46:07 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 04:46:08 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 04:46:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:46:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:46:08 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:46:08 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:46:08 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:46:08 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:46:08 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:46:08 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:46:08 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:46:08 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:46:08 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:46:08 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2010 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:46:08 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:46:08 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:46:08 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2010 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:46:08 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2010 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:46:08 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2010 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:46:08 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2010 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:46:13 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:46:13 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:46:13 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:46:13 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:46:13 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:46:13 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:46:13 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:46:13 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:46:13 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:46:13 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:46:13 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:46:13 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:46:13 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:46:13 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:46:13 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:46:13 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:46:13 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:46:13 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:46:13 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:46:13 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:46:13 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:46:13 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:46:13 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:46:13 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:46:13 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:46:13 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:46:13 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:46:13 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:46:13 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:46:13 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:46:13 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:46:13 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:46:13 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:46:13 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:46:13 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:46:13 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:46:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:46:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:46:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:46:13 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:46:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:46:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:46:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:46:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:46:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:46:13 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:46:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:46:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:46:13 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:46:13 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:46:13 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:46:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:46:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:46:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:46:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:46:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:46:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:46:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:46:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:46:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:46:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:46:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:46:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:46:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:46:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:46:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:46:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:46:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:46:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:46:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:46:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:46:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:46:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:46:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:46:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:46:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:46:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:46:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:46:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:46:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:46:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:46:13 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:46:14 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:46:14 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:46:14 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:46:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:46:14 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:46:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:46:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:46:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:46:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:46:14 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:46:14 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:46:14 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:46:14 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:46:14 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:46:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:46:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:46:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:46:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:46:15 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:46:15 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:46:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:46:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:46:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:46:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:46:16 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 04:46:16 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 04:46:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:46:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:46:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:46:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:46:17 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 04:46:17 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 04:46:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:46:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:46:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:46:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:46:17 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 04:46:18 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 04:46:18 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:46:18 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:46:18 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:46:18 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:46:18 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 04:46:19 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 04:46:19 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 04:46:20 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 04:46:20 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 04:46:21 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 04:46:21 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 04:46:22 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 04:46:22 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 04:46:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:46:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:46:23 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:46:23 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:46:23 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:46:23 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:46:23 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:46:23 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:46:23 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:46:23 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:46:23 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:46:23 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:46:23 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:46:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2020 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:46:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2020 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:46:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2020 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:46:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2020 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:46:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2020 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:46:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2020 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:46:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2021 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:46:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2021 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:46:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2021 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:46:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2021 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:46:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2021 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:46:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2021 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:46:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2021 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:46:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2021 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:46:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2022 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:46:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2022 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:46:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2022 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:46:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2022 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:46:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2022 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:46:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2022 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:46:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2022 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:46:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2022 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:46:28 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:46:28 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:46:28 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:46:28 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:46:28 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:46:28 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:46:28 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:46:28 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:46:28 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:46:28 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:46:28 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:46:28 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:46:28 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:46:28 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:46:28 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:46:28 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:46:28 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:46:28 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:46:28 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:46:28 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:46:28 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:46:28 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:46:28 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:46:28 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:46:28 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:46:28 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:46:28 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:46:28 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:46:28 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:46:28 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:46:28 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:46:28 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:46:28 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:46:28 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:46:28 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:46:28 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:46:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:46:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:46:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:46:28 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:46:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:46:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:46:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:46:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:46:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:46:28 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:46:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:46:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:46:28 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:46:28 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:46:28 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:46:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:46:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:46:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:46:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:46:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:46:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:46:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:46:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:46:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:46:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:46:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:46:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:46:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:46:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:46:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:46:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:46:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:46:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:46:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:46:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:46:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:46:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:46:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:46:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:46:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:46:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:46:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:46:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:46:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:46:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:46:28 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:46:28 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:46:28 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:46:28 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:46:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:46:28 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:46:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:46:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:46:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:46:29 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:46:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:46:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:46:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:46:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:46:29 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:46:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:46:29 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:46:29 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:46:29 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:46:29 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:46:30 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:46:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:46:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:46:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:46:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:46:30 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 04:46:30 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 04:46:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:46:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:46:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:46:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:46:31 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 04:46:31 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 04:46:32 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:46:32 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:46:32 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:46:32 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:46:32 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 04:46:32 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 04:46:33 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:46:33 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:46:33 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:46:33 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:46:33 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 04:46:33 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 04:46:34 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 04:46:34 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 04:46:35 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 04:46:35 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 04:46:36 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 04:46:36 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 04:46:37 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 04:46:37 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 04:46:38 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 04:46:38 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 04:46:39 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-27 04:46:39 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-27 04:46:39 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-27 04:46:40 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-27 04:46:40 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-27 04:46:41 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-27 04:46:41 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:46:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:46:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:46:41 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:46:41 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:46:41 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:46:41 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:46:41 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:46:41 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:46:41 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:46:41 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:46:41 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:46:41 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:46:41 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2873 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:46:41 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2873 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:46:41 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2873 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:46:41 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2874 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:46:41 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2874 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:46:41 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2874 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:46:41 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2874 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:46:41 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2874 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:46:41 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2874 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:46:41 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2874 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:46:41 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2874 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:46:41 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2875 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:46:41 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2875 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:46:41 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2875 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:46:41 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2875 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:46:41 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2875 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:46:41 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2875 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:46:41 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2875 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:46:41 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2875 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:46:41 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2876 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:46:41 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2876 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:46:41 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2876 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:46:41 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2876 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:46:41 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2876 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:46:41 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2876 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:46:41 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2876 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:46:41 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2876 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:46:46 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:46:46 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:46:46 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:46:46 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:46:46 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:46:46 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:46:46 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:46:46 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:46:46 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:46:46 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:46:46 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:46:46 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:46:46 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:46:46 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:46:46 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:46:46 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:46:46 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:46:46 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:46:46 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:46:46 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:46:46 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:46:46 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:46:46 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:46:46 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:46:46 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:46:46 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:46:46 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:46:46 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:46:46 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:46:46 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:46:46 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:46:46 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:46:46 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:46:46 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:46:46 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:46:46 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:46:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:46:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:46:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:46:46 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:46:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:46:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:46:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:46:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:46:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:46:46 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:46:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:46:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:46:46 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:46:46 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:46:46 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:46:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:46:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:46:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:46:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:46:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:46:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:46:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:46:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:46:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:46:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:46:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:46:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:46:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:46:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:46:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:46:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:46:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:46:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:46:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:46:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:46:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:46:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:46:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:46:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:46:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:46:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:46:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:46:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:46:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:46:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:46:46 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:46:47 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:46:47 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:46:47 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:46:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:46:47 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:46:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:46:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:46:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:46:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:46:47 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:46:47 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:46:47 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:46:47 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:46:47 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:46:47 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:46:47 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:46:47 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:46:47 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:46:47 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:46:48 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:46:48 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:46:48 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:46:48 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:46:48 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:46:48 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:46:48 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:46:48 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 04:46:49 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:46:49 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 04:46:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:46:49 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:46:49 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:46:49 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:46:49 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 04:46:50 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 04:46:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:46:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:46:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:46:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:46:50 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 04:46:51 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:46:51 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 04:46:51 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:46:51 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:46:51 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:46:51 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:46:51 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:46:51 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 04:46:52 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:46:52 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 04:46:52 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:46:52 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 04:46:53 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 04:46:53 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 04:46:54 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 04:46:54 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:46:54 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 04:46:55 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 04:46:55 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 04:46:56 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 04:46:56 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 04:46:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:46:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:46:56 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:46:56 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:46:56 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:46:56 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:46:56 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:46:56 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:46:56 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:46:56 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:46:56 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:46:56 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:46:56 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:46:56 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2171 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:46:56 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2171 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:46:56 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2171 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:46:56 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2171 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:46:56 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2171 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:46:56 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2171 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:47:01 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:47:01 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:47:01 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:47:01 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:47:01 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:47:01 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:47:01 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:47:01 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:47:01 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:47:01 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:47:01 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:47:01 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:47:01 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:47:01 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:47:01 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:47:01 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:47:01 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:47:01 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:47:01 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:47:01 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:47:01 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:47:01 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:47:01 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:47:01 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:47:01 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:47:01 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:47:01 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:47:01 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:47:01 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:47:01 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:47:01 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:47:01 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:47:01 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:47:01 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:47:01 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:47:01 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:47:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:47:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:47:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:47:01 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:47:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:47:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:47:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:47:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:47:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:47:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:47:01 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:47:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:47:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:47:01 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:47:01 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:47:01 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:47:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:47:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:47:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:47:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:47:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:47:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:47:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:47:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:47:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:47:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:47:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:47:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:47:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:47:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:47:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:47:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:47:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:47:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:47:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:47:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:47:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:47:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:47:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:47:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:47:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:47:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:47:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:47:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:47:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:47:01 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:47:02 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:47:02 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:47:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:47:02 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:47:02 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:47:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:47:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:47:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:47:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:47:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:47:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:47:02 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:47:02 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:47:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD HANDOVER
2025-04-27 04:47:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:47:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:47:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:47:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:47:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:47:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:47:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:47:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:47:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:47:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:47:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:47:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:47:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:47:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:47:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:47:02 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:47:02 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:47:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD HANDOVER
2025-04-27 04:47:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:47:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:47:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:47:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:47:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:47:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:47:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:47:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:47:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:47:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:47:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:47:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:47:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:47:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:47:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:47:02 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:47:02 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:47:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD HANDOVER
2025-04-27 04:47:02 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:47:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:47:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:47:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:47:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:47:02 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:47:02 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:47:02 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:47:02 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:47:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:47:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:47:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:47:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:47:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:47:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:47:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:47:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:47:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:47:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:47:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:47:02 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:47:02 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD HANDOVER
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:47:03 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:47:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:47:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:47:03 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD HANDOVER
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:47:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:47:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:47:03 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD HANDOVER
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 04:47:03 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:47:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:47:03 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:47:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:47:03 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD HANDOVER
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 04:47:03 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=3, maio=3, ma_len=4
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:47:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:47:03 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:47:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:47:03 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD HANDOVER
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:47:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:47:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:47:03 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD HANDOVER
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:47:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:47:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:47:03 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD HANDOVER
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:47:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:47:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:47:03 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD HANDOVER
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 04:47:03 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:47:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:47:03 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:47:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:47:03 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD HANDOVER
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 04:47:03 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:47:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:47:03 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:47:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:47:03 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:47:03 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD HANDOVER
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 04:47:03 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:47:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:47:03 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:47:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:47:03 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD HANDOVER
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 04:47:03 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:47:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:47:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:47:03 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 04:47:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:47:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:47:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:47:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:47:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:47:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:47:04 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:47:04 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:47:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD HANDOVER
2025-04-27 04:47:04 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 04:47:04 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-27 04:47:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:47:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:47:04 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 04:47:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:47:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:47:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:47:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:47:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:47:04 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 04:47:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:47:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:47:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:47:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:47:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:47:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:47:04 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:47:04 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:47:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD HANDOVER
2025-04-27 04:47:04 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 04:47:04 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-27 04:47:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:47:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:47:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:47:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:47:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:47:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:47:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:47:04 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 04:47:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:47:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:47:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:47:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:47:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:47:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:47:04 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:47:04 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:47:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD HANDOVER
2025-04-27 04:47:04 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 04:47:04 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-27 04:47:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:47:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:47:04 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 04:47:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:47:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:47:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:47:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:47:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:47:04 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 04:47:04 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:47:04 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:47:04 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:47:04 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:47:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:47:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:47:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:47:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:47:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:47:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:47:04 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:47:04 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:47:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD HANDOVER
2025-04-27 04:47:04 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 04:47:04 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-27 04:47:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:47:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:47:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:47:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:47:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:47:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:47:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:47:05 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 04:47:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:47:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:47:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:47:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:47:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:47:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:47:05 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:47:05 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:47:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD HANDOVER
2025-04-27 04:47:05 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 04:47:05 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 04:47:05 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-27 04:47:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:47:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:47:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:47:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:47:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:47:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:47:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:47:05 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 04:47:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:47:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:47:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:47:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:47:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:47:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:47:05 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:47:05 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:47:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD HANDOVER
2025-04-27 04:47:05 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 04:47:05 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-27 04:47:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:47:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:47:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:47:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:47:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:47:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:47:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:47:05 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 04:47:05 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:47:05 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:47:05 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:47:05 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:47:05 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:47:05 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:47:05 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:47:05 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:47:05 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:47:05 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:47:05 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:47:05 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=811 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:47:05 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=811 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:47:05 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=811 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:47:05 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=811 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:47:05 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=811 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:47:10 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:47:10 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:47:10 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:47:10 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:47:10 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:47:10 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:47:10 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:47:10 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:47:10 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:47:10 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:47:10 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:47:10 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:47:10 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:47:10 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:47:10 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:47:10 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:47:10 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:47:10 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:47:10 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:47:10 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:47:10 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:47:10 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:47:10 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:47:10 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:47:10 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:47:10 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:47:10 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:47:10 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:47:10 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:47:10 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:47:10 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:47:10 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:47:10 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:47:10 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:47:10 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:47:10 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:47:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:47:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:47:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:47:10 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:47:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:47:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:47:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:47:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:47:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:47:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:47:10 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:47:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:47:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:47:10 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:47:10 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:47:10 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:47:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:47:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:47:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:47:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:47:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:47:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:47:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:47:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:47:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:47:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:47:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:47:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:47:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:47:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:47:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:47:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:47:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:47:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:47:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:47:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:47:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:47:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:47:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:47:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:47:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:47:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:47:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:47:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:47:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:47:10 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:47:11 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:47:11 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:47:11 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:47:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:47:11 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:47:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:47:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:47:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:47:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:47:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:47:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:47:11 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:47:11 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:47:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD HANDOVER
2025-04-27 04:47:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:47:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:47:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:47:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:47:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:47:11 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:47:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:47:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:47:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:47:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:47:12 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:47:12 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:47:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:47:12 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:47:12 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:47:12 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:47:12 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 04:47:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:47:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:47:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:47:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:47:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:47:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:47:13 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:47:13 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:47:13 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:47:13 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:47:13 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:47:13 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=561 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:47:13 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:47:13 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:47:13 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=561 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:47:13 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=561 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:47:13 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=562 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:47:13 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=562 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:47:13 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=562 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:47:13 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=562 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:47:13 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=562 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:47:13 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=562 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:47:13 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=562 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:47:13 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=562 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:47:18 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:47:18 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:47:18 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:47:18 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:47:18 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:47:18 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:47:18 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:47:18 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:47:18 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:47:18 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:47:18 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:47:18 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:47:18 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:47:18 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:47:18 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:47:18 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:47:18 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:47:18 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:47:18 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:47:18 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:47:18 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:47:18 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:47:18 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:47:18 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:47:18 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:47:18 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:47:18 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:47:18 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:47:18 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:47:18 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:47:18 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:47:18 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:47:18 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:47:18 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:47:18 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:47:18 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:47:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:47:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:47:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:47:18 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:47:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:47:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:47:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:47:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:47:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:47:18 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:47:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:47:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:47:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:47:18 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:47:18 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:47:18 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:47:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:47:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:47:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:47:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:47:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:47:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:47:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:47:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:47:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:47:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:47:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:47:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:47:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:47:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:47:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:47:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:47:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:47:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:47:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:47:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:47:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:47:18 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:47:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:47:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:47:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:47:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:47:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:47:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:47:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:47:18 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:47:18 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:47:18 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:47:18 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:47:18 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:47:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:47:23 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:47:23 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:47:23 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:47:23 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:47:23 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:47:23 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:47:23 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:47:23 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:47:23 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:47:23 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:47:23 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:47:23 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:47:23 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:47:23 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:47:23 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:47:23 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:47:23 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:47:23 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:47:23 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:47:23 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:47:23 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:47:23 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:47:23 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:47:23 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:47:23 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:47:23 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:47:23 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:47:23 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:47:23 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:47:23 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:47:23 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:47:23 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:47:23 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:47:23 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:47:23 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:47:23 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:47:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:47:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:47:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:47:23 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:47:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:47:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:47:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:47:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:47:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:47:23 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:47:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:47:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:47:23 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:47:23 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:47:23 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:47:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:47:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:47:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:47:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:47:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:47:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:47:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:47:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:47:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:47:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:47:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:47:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:47:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:47:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:47:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:47:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:47:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:47:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:47:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:47:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:47:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:47:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:47:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:47:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:47:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:47:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:47:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:47:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:47:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:47:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:47:23 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:47:23 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:47:23 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:47:23 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:47:23 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:47:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:47:24 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:47:24 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:47:24 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:47:24 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:47:24 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:47:24 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:47:25 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:47:25 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:47:25 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:47:25 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:47:25 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:47:25 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 04:47:26 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 04:47:26 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:47:26 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:47:26 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:47:26 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:47:26 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 04:47:27 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 04:47:27 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:47:27 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:47:27 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:47:27 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:47:27 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 04:47:28 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 04:47:28 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:47:28 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:47:28 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:47:28 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:47:28 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 04:47:28 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 04:47:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:47:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:47:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:47:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:47:29 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:47:29 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:47:29 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:47:29 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:47:29 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:47:29 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:47:29 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:47:29 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1294 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:47:29 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1294 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:47:29 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1294 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:47:29 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1294 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:47:29 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1294 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:47:29 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1294 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:47:34 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:47:34 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:47:34 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:47:34 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:47:34 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:47:34 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:47:34 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:47:34 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:47:34 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:47:34 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:47:34 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:47:34 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:47:34 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:47:34 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:47:34 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:47:34 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:47:34 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:47:34 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:47:34 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:47:34 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:47:34 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:47:34 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:47:34 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:47:34 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:47:34 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:47:34 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:47:34 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:47:34 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:47:34 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:47:34 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:47:34 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:47:34 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:47:34 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:47:34 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:47:34 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:47:34 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:47:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:47:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:47:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:47:34 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:47:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:47:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:47:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:47:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:47:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:47:34 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:47:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:47:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:47:34 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:47:34 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:47:34 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:47:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:47:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:47:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:47:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:47:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:47:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:47:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:47:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:47:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:47:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:47:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:47:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:47:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:47:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:47:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:47:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:47:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:47:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:47:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:47:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:47:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:47:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:47:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:47:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:47:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:47:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:47:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:47:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:47:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:47:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:47:34 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:47:34 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:47:34 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:47:34 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:47:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:47:34 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:47:35 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:47:35 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:47:35 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:47:35 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:47:35 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:47:35 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:47:36 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:47:36 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:47:36 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:47:36 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:47:36 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:47:36 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 04:47:37 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 04:47:37 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:47:37 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:47:37 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:47:37 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:47:37 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 04:47:38 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 04:47:38 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:47:38 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:47:38 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:47:38 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:47:38 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 04:47:39 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 04:47:39 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:47:39 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:47:39 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:47:39 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:47:39 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 04:47:39 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:47:39 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:47:39 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:47:39 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:47:39 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:47:39 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:47:39 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:47:39 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:47:39 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:47:39 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:47:39 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:47:44 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:47:44 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:47:44 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:47:44 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:47:44 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:47:44 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:47:44 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:47:44 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:47:44 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:47:44 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:47:44 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:47:44 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:47:44 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:47:44 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:47:44 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:47:44 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:47:44 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:47:44 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:47:44 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:47:44 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:47:44 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:47:44 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:47:44 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:47:44 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:47:44 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:47:44 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:47:44 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:47:44 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:47:44 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:47:44 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:47:44 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:47:44 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:47:44 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:47:44 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:47:44 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:47:44 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:47:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:47:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:47:44 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:47:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:47:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:47:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:47:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:47:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:47:44 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:47:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:47:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:47:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:47:44 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:47:44 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:47:44 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:47:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:47:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:47:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:47:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:47:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:47:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:47:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:47:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:47:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:47:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:47:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:47:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:47:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:47:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:47:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:47:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:47:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:47:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:47:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:47:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:47:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:47:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:47:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:47:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:47:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:47:44 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:47:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:47:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:47:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:47:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:47:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:47:44 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:47:44 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:47:44 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:47:44 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:47:44 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:47:44 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:47:49 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:47:49 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:47:49 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:47:49 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:47:49 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:47:49 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:47:49 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:47:49 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:47:49 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:47:49 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:47:49 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:47:49 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:47:49 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:47:49 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:47:49 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:47:49 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:47:49 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:47:49 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:47:49 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:47:49 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:47:49 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:47:49 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:47:49 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:47:49 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:47:49 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:47:49 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:47:49 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:47:49 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:47:49 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:47:49 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:47:49 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:47:49 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:47:49 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:47:49 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:47:49 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:47:49 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:47:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:47:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:47:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:47:49 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:47:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:47:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:47:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:47:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:47:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:47:49 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:47:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:47:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:47:49 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:47:49 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:47:49 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:47:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:47:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:47:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:47:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:47:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:47:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:47:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:47:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:47:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:47:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:47:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:47:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:47:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:47:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:47:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:47:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:47:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:47:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:47:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:47:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:47:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:47:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:47:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:47:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:47:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:47:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:47:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:47:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:47:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:47:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:47:49 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:47:50 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:47:50 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:47:50 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:47:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:47:50 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:47:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:47:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:47:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:47:50 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:47:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:47:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:47:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:47:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:47:51 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:47:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:47:51 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:47:51 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:47:51 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:47:51 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:47:51 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:47:51 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:47:51 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:47:51 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:47:51 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:47:52 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 04:47:52 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 04:47:52 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:47:52 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:47:52 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:47:52 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:47:53 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 04:47:53 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 04:47:53 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:47:53 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:47:53 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:47:53 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:47:54 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 04:47:54 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 04:47:54 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:47:54 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:47:54 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:47:54 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:47:55 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 04:47:55 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 04:47:56 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 04:47:56 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 04:47:57 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 04:47:57 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 04:47:58 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 04:47:58 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 04:47:58 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 04:47:59 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 04:47:59 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 04:48:00 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 04:48:00 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-27 04:48:01 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-27 04:48:01 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-27 04:48:02 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-27 04:48:02 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-27 04:48:03 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-27 04:48:03 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-27 04:48:04 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-27 04:48:04 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-27 04:48:05 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-27 04:48:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:48:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:48:05 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:48:05 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:48:05 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:48:05 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:48:05 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:48:05 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:48:05 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:48:05 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:48:05 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:48:05 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:48:05 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:48:05 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3312 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:48:05 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3312 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:48:05 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3312 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:48:05 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3312 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:48:05 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3312 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:48:05 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3312 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:48:05 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3312 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:48:05 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3312 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:48:10 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:48:10 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:48:10 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:48:10 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:48:10 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:48:10 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:48:10 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:48:10 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:48:10 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:48:10 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:48:10 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:48:10 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:48:10 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:48:10 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:48:10 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:48:10 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:48:10 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:48:10 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:48:10 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:48:10 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:48:10 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:48:10 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:48:10 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:48:10 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:48:10 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:48:10 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:48:10 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:48:10 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:48:10 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:48:10 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:48:10 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:48:10 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:48:10 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:48:10 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:48:10 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:48:10 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:48:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:48:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:48:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:48:10 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:48:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:48:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:48:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:48:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:48:10 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:48:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:48:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:48:10 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:48:10 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:48:10 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:48:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:48:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:48:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:48:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:48:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:48:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:48:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:48:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:48:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:48:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:48:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:48:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:48:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:48:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:48:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:48:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:48:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:48:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:48:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:48:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:48:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:48:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:48:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:48:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:48:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:48:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:48:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:48:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:48:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:48:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:48:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:48:10 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:48:10 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:48:10 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:48:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:48:10 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:48:10 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:48:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:48:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:48:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:48:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:48:10 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:48:10 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:48:10 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:48:10 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:48:10 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:48:10 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:48:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:48:10 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:48:10 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:48:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:48:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:48:11 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:48:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:48:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:48:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:48:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:48:11 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:48:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:48:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:48:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:48:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:48:11 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:48:11 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:48:11 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:48:11 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:48:11 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:48:11 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:48:11 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=313 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:48:11 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=313 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:48:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:48:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:48:11 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:48:11 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=313 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:48:11 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=313 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:48:11 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=313 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:48:11 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=313 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:48:11 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=314 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:48:11 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=314 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:48:11 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=314 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:48:11 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=314 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:48:11 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=314 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:48:11 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=314 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:48:11 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=314 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:48:11 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=314 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:48:16 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:48:16 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:48:16 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:48:16 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:48:16 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:48:16 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:48:16 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:48:16 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:48:16 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:48:16 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:48:16 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:48:16 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:48:16 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:48:16 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:48:16 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:48:16 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:48:16 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:48:16 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:48:16 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:48:16 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:48:16 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:48:16 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:48:16 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:48:16 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:48:16 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:48:16 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:48:16 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:48:16 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:48:16 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:48:16 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:48:16 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:48:16 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:48:16 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:48:16 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:48:16 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:48:16 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:48:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:48:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:48:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:48:16 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:48:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:48:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:48:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:48:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:48:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:48:16 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:48:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:48:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:48:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:48:16 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:48:16 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:48:16 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:48:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:48:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:48:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:48:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:48:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:48:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:48:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:48:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:48:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:48:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:48:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:48:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:48:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:48:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:48:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:48:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:48:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:48:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:48:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:48:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:48:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:48:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:48:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:48:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:48:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:48:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:48:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:48:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:48:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:48:16 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:48:17 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:48:17 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:48:17 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:48:17 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:48:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:48:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:48:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:48:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:48:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:48:17 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:48:17 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:48:17 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:48:17 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:48:17 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:48:17 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:48:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:48:17 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:48:17 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:48:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:48:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:48:17 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:48:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:48:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:48:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:48:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:48:18 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:48:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:48:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:48:18 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:48:18 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:48:18 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:48:18 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:48:18 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:48:18 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:48:18 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:48:18 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:48:18 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:48:18 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:48:18 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:48:18 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=313 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:48:18 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=313 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:48:18 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=313 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:48:18 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=313 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:48:18 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=314 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:48:18 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=314 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:48:18 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=314 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:48:18 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=314 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:48:18 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=314 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:48:18 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=314 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:48:18 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=314 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:48:18 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=314 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:48:23 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:48:23 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:48:23 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:48:23 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:48:23 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:48:23 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:48:23 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:48:23 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:48:23 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:48:23 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:48:23 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:48:23 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:48:23 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:48:23 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:48:23 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:48:23 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:48:23 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:48:23 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:48:23 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:48:23 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:48:23 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:48:23 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:48:23 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:48:23 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:48:23 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:48:23 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:48:23 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:48:23 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:48:23 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:48:23 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:48:23 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:48:23 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:48:23 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:48:23 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:48:23 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:48:23 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:48:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:48:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:48:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:48:23 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:48:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:48:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:48:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:48:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:48:23 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:48:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:48:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:48:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:48:23 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:48:23 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:48:23 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:48:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:48:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:48:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:48:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:48:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:48:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:48:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:48:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:48:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:48:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:48:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:48:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:48:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:48:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:48:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:48:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:48:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:48:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:48:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:48:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:48:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:48:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:48:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:48:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:48:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:48:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:48:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:48:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:48:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:48:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:48:23 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:48:23 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:48:23 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:48:23 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:48:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:48:23 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:48:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:48:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:48:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:48:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:48:23 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:48:23 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:48:23 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:48:23 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:48:23 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:48:23 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:48:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:48:23 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 04:48:23 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-27 04:48:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:48:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:48:24 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:48:24 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:48:24 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:48:24 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:48:24 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:48:24 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:48:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:48:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:48:25 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 04:48:25 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:48:25 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:48:25 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:48:25 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:48:25 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:48:25 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:48:25 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:48:25 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:48:25 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:48:25 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:48:25 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:48:30 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:48:30 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:48:30 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:48:30 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:48:30 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:48:30 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:48:30 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:48:30 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:48:30 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:48:30 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:48:30 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:48:30 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:48:30 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:48:30 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:48:30 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:48:30 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:48:30 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:48:30 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:48:30 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:48:30 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:48:30 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:48:30 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:48:30 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:48:30 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:48:30 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:48:30 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:48:30 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:48:30 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:48:30 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:48:30 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:48:30 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:48:30 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:48:30 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:48:30 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:48:30 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:48:30 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:48:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:48:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:48:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:48:30 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:48:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:48:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:48:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:48:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:48:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:48:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:48:30 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:48:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:48:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:48:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:48:30 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:48:30 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:48:30 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:48:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:48:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:48:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:48:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:48:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:48:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:48:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:48:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:48:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:48:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:48:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:48:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:48:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:48:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:48:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:48:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:48:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:48:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:48:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:48:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:48:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:48:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:48:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:48:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:48:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:48:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:48:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:48:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:48:30 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:48:30 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:48:30 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:48:30 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:48:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:48:30 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:48:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:48:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:48:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:48:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:48:30 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:48:30 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:48:30 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:48:30 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:48:30 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:48:30 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:48:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:48:30 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 04:48:30 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-27 04:48:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:48:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:48:31 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:48:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:48:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:48:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:48:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:48:31 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:48:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:48:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:48:31 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 04:48:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:48:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:48:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:48:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:48:31 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:48:31 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:48:31 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:48:31 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:48:31 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:48:31 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:48:31 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:48:31 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=354 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:48:31 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=354 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:48:31 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=354 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:48:31 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=354 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:48:31 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=354 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:48:31 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=354 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:48:31 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=354 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:48:36 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:48:36 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:48:36 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:48:36 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:48:36 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:48:36 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:48:36 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:48:36 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:48:36 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:48:36 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:48:36 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:48:36 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:48:36 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:48:36 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:48:36 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:48:36 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:48:36 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:48:36 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:48:36 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:48:36 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:48:36 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:48:36 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:48:36 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:48:36 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:48:36 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:48:36 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:48:36 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:48:36 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:48:36 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:48:36 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:48:36 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:48:36 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:48:36 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:48:36 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:48:36 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:48:36 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:48:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:48:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:48:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:48:36 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:48:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:48:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:48:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:48:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:48:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:48:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:48:36 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:48:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:48:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:48:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:48:36 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:48:36 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:48:36 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:48:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:48:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:48:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:48:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:48:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:48:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:48:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:48:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:48:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:48:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:48:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:48:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:48:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:48:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:48:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:48:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:48:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:48:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:48:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:48:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:48:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:48:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:48:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:48:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:48:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:48:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:48:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:48:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:48:36 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:48:37 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:48:37 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:48:37 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:48:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:48:37 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:48:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:48:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:48:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:48:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:48:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:48:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:48:37 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:48:37 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:48:37 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:48:37 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:48:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:48:37 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 04:48:37 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-27 04:48:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:48:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:48:37 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:48:37 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:48:37 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:48:37 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:48:37 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:48:38 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:48:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:48:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:48:38 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 04:48:38 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:48:38 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:48:38 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:48:38 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:48:38 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:48:38 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:48:38 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:48:38 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:48:38 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:48:38 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:48:38 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:48:38 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=352 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:48:38 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=352 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:48:38 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=352 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:48:38 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=352 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:48:38 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=352 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:48:38 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=353 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:48:38 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=353 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:48:38 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=353 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:48:38 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=353 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:48:38 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=353 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:48:38 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=353 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:48:38 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=353 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:48:38 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=353 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:48:43 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:48:43 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:48:43 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:48:43 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:48:43 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:48:43 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:48:43 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:48:43 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:48:43 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:48:43 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:48:43 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:48:43 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:48:43 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:48:43 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:48:43 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:48:43 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:48:43 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:48:43 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:48:43 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:48:43 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:48:43 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:48:43 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:48:43 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:48:43 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:48:43 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:48:43 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:48:43 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:48:43 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:48:43 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:48:43 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:48:43 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:48:43 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:48:43 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:48:43 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:48:43 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:48:43 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:48:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:48:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:48:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:48:43 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:48:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:48:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:48:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:48:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:48:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:48:43 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:48:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:48:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:48:43 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:48:43 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:48:43 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:48:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:48:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:48:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:48:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:48:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:48:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:48:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:48:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:48:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:48:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:48:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:48:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:48:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:48:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:48:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:48:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:48:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:48:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:48:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:48:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:48:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:48:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:48:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:48:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:48:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:48:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:48:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:48:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:48:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:48:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:48:43 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:48:43 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:48:43 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:48:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:48:43 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:48:43 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:48:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:48:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:48:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:48:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:48:43 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:48:43 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:48:43 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:48:43 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:48:44 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:48:44 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:48:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:48:44 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:48:44 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:48:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:48:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:48:44 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:48:44 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:48:44 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:48:44 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:48:44 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:48:44 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:48:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:48:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:48:44 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:48:44 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:48:44 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:48:44 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:48:44 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:48:44 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:48:44 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:48:44 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:48:44 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:48:44 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:48:44 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:48:44 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=315 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:48:44 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=315 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:48:44 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=315 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:48:44 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=315 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:48:44 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=315 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:48:44 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=315 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:48:44 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=315 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:48:49 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:48:49 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:48:49 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:48:49 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:48:49 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:48:49 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:48:49 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:48:49 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:48:49 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:48:49 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:48:49 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:48:49 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:48:49 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:48:49 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:48:49 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:48:49 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:48:49 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:48:49 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:48:49 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:48:49 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:48:49 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:48:49 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:48:49 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:48:49 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:48:49 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:48:49 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:48:49 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:48:49 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:48:49 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:48:49 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:48:49 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:48:49 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:48:49 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:48:49 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:48:49 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:48:49 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:48:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:48:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:48:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:48:49 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:48:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:48:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:48:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:48:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:48:49 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:48:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:48:49 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:48:49 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:48:49 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:48:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:48:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:48:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:48:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:48:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:48:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:48:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:48:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:48:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:48:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:48:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:48:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:48:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:48:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:48:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:48:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:48:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:48:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:48:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:48:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:48:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:48:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:48:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:48:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:48:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:48:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:48:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:48:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:48:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:48:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:48:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:48:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:48:49 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:48:50 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:48:50 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:48:50 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:48:50 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:48:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:48:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:48:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:48:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:48:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:48:50 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:48:50 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:48:50 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:48:50 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:48:50 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:48:50 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:48:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:48:50 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 04:48:50 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-27 04:48:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:48:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:48:50 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:48:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:48:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:48:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:48:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:48:51 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:48:51 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:48:51 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:48:51 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 04:48:51 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:48:51 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:48:51 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:48:51 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:48:51 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:48:51 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:48:51 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:48:51 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:48:51 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:48:51 [WARNING] transceiver.py:250 (TRX2@172.18.127.20:5700/2) RX TRXD message (ver=1 fn=353 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:48:51 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:48:51 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:48:51 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=352 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:48:51 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=352 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:48:51 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=352 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:48:51 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=352 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:48:51 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=352 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:48:51 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=352 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:48:51 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=352 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:48:51 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=353 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:48:51 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=353 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:48:51 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=353 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:48:51 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=353 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:48:51 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=353 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:48:51 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=353 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:48:51 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=353 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:48:51 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=353 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:48:56 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:48:56 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:48:56 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:48:56 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:48:56 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:48:56 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:48:56 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:48:56 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:48:56 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:48:56 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:48:56 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:48:56 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:48:56 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:48:56 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:48:56 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:48:56 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:48:56 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:48:56 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:48:56 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:48:56 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:48:56 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:48:56 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:48:56 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:48:56 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:48:56 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:48:56 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:48:56 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:48:56 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:48:56 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:48:56 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:48:56 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:48:56 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:48:56 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:48:56 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:48:56 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:48:56 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:48:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:48:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:48:56 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:48:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:48:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:48:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:48:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:48:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:48:56 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:48:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:48:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:48:56 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:48:56 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:48:56 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:48:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:48:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:48:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:48:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:48:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:48:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:48:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:48:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:48:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:48:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:48:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:48:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:48:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:48:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:48:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:48:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:48:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:48:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:48:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:48:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:48:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:48:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:48:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:48:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:48:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:48:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:48:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:48:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:48:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:48:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:48:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:48:56 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:48:57 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:48:57 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:48:57 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:48:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:48:57 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:48:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:48:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:48:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:48:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:48:57 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:48:57 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:48:57 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:48:57 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:48:57 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:48:57 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:48:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:48:57 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:48:57 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:48:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:48:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:48:57 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:48:57 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:48:57 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:48:57 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:48:57 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:48:58 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:48:58 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:48:58 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:48:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:48:58 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:48:58 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:48:59 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 04:48:59 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 04:48:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:48:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:48:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:48:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:48:59 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 04:49:00 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 04:49:00 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:49:00 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:49:00 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:49:00 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:49:00 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 04:49:01 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 04:49:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:49:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:49:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:49:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:49:01 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 04:49:02 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 04:49:02 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 04:49:03 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 04:49:03 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 04:49:04 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 04:49:04 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 04:49:05 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 04:49:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:49:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:49:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:49:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:49:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:49:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:49:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:49:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:49:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:49:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:49:05 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:49:05 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:49:05 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:49:05 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:49:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:49:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:49:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:49:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:49:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:49:05 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 04:49:06 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 04:49:06 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 04:49:07 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 04:49:07 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-27 04:49:08 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-27 04:49:08 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-27 04:49:09 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-27 04:49:09 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-27 04:49:09 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-27 04:49:10 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-27 04:49:10 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-27 04:49:11 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-27 04:49:11 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-27 04:49:12 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-27 04:49:12 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-27 04:49:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:49:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:49:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:49:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:49:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:49:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:49:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:49:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:49:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:49:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:49:13 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:49:13 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:49:13 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:49:13 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:49:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:49:13 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-27 04:49:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:49:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:49:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:49:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:49:13 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-27 04:49:14 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-27 04:49:14 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-27 04:49:15 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2025-04-27 04:49:15 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2025-04-27 04:49:16 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2025-04-27 04:49:16 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2025-04-27 04:49:17 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2025-04-27 04:49:17 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2025-04-27 04:49:18 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2025-04-27 04:49:18 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2025-04-27 04:49:18 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2025-04-27 04:49:19 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2025-04-27 04:49:19 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2025-04-27 04:49:20 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2025-04-27 04:49:20 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2025-04-27 04:49:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:49:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:49:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:49:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:49:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:49:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:49:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:49:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:49:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:49:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:49:21 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:49:21 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:49:21 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:49:21 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:49:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:49:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:49:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:49:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:49:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:49:21 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2025-04-27 04:49:21 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2025-04-27 04:49:22 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2025-04-27 04:49:22 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2025-04-27 04:49:23 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2025-04-27 04:49:23 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2025-04-27 04:49:24 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2025-04-27 04:49:24 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2025-04-27 04:49:25 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2025-04-27 04:49:25 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2025-04-27 04:49:26 [DEBUG] clck_gen.py:102 IND CLOCK 6324
2025-04-27 04:49:26 [DEBUG] clck_gen.py:102 IND CLOCK 6426
2025-04-27 04:49:27 [DEBUG] clck_gen.py:102 IND CLOCK 6528
2025-04-27 04:49:27 [DEBUG] clck_gen.py:102 IND CLOCK 6630
2025-04-27 04:49:28 [DEBUG] clck_gen.py:102 IND CLOCK 6732
2025-04-27 04:49:28 [DEBUG] clck_gen.py:102 IND CLOCK 6834
2025-04-27 04:49:29 [DEBUG] clck_gen.py:102 IND CLOCK 6936
2025-04-27 04:49:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:49:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:49:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:49:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:49:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:49:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:49:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:49:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:49:29 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:49:29 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:49:29 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:49:29 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:49:29 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:49:29 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:49:29 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:49:29 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=7017 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:49:29 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=7017 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:49:29 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=7017 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:49:29 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=7017 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:49:29 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=7017 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:49:29 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=7017 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:49:34 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:49:34 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:49:34 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:49:34 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:49:34 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:49:34 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:49:34 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:49:34 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:49:34 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:49:34 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:49:34 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:49:34 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:49:34 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:49:34 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:49:34 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:49:34 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:49:34 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:49:34 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:49:34 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:49:34 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:49:34 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:49:34 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:49:34 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:49:34 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:49:34 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:49:34 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:49:34 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:49:34 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:49:34 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:49:34 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:49:34 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:49:34 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:49:34 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:49:34 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:49:34 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:49:34 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:49:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:49:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:49:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:49:34 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:49:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:49:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:49:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:49:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:49:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:49:34 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:49:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:49:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:49:34 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:49:34 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:49:34 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:49:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:49:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:49:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:49:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:49:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:49:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:49:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:49:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:49:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:49:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:49:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:49:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:49:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:49:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:49:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:49:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:49:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:49:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:49:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:49:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:49:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:49:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:49:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:49:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:49:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:49:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:49:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:49:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:49:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:49:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:49:34 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:49:34 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:49:34 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:49:34 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:49:34 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:49:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:49:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:49:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:49:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:49:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:49:34 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:49:34 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:49:34 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:49:34 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:49:34 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:49:34 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:49:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:49:34 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 04:49:34 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-27 04:49:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:49:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:49:35 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:49:35 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:49:35 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:49:35 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:49:35 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:49:35 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:49:36 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:49:36 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:49:36 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:49:36 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:49:36 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:49:36 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 04:49:37 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 04:49:37 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:49:37 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:49:37 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:49:37 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:49:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:49:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:49:37 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 04:49:37 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:49:37 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:49:37 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:49:37 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:49:37 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:49:37 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:49:37 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:49:37 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:49:37 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=664 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:49:37 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:49:37 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:49:37 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:49:37 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=664 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:49:37 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=664 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:49:37 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=664 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:49:37 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=664 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:49:37 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=664 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:49:42 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:49:42 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:49:42 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:49:42 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:49:42 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:49:42 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:49:42 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:49:42 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:49:42 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:49:42 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:49:42 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:49:42 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:49:42 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:49:42 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:49:42 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:49:42 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:49:42 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:49:42 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:49:42 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:49:42 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:49:42 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:49:42 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:49:42 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:49:42 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:49:42 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:49:42 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:49:42 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:49:42 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:49:42 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:49:42 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:49:42 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:49:42 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:49:42 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:49:42 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:49:42 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:49:42 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:49:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:49:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:49:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:49:42 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:49:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:49:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:49:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:49:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:49:42 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:49:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:49:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:49:42 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:49:42 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:49:42 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:49:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:49:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:49:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:49:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:49:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:49:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:49:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:49:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:49:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:49:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:49:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:49:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:49:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:49:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:49:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:49:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:49:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:49:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:49:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:49:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:49:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:49:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:49:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:49:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:49:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:49:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:49:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:49:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:49:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:49:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:49:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:49:42 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:49:43 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:49:43 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:49:43 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:49:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:49:43 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:49:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:49:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:49:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:49:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:49:43 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:49:43 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:49:43 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:49:43 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:49:43 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:49:43 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:49:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:49:43 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 04:49:43 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-27 04:49:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:49:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:49:43 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:49:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:49:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:49:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:49:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:49:43 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:49:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:49:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:49:44 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 04:49:44 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:49:44 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:49:44 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:49:44 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:49:44 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:49:44 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:49:44 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:49:44 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:49:44 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:49:44 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:49:44 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:49:44 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=352 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:49:44 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=352 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:49:44 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=352 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:49:44 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=352 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:49:44 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=352 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:49:44 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=352 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:49:44 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=353 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:49:44 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=353 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:49:44 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=353 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:49:44 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=353 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:49:44 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=353 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:49:44 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=353 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:49:44 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=353 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:49:44 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=353 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:49:49 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:49:49 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:49:49 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:49:49 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:49:49 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:49:49 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:49:49 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:49:49 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:49:49 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:49:49 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:49:49 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:49:49 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:49:49 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:49:49 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:49:49 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:49:49 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:49:49 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:49:49 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:49:49 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:49:49 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:49:49 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:49:49 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:49:49 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:49:49 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:49:49 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:49:49 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:49:49 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:49:49 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:49:49 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:49:49 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:49:49 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:49:49 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:49:49 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:49:49 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:49:49 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:49:49 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:49:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:49:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:49:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:49:49 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:49:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:49:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:49:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:49:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:49:49 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:49:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:49:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:49:49 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:49:49 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:49:49 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:49:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:49:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:49:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:49:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:49:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:49:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:49:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:49:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:49:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:49:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:49:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:49:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:49:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:49:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:49:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:49:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:49:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:49:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:49:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:49:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:49:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:49:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:49:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:49:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:49:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:49:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:49:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:49:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:49:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:49:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:49:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:49:49 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:49:49 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:49:49 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:49:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:49:49 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:49:49 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:49:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:49:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:49:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:49:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:49:49 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:49:49 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:49:49 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:49:49 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:49:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:49:49 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:49:49 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:49:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:49:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:49:50 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:49:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:49:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:49:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:49:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:49:50 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:49:51 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:49:51 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:49:51 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:49:51 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:49:51 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:49:51 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 04:49:52 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 04:49:52 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:49:52 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:49:52 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:49:52 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:49:52 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 04:49:53 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 04:49:53 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:49:53 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:49:53 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:49:53 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:49:53 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 04:49:54 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 04:49:54 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:49:54 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:49:54 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:49:54 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:49:54 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 04:49:54 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 04:49:55 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 04:49:55 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 04:49:56 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 04:49:56 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 04:49:57 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 04:49:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:49:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:49:57 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 04:49:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:49:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:49:57 [WARNING] transceiver.py:250 (MS@172.18.127.22:6700) RX TRXD message (fn=1839 tn=3 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:49:57 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:49:57 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:49:57 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:49:57 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:49:57 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:49:57 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:49:57 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:49:57 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:49:57 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:49:57 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:49:57 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:49:57 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1841 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:49:57 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1841 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:49:57 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1841 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:49:57 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1841 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:49:57 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1841 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:49:57 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1841 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:49:57 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1841 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:49:57 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1842 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:49:57 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1842 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:49:57 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1842 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:49:57 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1842 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:49:57 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1842 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:49:57 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1842 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:49:57 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1842 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:49:57 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1842 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:49:57 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1843 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:49:57 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1843 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:49:57 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1843 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:49:57 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1843 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:49:57 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1843 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:49:57 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1843 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:49:57 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1843 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:49:57 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1843 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:50:02 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:50:02 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:50:02 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:50:02 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:50:02 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:50:02 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:50:02 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:50:02 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:50:02 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:50:02 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:50:02 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:50:02 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:50:02 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:50:02 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:50:02 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:50:02 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:50:02 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:50:02 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:50:02 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:50:02 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:50:02 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:50:02 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:50:02 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:50:02 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:50:02 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:50:02 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:50:02 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:50:02 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:50:02 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:50:02 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:50:02 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:50:02 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:50:02 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:50:02 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:50:02 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:50:02 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:50:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:50:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:50:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:50:02 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:50:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:50:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:50:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:50:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:50:02 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:50:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:50:02 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:50:02 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:50:02 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:50:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:50:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:50:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:50:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:50:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:50:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:50:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:50:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:50:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:50:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:50:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:50:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:50:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:50:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:50:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:50:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:50:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:50:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:50:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:50:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:50:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:50:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:50:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:50:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:50:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:50:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:50:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:50:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:50:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:50:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:50:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:50:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:50:02 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:50:03 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:50:03 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:50:03 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:50:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:50:03 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:50:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:50:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:50:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:50:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:50:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:50:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:50:03 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:50:03 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:50:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:50:03 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 04:50:03 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-27 04:50:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:50:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:50:03 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:50:03 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:50:03 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:50:03 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:50:03 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:50:04 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:50:04 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:50:04 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:50:04 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:50:04 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:50:04 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:50:05 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 04:50:05 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 04:50:05 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:50:05 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:50:05 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:50:05 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:50:06 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 04:50:06 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 04:50:06 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:50:06 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:50:06 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:50:06 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:50:07 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 04:50:07 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 04:50:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:50:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:50:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:50:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:50:08 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 04:50:08 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 04:50:09 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 04:50:09 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 04:50:09 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 04:50:10 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 04:50:10 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 04:50:11 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 04:50:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:50:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:50:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:50:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:50:11 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 04:50:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:50:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:50:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:50:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:50:11 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:50:11 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:50:11 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:50:11 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:50:11 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:50:11 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:50:11 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1848 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:50:11 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:50:11 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1848 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:50:11 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1848 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:50:11 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1848 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:50:11 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1848 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:50:11 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1848 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:50:11 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1848 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:50:11 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1849 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:50:11 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1849 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:50:11 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1849 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:50:11 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1849 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:50:11 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1849 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:50:11 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1849 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:50:11 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1849 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:50:11 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1849 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:50:16 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:50:16 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:50:16 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:50:16 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:50:16 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:50:16 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:50:16 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:50:16 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:50:16 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:50:16 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:50:16 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:50:16 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:50:16 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:50:16 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:50:16 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:50:16 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:50:16 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:50:16 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:50:16 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:50:16 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:50:16 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:50:16 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:50:16 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:50:16 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:50:16 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:50:16 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:50:16 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:50:16 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:50:16 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:50:16 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:50:16 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:50:16 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:50:16 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:50:16 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:50:16 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:50:16 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:50:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:50:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:50:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:50:16 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:50:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:50:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:50:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:50:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:50:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:50:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:50:16 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:50:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:50:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:50:16 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:50:16 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:50:16 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:50:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:50:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:50:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:50:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:50:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:50:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:50:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:50:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:50:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:50:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:50:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:50:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:50:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:50:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:50:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:50:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:50:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:50:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:50:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:50:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:50:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:50:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:50:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:50:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:50:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:50:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:50:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:50:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:50:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:50:16 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:50:16 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:50:17 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:50:17 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:50:17 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:50:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:50:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:50:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:50:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:50:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:50:17 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:50:17 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:50:17 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:50:17 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:50:17 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:50:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:50:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:50:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:50:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:50:17 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:50:18 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:50:18 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:50:18 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:50:18 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:50:18 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:50:18 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 04:50:19 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 04:50:19 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:50:19 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:50:19 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:50:19 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:50:19 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 04:50:20 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 04:50:20 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:50:20 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:50:20 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:50:20 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:50:20 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 04:50:21 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 04:50:21 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:50:21 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:50:21 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:50:21 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:50:21 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 04:50:22 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 04:50:22 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 04:50:23 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 04:50:23 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 04:50:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:50:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:50:23 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:50:23 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:50:23 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:50:23 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:50:23 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:50:23 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:50:23 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:50:23 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:50:23 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:50:23 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:50:23 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:50:28 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:50:28 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:50:28 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:50:28 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:50:28 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:50:28 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:50:28 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:50:28 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:50:28 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:50:28 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:50:28 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:50:28 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:50:28 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:50:28 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:50:28 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:50:28 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:50:28 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:50:28 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:50:28 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:50:28 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:50:28 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:50:28 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:50:28 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:50:28 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:50:28 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:50:28 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:50:28 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:50:28 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:50:28 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:50:28 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:50:28 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:50:28 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:50:28 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:50:28 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:50:28 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:50:28 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:50:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:50:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:50:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:50:28 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:50:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:50:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:50:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:50:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:50:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:50:28 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:50:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:50:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:50:28 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:50:28 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:50:28 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:50:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:50:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:50:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:50:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:50:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:50:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:50:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:50:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:50:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:50:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:50:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:50:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:50:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:50:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:50:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:50:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:50:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:50:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:50:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:50:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:50:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:50:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:50:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:50:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:50:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:50:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:50:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:50:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:50:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:50:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:50:28 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:50:29 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:50:29 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:50:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:50:29 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:50:29 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:50:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:50:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:50:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:50:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:50:29 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:50:29 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:50:29 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:50:29 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:50:29 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:50:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:50:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:50:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:50:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:50:30 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:50:30 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:50:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:50:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:50:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:50:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:50:31 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 04:50:31 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 04:50:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:50:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:50:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:50:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:50:32 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 04:50:32 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 04:50:32 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:50:32 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:50:32 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:50:32 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:50:33 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 04:50:33 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 04:50:33 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:50:33 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:50:33 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:50:33 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:50:33 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:50:33 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:50:33 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:50:33 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:50:33 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:50:33 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:50:33 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:50:33 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:50:33 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:50:33 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:50:33 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1079 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:50:33 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1079 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:50:33 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1079 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:50:33 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1079 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:50:33 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1079 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:50:33 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1080 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:50:33 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1080 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:50:33 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1080 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:50:33 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1080 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:50:33 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1080 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:50:33 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1080 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:50:33 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1080 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:50:33 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1080 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:50:34 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 04:50:34 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 04:50:34 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 04:50:35 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 04:50:35 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 04:50:36 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 04:50:36 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 04:50:37 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 04:50:37 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 04:50:38 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 04:50:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:50:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:50:38 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:50:38 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:50:38 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:50:38 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:50:38 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:50:38 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:50:38 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:50:38 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:50:38 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:50:38 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:50:38 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:50:38 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:50:38 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:50:38 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:50:38 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:50:38 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:50:38 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:50:38 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:50:38 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:50:38 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:50:38 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:50:38 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:50:38 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:50:38 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:50:38 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:50:38 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:50:38 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:50:38 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:50:38 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:50:38 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:50:38 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:50:38 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:50:38 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:50:38 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:50:38 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:50:38 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:50:38 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:50:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:50:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:50:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:50:38 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:50:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:50:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:50:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:50:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:50:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:50:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:50:38 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:50:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:50:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:50:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:50:38 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:50:38 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:50:38 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:50:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:50:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:50:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:50:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:50:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:50:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:50:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:50:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:50:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:50:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:50:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:50:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:50:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:50:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:50:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:50:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:50:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:50:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:50:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:50:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:50:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:50:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:50:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:50:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:50:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:50:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:50:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:50:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:50:38 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:50:38 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:50:38 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:50:38 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:50:38 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:50:38 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:50:38 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:50:43 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:50:43 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:50:43 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:50:43 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:50:43 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:50:43 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:50:43 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:50:43 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:50:43 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:50:43 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:50:43 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:50:43 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:50:43 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:50:43 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:50:43 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:50:43 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:50:43 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:50:43 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:50:43 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:50:43 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:50:43 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:50:43 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:50:43 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:50:43 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:50:43 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:50:43 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:50:43 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:50:43 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:50:43 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:50:43 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:50:43 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:50:43 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:50:43 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:50:43 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:50:43 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:50:43 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:50:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:50:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:50:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:50:43 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:50:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:50:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:50:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:50:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:50:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:50:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:50:43 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:50:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:50:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:50:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:50:43 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:50:43 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:50:43 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:50:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:50:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:50:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:50:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:50:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:50:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:50:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:50:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:50:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:50:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:50:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:50:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:50:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:50:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:50:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:50:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:50:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:50:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:50:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:50:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:50:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:50:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:50:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:50:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:50:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:50:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:50:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:50:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:50:43 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:50:44 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:50:44 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:50:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:50:44 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:50:44 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:50:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:50:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:50:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:50:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:50:44 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:50:44 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:50:44 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:50:44 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:50:44 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:50:44 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:50:44 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:50:44 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:50:44 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:50:45 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:50:45 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:50:45 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:50:45 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:50:45 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:50:45 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:50:46 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 04:50:46 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 04:50:46 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:50:46 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:50:46 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:50:46 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:50:47 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 04:50:47 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 04:50:47 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:50:47 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:50:47 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:50:47 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:50:48 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 04:50:48 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 04:50:48 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:50:48 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:50:48 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:50:48 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:50:49 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 04:50:49 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 04:50:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:50:50 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 04:50:50 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 04:50:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:50:51 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 04:50:51 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 04:50:51 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:50:52 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 04:50:52 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 04:50:52 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:50:52 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 04:50:53 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 04:50:53 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 04:50:53 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:50:53 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:50:54 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 04:50:54 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-27 04:50:55 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-27 04:50:55 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-27 04:50:56 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-27 04:50:56 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-27 04:50:56 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:50:57 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-27 04:50:57 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-27 04:50:57 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:50:58 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-27 04:50:58 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-27 04:50:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:50:59 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-27 04:50:59 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-27 04:50:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:51:00 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-27 04:51:00 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-27 04:51:00 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:51:01 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-27 04:51:01 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-27 04:51:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:51:02 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-27 04:51:02 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2025-04-27 04:51:03 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2025-04-27 04:51:03 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2025-04-27 04:51:03 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2025-04-27 04:51:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:51:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:51:04 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:51:04 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:51:04 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:51:04 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:51:04 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:51:04 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:51:04 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:51:04 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:51:04 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:51:04 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:51:04 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:51:09 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:51:09 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:51:09 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:51:09 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:51:09 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:51:09 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:51:09 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:51:09 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:51:09 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:51:09 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:51:09 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:51:09 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:51:09 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:51:09 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:51:09 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:51:09 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:51:09 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:51:09 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:51:09 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:51:09 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:51:09 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:51:09 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:51:09 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:51:09 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:51:09 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:51:09 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:51:09 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:51:09 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:51:09 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:51:09 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:51:09 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:51:09 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:51:09 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:51:09 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:51:09 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:51:09 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:51:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:51:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:51:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:51:09 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:51:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:51:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:51:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:51:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:51:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:51:09 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:51:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:51:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:51:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:51:09 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:51:09 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:51:09 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:51:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:51:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:51:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:51:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:51:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:51:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:51:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:51:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:51:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:51:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:51:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:51:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:51:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:51:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:51:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:51:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:51:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:51:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:51:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:51:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:51:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:51:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:51:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:51:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:51:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:51:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:51:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:51:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:51:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:51:09 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:51:09 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:51:09 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:51:09 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:51:09 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:51:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:51:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:51:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:51:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:51:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:51:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:51:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:51:09 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:51:09 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:51:09 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:51:09 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:51:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD NOHANDOVER
2025-04-27 04:51:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:51:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:51:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:51:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:51:09 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=132 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 04:51:09 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=135 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 04:51:09 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=138 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 04:51:09 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=141 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 04:51:09 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=144 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 04:51:09 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=147 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 04:51:09 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=150 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 04:51:09 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=153 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 04:51:09 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=156 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 04:51:09 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=159 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 04:51:09 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=162 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 04:51:09 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=165 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 04:51:09 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=171 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 04:51:09 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=174 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 04:51:09 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=177 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 04:51:09 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=180 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 04:51:09 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=183 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 04:51:09 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=186 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 04:51:09 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=189 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 04:51:09 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=192 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 04:51:10 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=195 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 04:51:10 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=198 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 04:51:10 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=201 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 04:51:10 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=204 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 04:51:10 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:51:10 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=210 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 04:51:10 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=213 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 04:51:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:51:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:51:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:51:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:51:10 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:51:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD NOHANDOVER
2025-04-27 04:51:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:51:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:51:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:51:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:51:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:51:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:51:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:51:11 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:51:11 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:51:11 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:51:11 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:51:11 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:51:11 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:51:11 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:51:11 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=408 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:51:11 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=408 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:51:11 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=408 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:51:11 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=408 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:51:11 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=408 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:51:11 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=408 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:51:11 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=408 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:51:11 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=408 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:51:16 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:51:16 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:51:16 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:51:16 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:51:16 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:51:16 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:51:16 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:51:16 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:51:16 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:51:16 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:51:16 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:51:16 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:51:16 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:51:16 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:51:16 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:51:16 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:51:16 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:51:16 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:51:16 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:51:16 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:51:16 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:51:16 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:51:16 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:51:16 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:51:16 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:51:16 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:51:16 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:51:16 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:51:16 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:51:16 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:51:16 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:51:16 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:51:16 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:51:16 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:51:16 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:51:16 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:51:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:51:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:51:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:51:16 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:51:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:51:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:51:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:51:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:51:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:51:16 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:51:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:51:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:51:16 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:51:16 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:51:16 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:51:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:51:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:51:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:51:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:51:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:51:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:51:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:51:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:51:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:51:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:51:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:51:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:51:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:51:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:51:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:51:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:51:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:51:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:51:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:51:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:51:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:51:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:51:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:51:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:51:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:51:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:51:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:51:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:51:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:51:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:51:16 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:51:16 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:51:16 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:51:16 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:51:16 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:51:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:51:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:51:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:51:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:51:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:51:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:51:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:51:16 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:51:16 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:51:16 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:51:16 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:51:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD NOHANDOVER
2025-04-27 04:51:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:51:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:51:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:51:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:51:16 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=132 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 04:51:16 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=135 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 04:51:16 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=138 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 04:51:16 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=141 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 04:51:16 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=144 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 04:51:16 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=147 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 04:51:16 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=150 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 04:51:16 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=153 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 04:51:16 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=156 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 04:51:16 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=159 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 04:51:16 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=162 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 04:51:16 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=165 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 04:51:16 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=171 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 04:51:16 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=174 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 04:51:16 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=177 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 04:51:16 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=180 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 04:51:16 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=183 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 04:51:16 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=186 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 04:51:16 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=189 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 04:51:16 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=192 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 04:51:16 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=195 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 04:51:16 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=198 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 04:51:16 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=201 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 04:51:16 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=204 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 04:51:16 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:51:17 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=210 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 04:51:17 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=213 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-27 04:51:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:51:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:51:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:51:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:51:17 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:51:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD NOHANDOVER
2025-04-27 04:51:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:51:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:51:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:51:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:51:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:51:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:51:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:51:17 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:51:17 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:51:17 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:51:17 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:51:17 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:51:17 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=407 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:51:17 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:51:17 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:51:17 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=407 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:51:17 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=408 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:51:17 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=408 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:51:17 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=408 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:51:17 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=408 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:51:17 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=408 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:51:17 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=408 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:51:17 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=408 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:51:17 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=408 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:51:22 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:51:22 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:51:22 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:51:22 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:51:22 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:51:22 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:51:22 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:51:22 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:51:22 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:51:22 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:51:22 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:51:22 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:51:22 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:51:22 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:51:22 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:51:22 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:51:22 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:51:22 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:51:22 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:51:22 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:51:22 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:51:22 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:51:22 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:51:22 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:51:22 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:51:22 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:51:22 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:51:22 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:51:22 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:51:22 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:51:22 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:51:22 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:51:22 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:51:22 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:51:22 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:51:22 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:51:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:51:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:51:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:51:22 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:51:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:51:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:51:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:51:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:51:22 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:51:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:51:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:51:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:51:22 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:51:22 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:51:22 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:51:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:51:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:51:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:51:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:51:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:51:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:51:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:51:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:51:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:51:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:51:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:51:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:51:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:51:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:51:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:51:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:51:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:51:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:51:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:51:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:51:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:51:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:51:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:51:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:51:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:51:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:51:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:51:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:51:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:51:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:51:22 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:51:23 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:51:23 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:51:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:51:23 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:51:23 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:51:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:51:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:51:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:51:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:51:23 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:51:23 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:51:23 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:51:23 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:51:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:51:23 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:51:23 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:51:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:51:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:51:23 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:51:23 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:51:23 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:51:23 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:51:23 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:51:24 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:51:24 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:51:24 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:51:24 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:51:24 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:51:24 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:51:25 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 04:51:25 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 04:51:25 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:51:25 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:51:25 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:51:25 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:51:26 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 04:51:26 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 04:51:26 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:51:26 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:51:26 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:51:26 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:51:27 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 04:51:27 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 04:51:27 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:51:27 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:51:27 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:51:27 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:51:28 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 04:51:28 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 04:51:29 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 04:51:29 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 04:51:30 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 04:51:30 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 04:51:31 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 04:51:31 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 04:51:32 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 04:51:32 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 04:51:32 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 04:51:33 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 04:51:33 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-27 04:51:34 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-27 04:51:34 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-27 04:51:35 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-27 04:51:35 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-27 04:51:36 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-27 04:51:36 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-27 04:51:37 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-27 04:51:37 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-27 04:51:38 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-27 04:51:38 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-27 04:51:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:51:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:51:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:51:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:51:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:51:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:51:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:51:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:51:39 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:51:39 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:51:39 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:51:39 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:51:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:51:39 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 04:51:39 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2025-04-27 04:51:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:51:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:51:39 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-27 04:51:39 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-27 04:51:40 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-27 04:51:40 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-27 04:51:41 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-27 04:51:41 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2025-04-27 04:51:42 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2025-04-27 04:51:42 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2025-04-27 04:51:43 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2025-04-27 04:51:43 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2025-04-27 04:51:43 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2025-04-27 04:51:44 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2025-04-27 04:51:44 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2025-04-27 04:51:45 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2025-04-27 04:51:45 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2025-04-27 04:51:46 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2025-04-27 04:51:46 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2025-04-27 04:51:47 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2025-04-27 04:51:47 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2025-04-27 04:51:48 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2025-04-27 04:51:48 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2025-04-27 04:51:49 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2025-04-27 04:51:49 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2025-04-27 04:51:50 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2025-04-27 04:51:50 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2025-04-27 04:51:51 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2025-04-27 04:51:51 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2025-04-27 04:51:52 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2025-04-27 04:51:52 [DEBUG] clck_gen.py:102 IND CLOCK 6324
2025-04-27 04:51:52 [DEBUG] clck_gen.py:102 IND CLOCK 6426
2025-04-27 04:51:53 [DEBUG] clck_gen.py:102 IND CLOCK 6528
2025-04-27 04:51:53 [DEBUG] clck_gen.py:102 IND CLOCK 6630
2025-04-27 04:51:54 [DEBUG] clck_gen.py:102 IND CLOCK 6732
2025-04-27 04:51:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:51:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:51:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:51:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:51:54 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 04:51:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:51:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:51:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:51:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:51:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:51:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:51:54 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:51:54 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:51:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:51:54 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 04:51:54 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=3, maio=3, ma_len=4
2025-04-27 04:51:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:51:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:51:54 [DEBUG] clck_gen.py:102 IND CLOCK 6834
2025-04-27 04:51:55 [DEBUG] clck_gen.py:102 IND CLOCK 6936
2025-04-27 04:51:55 [DEBUG] clck_gen.py:102 IND CLOCK 7038
2025-04-27 04:51:56 [DEBUG] clck_gen.py:102 IND CLOCK 7140
2025-04-27 04:51:56 [DEBUG] clck_gen.py:102 IND CLOCK 7242
2025-04-27 04:51:57 [DEBUG] clck_gen.py:102 IND CLOCK 7344
2025-04-27 04:51:57 [DEBUG] clck_gen.py:102 IND CLOCK 7446
2025-04-27 04:51:58 [DEBUG] clck_gen.py:102 IND CLOCK 7548
2025-04-27 04:51:58 [DEBUG] clck_gen.py:102 IND CLOCK 7650
2025-04-27 04:51:59 [DEBUG] clck_gen.py:102 IND CLOCK 7752
2025-04-27 04:51:59 [DEBUG] clck_gen.py:102 IND CLOCK 7854
2025-04-27 04:52:00 [DEBUG] clck_gen.py:102 IND CLOCK 7956
2025-04-27 04:52:00 [DEBUG] clck_gen.py:102 IND CLOCK 8058
2025-04-27 04:52:01 [DEBUG] clck_gen.py:102 IND CLOCK 8160
2025-04-27 04:52:01 [DEBUG] clck_gen.py:102 IND CLOCK 8262
2025-04-27 04:52:02 [DEBUG] clck_gen.py:102 IND CLOCK 8364
2025-04-27 04:52:02 [DEBUG] clck_gen.py:102 IND CLOCK 8466
2025-04-27 04:52:02 [DEBUG] clck_gen.py:102 IND CLOCK 8568
2025-04-27 04:52:03 [DEBUG] clck_gen.py:102 IND CLOCK 8670
2025-04-27 04:52:03 [DEBUG] clck_gen.py:102 IND CLOCK 8772
2025-04-27 04:52:04 [DEBUG] clck_gen.py:102 IND CLOCK 8874
2025-04-27 04:52:04 [DEBUG] clck_gen.py:102 IND CLOCK 8976
2025-04-27 04:52:05 [DEBUG] clck_gen.py:102 IND CLOCK 9078
2025-04-27 04:52:05 [DEBUG] clck_gen.py:102 IND CLOCK 9180
2025-04-27 04:52:06 [DEBUG] clck_gen.py:102 IND CLOCK 9282
2025-04-27 04:52:06 [DEBUG] clck_gen.py:102 IND CLOCK 9384
2025-04-27 04:52:07 [DEBUG] clck_gen.py:102 IND CLOCK 9486
2025-04-27 04:52:07 [DEBUG] clck_gen.py:102 IND CLOCK 9588
2025-04-27 04:52:08 [DEBUG] clck_gen.py:102 IND CLOCK 9690
2025-04-27 04:52:08 [DEBUG] clck_gen.py:102 IND CLOCK 9792
2025-04-27 04:52:09 [DEBUG] clck_gen.py:102 IND CLOCK 9894
2025-04-27 04:52:09 [DEBUG] clck_gen.py:102 IND CLOCK 9996
2025-04-27 04:52:10 [DEBUG] clck_gen.py:102 IND CLOCK 10098
2025-04-27 04:52:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:52:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:52:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:52:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:52:10 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 04:52:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:52:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:52:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:52:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:52:10 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:52:10 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:52:10 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:52:10 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:52:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:52:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:52:10 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:52:10 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:52:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:52:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:52:10 [DEBUG] clck_gen.py:102 IND CLOCK 10200
2025-04-27 04:52:11 [DEBUG] clck_gen.py:102 IND CLOCK 10302
2025-04-27 04:52:11 [DEBUG] clck_gen.py:102 IND CLOCK 10404
2025-04-27 04:52:12 [DEBUG] clck_gen.py:102 IND CLOCK 10506
2025-04-27 04:52:12 [DEBUG] clck_gen.py:102 IND CLOCK 10608
2025-04-27 04:52:13 [DEBUG] clck_gen.py:102 IND CLOCK 10710
2025-04-27 04:52:13 [DEBUG] clck_gen.py:102 IND CLOCK 10812
2025-04-27 04:52:13 [DEBUG] clck_gen.py:102 IND CLOCK 10914
2025-04-27 04:52:14 [DEBUG] clck_gen.py:102 IND CLOCK 11016
2025-04-27 04:52:14 [DEBUG] clck_gen.py:102 IND CLOCK 11118
2025-04-27 04:52:15 [DEBUG] clck_gen.py:102 IND CLOCK 11220
2025-04-27 04:52:15 [DEBUG] clck_gen.py:102 IND CLOCK 11322
2025-04-27 04:52:16 [DEBUG] clck_gen.py:102 IND CLOCK 11424
2025-04-27 04:52:16 [DEBUG] clck_gen.py:102 IND CLOCK 11526
2025-04-27 04:52:17 [DEBUG] clck_gen.py:102 IND CLOCK 11628
2025-04-27 04:52:17 [DEBUG] clck_gen.py:102 IND CLOCK 11730
2025-04-27 04:52:18 [DEBUG] clck_gen.py:102 IND CLOCK 11832
2025-04-27 04:52:18 [DEBUG] clck_gen.py:102 IND CLOCK 11934
2025-04-27 04:52:19 [DEBUG] clck_gen.py:102 IND CLOCK 12036
2025-04-27 04:52:19 [DEBUG] clck_gen.py:102 IND CLOCK 12138
2025-04-27 04:52:20 [DEBUG] clck_gen.py:102 IND CLOCK 12240
2025-04-27 04:52:20 [DEBUG] clck_gen.py:102 IND CLOCK 12342
2025-04-27 04:52:21 [DEBUG] clck_gen.py:102 IND CLOCK 12444
2025-04-27 04:52:21 [DEBUG] clck_gen.py:102 IND CLOCK 12546
2025-04-27 04:52:22 [DEBUG] clck_gen.py:102 IND CLOCK 12648
2025-04-27 04:52:22 [DEBUG] clck_gen.py:102 IND CLOCK 12750
2025-04-27 04:52:23 [DEBUG] clck_gen.py:102 IND CLOCK 12852
2025-04-27 04:52:23 [DEBUG] clck_gen.py:102 IND CLOCK 12954
2025-04-27 04:52:24 [DEBUG] clck_gen.py:102 IND CLOCK 13056
2025-04-27 04:52:24 [DEBUG] clck_gen.py:102 IND CLOCK 13158
2025-04-27 04:52:24 [DEBUG] clck_gen.py:102 IND CLOCK 13260
2025-04-27 04:52:25 [DEBUG] clck_gen.py:102 IND CLOCK 13362
2025-04-27 04:52:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:52:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:52:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:52:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:52:25 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:52:25 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:52:25 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:52:25 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:52:25 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:52:25 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:52:25 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:52:25 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:52:25 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:52:25 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:52:25 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:52:25 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=13456 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:52:25 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=13456 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:52:25 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=13456 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:52:25 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=13456 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:52:25 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=13456 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:52:25 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=13456 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:52:25 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=13456 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:52:30 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:52:30 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:52:30 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:52:30 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:52:30 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:52:30 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:52:30 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:52:30 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:52:30 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:52:30 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:52:30 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:52:30 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:52:30 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:52:30 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:52:30 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:52:30 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:52:30 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:52:30 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:52:30 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:52:30 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:52:30 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:52:30 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:52:30 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:52:30 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:52:30 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:52:30 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:52:30 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:52:30 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:52:30 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:52:30 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:52:30 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:52:30 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:52:30 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:52:30 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:52:30 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:52:30 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:52:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:52:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:52:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:52:30 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:52:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:52:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:52:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:52:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:52:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:52:30 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:52:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:52:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:52:30 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:52:30 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:52:30 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:52:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:52:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:52:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:52:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:52:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:52:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:52:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:52:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:52:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:52:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:52:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:52:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:52:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:52:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:52:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:52:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:52:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:52:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:52:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:52:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:52:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:52:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:52:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:52:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:52:30 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:52:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:52:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:52:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:52:30 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:52:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:52:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:52:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:52:30 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:52:30 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:52:30 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:52:30 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:52:30 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:52:35 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:52:35 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:52:35 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:52:35 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:52:35 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:52:35 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:52:35 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:52:35 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:52:35 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:52:35 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:52:35 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:52:35 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:52:35 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:52:35 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:52:35 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:52:35 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:52:35 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:52:35 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:52:35 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:52:35 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:52:35 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:52:35 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:52:35 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:52:35 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:52:35 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:52:35 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:52:35 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:52:35 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:52:35 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:52:35 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:52:35 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:52:35 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:52:35 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:52:35 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:52:35 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:52:35 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:52:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:52:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:52:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:52:35 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:52:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:52:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:52:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:52:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:52:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:52:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:52:35 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:52:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:52:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:52:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:52:35 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:52:35 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:52:35 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:52:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:52:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:52:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:52:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:52:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:52:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:52:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:52:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:52:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:52:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:52:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:52:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:52:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:52:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:52:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:52:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:52:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:52:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:52:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:52:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:52:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:52:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:52:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:52:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:52:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:52:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:52:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:52:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:52:35 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:52:36 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:52:36 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:52:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:52:36 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:52:36 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:52:36 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:52:36 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:52:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:52:36 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:52:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:52:36 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:52:36 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:52:36 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:52:36 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:52:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:52:36 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:52:36 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:52:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:52:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:52:36 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:52:36 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:52:36 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:52:36 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:52:36 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:52:37 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:52:37 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:52:37 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:52:37 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:52:37 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:52:37 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:52:38 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 04:52:38 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 04:52:38 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:52:38 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:52:38 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:52:38 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:52:39 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 04:52:39 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 04:52:39 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:52:39 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:52:39 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:52:39 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:52:40 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 04:52:40 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 04:52:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:52:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:52:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:52:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:52:41 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 04:52:41 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 04:52:42 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 04:52:42 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 04:52:43 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 04:52:43 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 04:52:44 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 04:52:44 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 04:52:45 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 04:52:45 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 04:52:45 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 04:52:46 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 04:52:46 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-27 04:52:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:52:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:52:46 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:52:46 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:52:46 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:52:46 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:52:46 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:52:46 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:52:46 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:52:46 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:52:46 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:52:46 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:52:46 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:52:46 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:52:46 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:52:46 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2352 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:52:46 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2352 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:52:46 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2352 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:52:46 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2352 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:52:46 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2352 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:52:46 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2352 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:52:46 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2352 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:52:51 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:52:51 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:52:51 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:52:51 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:52:51 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:52:51 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:52:51 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:52:51 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:52:51 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:52:51 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:52:51 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:52:51 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:52:51 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:52:51 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:52:51 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:52:51 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:52:51 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:52:51 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:52:51 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:52:51 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:52:51 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:52:51 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:52:51 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:52:51 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:52:51 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:52:51 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:52:51 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:52:51 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:52:51 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:52:51 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:52:51 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:52:51 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:52:51 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:52:51 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:52:51 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:52:51 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:52:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:52:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:52:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:52:51 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:52:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:52:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:52:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:52:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:52:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:52:51 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:52:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:52:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:52:51 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:52:51 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:52:51 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:52:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:52:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:52:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:52:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:52:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:52:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:52:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:52:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:52:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:52:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:52:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:52:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:52:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:52:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:52:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:52:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:52:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:52:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:52:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:52:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:52:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:52:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:52:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:52:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:52:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:52:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:52:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:52:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:52:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:52:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:52:51 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:52:52 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:52:52 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:52:52 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:52:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:52:52 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:52:52 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:52:52 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:52:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:52:52 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:52:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:52:52 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:52:52 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:52:52 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:52:52 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:52:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:52:52 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:52:52 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:52:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:52:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:52:52 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:52:52 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:52:52 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:52:52 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:52:52 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:52:53 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:52:53 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:52:53 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:52:53 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:52:53 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:52:53 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:52:54 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 04:52:54 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 04:52:54 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:52:54 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:52:54 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:52:54 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:52:55 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 04:52:55 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 04:52:55 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:52:55 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:52:55 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:52:55 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:52:56 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 04:52:56 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 04:52:56 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:52:56 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:52:56 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:52:56 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:52:57 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 04:52:57 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 04:52:58 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 04:52:58 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 04:52:59 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 04:52:59 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 04:53:00 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 04:53:00 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 04:53:00 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 04:53:01 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 04:53:01 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 04:53:02 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 04:53:02 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-27 04:53:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:53:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:53:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:53:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:53:02 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:53:02 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:53:02 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:53:02 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:53:02 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:53:02 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:53:02 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:53:02 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:53:02 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:53:02 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:53:02 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:53:02 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2359 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:53:02 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2359 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:53:02 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2359 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:53:02 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2359 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:53:02 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2359 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:53:02 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2359 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:53:02 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2359 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:53:07 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:53:07 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:53:07 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:53:07 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:53:07 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:53:07 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:53:07 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:53:07 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:53:07 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:53:07 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:53:07 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:53:07 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:53:07 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:53:07 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:53:07 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:53:07 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:53:07 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:53:07 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:53:07 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:53:07 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:53:07 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:53:07 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:53:07 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:53:07 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:53:07 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:53:07 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:53:07 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:53:07 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:53:07 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:53:07 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:53:07 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:53:07 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:53:07 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:53:07 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:53:07 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:53:07 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:53:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:53:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:53:07 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:53:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:53:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:53:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:53:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:53:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:53:07 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:53:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:53:07 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:53:07 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:53:07 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:53:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:53:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:53:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:53:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:53:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:53:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:53:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:53:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:53:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:53:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:53:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:53:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:53:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:53:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:53:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:53:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:53:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:53:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:53:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:53:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:53:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:53:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:53:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:53:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:53:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:53:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:53:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:53:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:53:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:53:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:53:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:53:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:53:07 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:53:08 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:53:08 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:53:08 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:53:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:53:08 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:53:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:53:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:53:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:53:08 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:53:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:53:08 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:53:08 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:53:08 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:53:08 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:53:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:53:08 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:53:08 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:53:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:53:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:53:08 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:53:08 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:53:08 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:53:08 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:53:08 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:53:09 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:53:09 [DEBUG] fake_trx.py:263 (MS@172.18.127.22:6700) Recv SETTA cmd
2025-04-27 04:53:09 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:53:09 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:53:09 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:53:09 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:53:09 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:53:10 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 04:53:10 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 04:53:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:53:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:53:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:53:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:53:11 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 04:53:11 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 04:53:12 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:53:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:53:12 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:53:12 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:53:12 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 04:53:12 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 04:53:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:53:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:53:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:53:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:53:13 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 04:53:13 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 04:53:14 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 04:53:14 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 04:53:15 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 04:53:15 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 04:53:16 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 04:53:16 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 04:53:17 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 04:53:17 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 04:53:17 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 04:53:18 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 04:53:18 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-27 04:53:19 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-27 04:53:19 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-27 04:53:20 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-27 04:53:20 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-27 04:53:21 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-27 04:53:21 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-27 04:53:22 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-27 04:53:22 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-27 04:53:23 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-27 04:53:23 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-27 04:53:24 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-27 04:53:24 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-27 04:53:25 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-27 04:53:25 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-27 04:53:26 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-27 04:53:26 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2025-04-27 04:53:27 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2025-04-27 04:53:27 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2025-04-27 04:53:27 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2025-04-27 04:53:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:53:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:53:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:53:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:53:28 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:53:28 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:53:28 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:53:28 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:53:28 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:53:28 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:53:28 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:53:28 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:53:28 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:53:28 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:53:28 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4329 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:53:28 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:53:28 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4329 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:53:28 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4329 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:53:28 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4329 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:53:28 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4329 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:53:28 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4329 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:53:28 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4330 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:53:28 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4330 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:53:28 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4330 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:53:28 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4330 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:53:28 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4330 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:53:28 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4330 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:53:28 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4330 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:53:28 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4330 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:53:28 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4331 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:53:28 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4331 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:53:28 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4331 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:53:28 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4331 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:53:28 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4331 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:53:28 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4331 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:53:28 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4331 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:53:28 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4331 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:53:33 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:53:33 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:53:33 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:53:33 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:53:33 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:53:33 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:53:33 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:53:33 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:53:33 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:53:33 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:53:33 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:53:33 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:53:33 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:53:33 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:53:33 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:53:33 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:53:33 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:53:33 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:53:33 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:53:33 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:53:33 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:53:33 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:53:33 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:53:33 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:53:33 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:53:33 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:53:33 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:53:33 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:53:33 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:53:33 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:53:33 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:53:33 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:53:33 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:53:33 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:53:33 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:53:33 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:53:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:53:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:53:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:53:33 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:53:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:53:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:53:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:53:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:53:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:53:33 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:53:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:53:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:53:33 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:53:33 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:53:33 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:53:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:53:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:53:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:53:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:53:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:53:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:53:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:53:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:53:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:53:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:53:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:53:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:53:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:53:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:53:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:53:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:53:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:53:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:53:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:53:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:53:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:53:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:53:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:53:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:53:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:53:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:53:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:53:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:53:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:53:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:53:33 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:53:33 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:53:33 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:53:33 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:53:33 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:53:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:53:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:53:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:53:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:53:33 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:53:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:53:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:53:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:53:33 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:53:33 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:53:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:53:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:53:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:53:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:53:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:53:34 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:53:34 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:53:34 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:53:34 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:53:34 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:53:34 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:53:35 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:53:35 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:53:35 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:53:35 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:53:35 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:53:35 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 04:53:36 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 04:53:36 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:53:36 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:53:36 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:53:36 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:53:36 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 04:53:37 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 04:53:37 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:53:37 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:53:37 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:53:37 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:53:37 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 04:53:38 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 04:53:38 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:53:38 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:53:38 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:53:38 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:53:38 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 04:53:38 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 04:53:39 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 04:53:39 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 04:53:40 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 04:53:40 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 04:53:41 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 04:53:41 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 04:53:42 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 04:53:42 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 04:53:43 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 04:53:43 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 04:53:44 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-27 04:53:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:53:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:53:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:53:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:53:44 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:53:44 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:53:44 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:53:44 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:53:44 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:53:44 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:53:44 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:53:44 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:53:44 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:53:44 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:53:44 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:53:49 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:53:49 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:53:49 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:53:49 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:53:49 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:53:49 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:53:49 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:53:49 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:53:49 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:53:49 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:53:49 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:53:49 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:53:49 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:53:49 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:53:49 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:53:49 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:53:49 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:53:49 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:53:49 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:53:49 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:53:49 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:53:49 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:53:49 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:53:49 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:53:49 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:53:49 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:53:49 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:53:49 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:53:49 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:53:49 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:53:49 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:53:49 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:53:49 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:53:49 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:53:49 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:53:49 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:53:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:53:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:53:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:53:49 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:53:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:53:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:53:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:53:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:53:49 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:53:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:53:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:53:49 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:53:49 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:53:49 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:53:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:53:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:53:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:53:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:53:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:53:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:53:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:53:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:53:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:53:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:53:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:53:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:53:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:53:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:53:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:53:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:53:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:53:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:53:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:53:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:53:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:53:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:53:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:53:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:53:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:53:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:53:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:53:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:53:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:53:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:53:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:53:49 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:53:49 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:53:49 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:53:49 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:53:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:53:49 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:53:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:53:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:53:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:53:49 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:53:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:53:49 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:53:49 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:53:49 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:53:49 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:53:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:53:49 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:53:49 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:53:49 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:53:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:53:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:53:50 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:53:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:53:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:53:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:53:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:53:50 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:53:50 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:53:51 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:53:51 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:53:51 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:53:51 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:53:51 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:53:51 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 04:53:52 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 04:53:52 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:53:52 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:53:52 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:53:52 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:53:52 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 04:53:53 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 04:53:53 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:53:53 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:53:53 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:53:53 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:53:53 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 04:53:53 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 04:53:54 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:53:54 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:53:54 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:53:54 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:53:54 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 04:53:54 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 04:53:55 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 04:53:55 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 04:53:56 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 04:53:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:53:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:53:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:53:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:53:56 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:53:56 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:53:56 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:53:56 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:53:56 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:53:56 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:53:56 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:53:56 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:53:56 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:53:56 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1562 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:53:56 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:53:56 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:53:56 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1562 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:53:56 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1563 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:53:56 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1563 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:53:56 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1563 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:53:56 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1563 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:53:56 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1563 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:53:56 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1563 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:53:56 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1563 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:53:56 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1563 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:54:01 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:54:01 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:54:01 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:54:01 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:54:01 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:54:01 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:54:01 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:54:01 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:54:01 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:54:01 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:54:01 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:54:01 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:54:01 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:54:01 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:54:01 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:54:01 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:54:01 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:54:01 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:54:01 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:54:01 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:54:01 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:54:01 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:54:01 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:54:01 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:54:01 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:54:01 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:54:01 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:54:01 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:54:01 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:54:01 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:54:01 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:54:01 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:54:01 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:54:01 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:54:01 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:54:01 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:54:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:54:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:54:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:54:01 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:54:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:54:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:54:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:54:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:54:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:54:01 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:54:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:54:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:54:01 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:54:01 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:54:01 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:54:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:54:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:54:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:54:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:54:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:54:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:54:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:54:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:54:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:54:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:54:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:54:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:54:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:54:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:54:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:54:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:54:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:54:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:54:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:54:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:54:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:54:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:54:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:54:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:54:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:54:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:54:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:54:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:54:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:54:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:54:01 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:54:02 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:54:02 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:54:02 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:54:02 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:54:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:54:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:54:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:54:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:54:02 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:54:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:54:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:54:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:54:02 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:54:02 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:54:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:54:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:54:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:54:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:54:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:54:02 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:54:02 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:54:02 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:54:02 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:54:02 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:54:02 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:54:03 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:54:03 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:54:03 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:54:03 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:54:03 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:54:03 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 04:54:04 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 04:54:04 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:54:04 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:54:04 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:54:04 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:54:04 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 04:54:05 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 04:54:05 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:54:05 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:54:05 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:54:05 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:54:05 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 04:54:06 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 04:54:06 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:54:06 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:54:06 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:54:06 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:54:06 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 04:54:07 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 04:54:07 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 04:54:08 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 04:54:08 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 04:54:09 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 04:54:09 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 04:54:10 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 04:54:10 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 04:54:11 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 04:54:11 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 04:54:12 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 04:54:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:54:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:54:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:54:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:54:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:54:12 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:54:12 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:54:12 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:54:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:54:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:54:12 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:54:12 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:54:12 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:54:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:54:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:54:12 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2265 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:54:12 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2265 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:54:12 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2265 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:54:12 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2265 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:54:12 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2265 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:54:12 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2265 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:54:12 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2265 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:54:17 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:54:17 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:54:17 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:54:17 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:54:17 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:54:17 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:54:17 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:54:17 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:54:17 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:54:17 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:54:17 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:54:17 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:54:17 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:54:17 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:54:17 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:54:17 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:54:17 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:54:17 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:54:17 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:54:17 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:54:17 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:54:17 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:54:17 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:54:17 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:54:17 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:54:17 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:54:17 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:54:17 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:54:17 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:54:17 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:54:17 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:54:17 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:54:17 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:54:17 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:54:17 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:54:17 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:54:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:54:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:54:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:54:17 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:54:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:54:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:54:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:54:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:54:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:54:17 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:54:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:54:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:54:17 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:54:17 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:54:17 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:54:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:54:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:54:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:54:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:54:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:54:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:54:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:54:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:54:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:54:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:54:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:54:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:54:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:54:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:54:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:54:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:54:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:54:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:54:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:54:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:54:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:54:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:54:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:54:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:54:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:54:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:54:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:54:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:54:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:54:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:54:17 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:54:17 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:54:17 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:54:17 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:54:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:54:17 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:54:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:54:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:54:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:54:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:54:17 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:54:17 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:54:17 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:54:17 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:54:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:54:17 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:54:17 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:54:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:54:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:54:18 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:54:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:54:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:54:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:54:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:54:18 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:54:18 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:54:18 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:54:18 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:54:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:54:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:54:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:54:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:54:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:54:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:54:18 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:54:18 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:54:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:54:18 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 04:54:18 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-27 04:54:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:54:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:54:18 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:54:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:54:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:54:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:54:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:54:18 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 04:54:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:54:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:54:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:54:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:54:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:54:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:54:18 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:54:18 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:54:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:54:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:54:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:54:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:54:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:54:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:54:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:54:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:54:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:54:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:54:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:54:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:54:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:54:19 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:54:19 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:54:19 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:54:19 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:54:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:54:19 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 04:54:19 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-27 04:54:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:54:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:54:19 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:54:19 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:54:19 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:54:19 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:54:19 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:54:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:54:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:54:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:54:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:54:19 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 04:54:19 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:54:19 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:54:19 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:54:19 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:54:19 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:54:19 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:54:19 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:54:19 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:54:19 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:54:19 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:54:19 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:54:19 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=497 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:54:19 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=497 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:54:19 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=497 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:54:19 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=497 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:54:19 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=497 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:54:24 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:54:24 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:54:24 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:54:24 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:54:24 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:54:24 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:54:24 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:54:24 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:54:24 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:54:24 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:54:24 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:54:24 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:54:24 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:54:24 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:54:24 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:54:24 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:54:24 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:54:24 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:54:24 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:54:24 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:54:24 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:54:24 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:54:24 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:54:24 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:54:24 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:54:24 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:54:24 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:54:24 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:54:24 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:54:24 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:54:24 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:54:24 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:54:24 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:54:24 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:54:24 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:54:24 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:54:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:54:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:54:24 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:54:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:54:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:54:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:54:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:54:24 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:54:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:54:24 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:54:24 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:54:24 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:54:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:54:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:54:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:54:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:54:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:54:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:54:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:54:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:54:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:54:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:54:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:54:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:54:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:54:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:54:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:54:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:54:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:54:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:54:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:54:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:54:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:54:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:54:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:54:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:54:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:54:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:54:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:54:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:54:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:54:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:54:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:54:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:54:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:54:24 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:54:25 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:54:25 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:54:25 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:54:25 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:54:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:54:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:54:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:54:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:54:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:54:25 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:54:25 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:54:25 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:54:25 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:54:25 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:54:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:54:25 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:54:25 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:54:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:54:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:54:25 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:54:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:54:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:54:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:54:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:54:25 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:54:25 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:54:25 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:54:25 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:54:25 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:54:25 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:54:25 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:54:25 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:54:25 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:54:25 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:54:25 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:54:25 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=210 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:54:25 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=210 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:54:25 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=210 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:54:25 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=210 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:54:25 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=210 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:54:25 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=210 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:54:30 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:54:30 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:54:30 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:54:30 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:54:30 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:54:30 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:54:30 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:54:30 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:54:30 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:54:30 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:54:30 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:54:30 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:54:30 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:54:30 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:54:30 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:54:30 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:54:30 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:54:30 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:54:30 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:54:30 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:54:30 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:54:30 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:54:30 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:54:30 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:54:30 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:54:30 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:54:30 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:54:30 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:54:30 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:54:30 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:54:30 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:54:30 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:54:30 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:54:30 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:54:30 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:54:30 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:54:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:54:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:54:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:54:30 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:54:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:54:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:54:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:54:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:54:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:54:30 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:54:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:54:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:54:30 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:54:30 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:54:30 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:54:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:54:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:54:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:54:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:54:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:54:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:54:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:54:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:54:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:54:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:54:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:54:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:54:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:54:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:54:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:54:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:54:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:54:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:54:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:54:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:54:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:54:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:54:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:54:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:54:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:54:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:54:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:54:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:54:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:54:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:54:30 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:54:31 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:54:31 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:54:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:54:31 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:54:31 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:54:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:54:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:54:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:54:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:54:31 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:54:31 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:54:31 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:54:31 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:54:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:54:31 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:54:31 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:54:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:54:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:54:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:54:31 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:54:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:54:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:54:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:54:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:54:32 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:54:32 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:54:32 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:54:32 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:54:32 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:54:32 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:54:32 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 04:54:33 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 04:54:33 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:54:33 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:54:33 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:54:33 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:54:33 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 04:54:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:54:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:54:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:54:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:54:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:54:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:54:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:54:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:54:34 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:54:34 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:54:34 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:54:34 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:54:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:54:34 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 04:54:34 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-27 04:54:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:54:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:54:34 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 04:54:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:54:34 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:54:34 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:54:34 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:54:34 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:54:34 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 04:54:35 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 04:54:35 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:54:35 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:54:35 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:54:35 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:54:35 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 04:54:36 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 04:54:36 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 04:54:37 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 04:54:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:54:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:54:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:54:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:54:37 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 04:54:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:54:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:54:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:54:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:54:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:54:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:54:37 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:54:37 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:54:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:54:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:54:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:54:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:54:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:54:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:54:37 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 04:54:38 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 04:54:38 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 04:54:39 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 04:54:39 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 04:54:40 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 04:54:40 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 04:54:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:54:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:54:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:54:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:54:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:54:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:54:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:54:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:54:40 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:54:40 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:54:40 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:54:40 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:54:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:54:40 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 04:54:40 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-27 04:54:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:54:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:54:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:54:41 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 04:54:41 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-27 04:54:42 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-27 04:54:42 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-27 04:54:42 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-27 04:54:43 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-27 04:54:43 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-27 04:54:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:54:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:54:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:54:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:54:43 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 04:54:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:54:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:54:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:54:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:54:43 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:54:43 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:54:43 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:54:43 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:54:43 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:54:43 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:54:43 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:54:43 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2875 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:54:43 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2875 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:54:43 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2875 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:54:43 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2875 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:54:43 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2875 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:54:43 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2875 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:54:48 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:54:48 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:54:48 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:54:48 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:54:48 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:54:48 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:54:49 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:54:49 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:54:49 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:54:49 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:54:49 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:54:49 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:54:49 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:54:49 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:54:49 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:54:49 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:54:49 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:54:49 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:54:49 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:54:49 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:54:49 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:54:49 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:54:49 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:54:49 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:54:49 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:54:49 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:54:49 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:54:49 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:54:49 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:54:49 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:54:49 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:54:49 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:54:49 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:54:49 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:54:49 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:54:49 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:54:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:54:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:54:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:54:49 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:54:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:54:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:54:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:54:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:54:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:54:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:54:49 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:54:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:54:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:54:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:54:49 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:54:49 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:54:49 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:54:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:54:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:54:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:54:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:54:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:54:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:54:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:54:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:54:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:54:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:54:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:54:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:54:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:54:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:54:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:54:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:54:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:54:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:54:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:54:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:54:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:54:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:54:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:54:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:54:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:54:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:54:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:54:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:54:49 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:54:49 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:54:49 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:54:49 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:54:49 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:54:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:54:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:54:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:54:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:54:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:54:49 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:54:49 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:54:49 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:54:49 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:54:49 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:54:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:54:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:54:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:54:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:54:50 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:54:50 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:54:51 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:54:51 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:54:51 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:54:51 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:54:51 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 04:54:51 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 04:54:52 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:54:52 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:54:52 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:54:52 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:54:52 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 04:54:52 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 04:54:53 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:54:53 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:54:53 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:54:53 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:54:53 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 04:54:53 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 04:54:54 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:54:54 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:54:54 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:54:54 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:54:54 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 04:54:54 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 04:54:55 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 04:54:55 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 04:54:56 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 04:54:56 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 04:54:57 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 04:54:57 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 04:54:58 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 04:54:58 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 04:54:59 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 04:54:59 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 04:54:59 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-27 04:55:00 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-27 04:55:00 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-27 04:55:01 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-27 04:55:01 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-27 04:55:02 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-27 04:55:02 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-27 04:55:03 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-27 04:55:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:55:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:55:03 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:55:03 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:55:03 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:55:03 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:55:03 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:55:03 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:55:03 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:55:03 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:55:03 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:55:03 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:55:03 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3124 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:55:03 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:55:03 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3124 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:55:03 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3124 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:55:03 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3125 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:55:03 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3125 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:55:03 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3125 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:55:03 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3125 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:55:03 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3125 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:55:03 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3125 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:55:03 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3125 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:55:03 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3125 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:55:08 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:55:08 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:55:08 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:55:08 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:55:08 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:55:08 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:55:08 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:55:08 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:55:08 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:55:08 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:55:08 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:55:08 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:55:08 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:55:08 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:55:08 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:55:08 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:55:08 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:55:08 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:55:08 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:55:08 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:55:08 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:55:08 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:55:08 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:55:08 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:55:08 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:55:08 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:55:08 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:55:08 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:55:08 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:55:08 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:55:08 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:55:08 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:55:08 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:55:08 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:55:08 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:55:08 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:55:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:55:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:55:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:55:08 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:55:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:55:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:55:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:55:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:55:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:55:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:55:08 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:55:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:55:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:55:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:55:08 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:55:08 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:55:08 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:55:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:55:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:55:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:55:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:55:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:55:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:55:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:55:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:55:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:55:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:55:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:55:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:55:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:55:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:55:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:55:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:55:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:55:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:55:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:55:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:55:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:55:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:55:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:55:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:55:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:55:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:55:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:55:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:55:08 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:55:09 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:55:09 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:55:09 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:55:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:55:09 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:55:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:55:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:55:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:55:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:55:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:55:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:55:09 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:55:09 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:55:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:55:09 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 04:55:09 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-27 04:55:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:55:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:55:09 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:55:09 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:55:09 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:55:09 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:55:09 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:55:10 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:55:10 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:55:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:55:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:55:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:55:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:55:11 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 04:55:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:55:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:55:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:55:11 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 04:55:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:55:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:55:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:55:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:55:11 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:55:11 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:55:11 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 04:55:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:55:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:55:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:55:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:55:12 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 04:55:12 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 04:55:12 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:55:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:55:12 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:55:12 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:55:13 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 04:55:13 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 04:55:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:55:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:55:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:55:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:55:13 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 04:55:14 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 04:55:14 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 04:55:15 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 04:55:15 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 04:55:16 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 04:55:16 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 04:55:17 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 04:55:17 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 04:55:18 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 04:55:18 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 04:55:19 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 04:55:19 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-27 04:55:20 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-27 04:55:20 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-27 04:55:21 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-27 04:55:21 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-27 04:55:22 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-27 04:55:22 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-27 04:55:23 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-27 04:55:23 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-27 04:55:24 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-27 04:55:24 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-27 04:55:24 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-27 04:55:25 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-27 04:55:25 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-27 04:55:26 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-27 04:55:26 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-27 04:55:27 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2025-04-27 04:55:27 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2025-04-27 04:55:28 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2025-04-27 04:55:28 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2025-04-27 04:55:29 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2025-04-27 04:55:29 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2025-04-27 04:55:30 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2025-04-27 04:55:30 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2025-04-27 04:55:31 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2025-04-27 04:55:31 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2025-04-27 04:55:32 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2025-04-27 04:55:32 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2025-04-27 04:55:33 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2025-04-27 04:55:33 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2025-04-27 04:55:34 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2025-04-27 04:55:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:55:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:55:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:55:34 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:55:34 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:55:34 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:55:34 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:55:34 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:55:34 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:55:34 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:55:34 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:55:34 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:55:34 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=5470 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:55:34 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:55:34 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:55:34 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=5470 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:55:34 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=5470 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:55:34 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=5470 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:55:34 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=5470 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:55:34 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=5470 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:55:34 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=5471 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:55:34 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=5471 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:55:34 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=5471 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:55:34 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=5471 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:55:34 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=5471 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:55:34 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=5471 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:55:34 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=5471 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:55:34 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=5471 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:55:39 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:55:39 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:55:39 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:55:39 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:55:39 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:55:39 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:55:39 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:55:39 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:55:39 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:55:39 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:55:39 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:55:39 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:55:39 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:55:39 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:55:39 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:55:39 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:55:39 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:55:39 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:55:39 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:55:39 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:55:39 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:55:39 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:55:39 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:55:39 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:55:39 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:55:39 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:55:39 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:55:39 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:55:39 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:55:39 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:55:39 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:55:39 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:55:39 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:55:39 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:55:39 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:55:39 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:55:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:55:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:55:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:55:39 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:55:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:55:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:55:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:55:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:55:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:55:39 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:55:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:55:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:55:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:55:39 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:55:39 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:55:39 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:55:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:55:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:55:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:55:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:55:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:55:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:55:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:55:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:55:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:55:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:55:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:55:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:55:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:55:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:55:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:55:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:55:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:55:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:55:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:55:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:55:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:55:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:55:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:55:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:55:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:55:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:55:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:55:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:55:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:55:39 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:55:39 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:55:39 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:55:39 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:55:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:55:39 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:55:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:55:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:55:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:55:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:55:39 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:55:39 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:55:39 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:55:39 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:55:40 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:55:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:55:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:55:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:55:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:55:40 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:55:41 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:55:41 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:55:41 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:55:41 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:55:41 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:55:41 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 04:55:42 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 04:55:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:55:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:55:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:55:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:55:42 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 04:55:43 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 04:55:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:55:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:55:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:55:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:55:43 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 04:55:44 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 04:55:44 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:55:44 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:55:44 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:55:44 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:55:44 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 04:55:45 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 04:55:45 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 04:55:46 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 04:55:46 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 04:55:46 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 04:55:47 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 04:55:47 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 04:55:48 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 04:55:48 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 04:55:49 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 04:55:49 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 04:55:50 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-27 04:55:50 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-27 04:55:51 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-27 04:55:51 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-27 04:55:52 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-27 04:55:52 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-27 04:55:53 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-27 04:55:53 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-27 04:55:54 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-27 04:55:54 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-27 04:55:55 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-27 04:55:55 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-27 04:55:56 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-27 04:55:56 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-27 04:55:57 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-27 04:55:57 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-27 04:55:57 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2025-04-27 04:55:58 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2025-04-27 04:55:58 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2025-04-27 04:55:59 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2025-04-27 04:55:59 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2025-04-27 04:56:00 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2025-04-27 04:56:00 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2025-04-27 04:56:01 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2025-04-27 04:56:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:56:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:56:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:56:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:56:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:56:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:56:01 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:56:01 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:56:01 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:56:01 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:56:01 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:56:01 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:56:01 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:56:06 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:56:06 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:56:06 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:56:06 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:56:06 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:56:06 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:56:06 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:56:06 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:56:06 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:56:06 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:56:06 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:56:06 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:56:06 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:56:06 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:56:06 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:56:06 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:56:06 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:56:06 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:56:06 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:56:06 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:56:06 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:56:06 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:56:06 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:56:06 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:56:06 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:56:06 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:56:06 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:56:06 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:56:06 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:56:06 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:56:06 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:56:06 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:56:06 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:56:06 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:56:06 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:56:06 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:56:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:56:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:56:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:56:06 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:56:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:56:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:56:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:56:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:56:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:56:06 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:56:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:56:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:56:06 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:56:06 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:56:06 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:56:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:56:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:56:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:56:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:56:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:56:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:56:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:56:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:56:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:56:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:56:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:56:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:56:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:56:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:56:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:56:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:56:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:56:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:56:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:56:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:56:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:56:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:56:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:56:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:56:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:56:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:56:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:56:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:56:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:56:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:56:06 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:56:06 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:56:06 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:56:06 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:56:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:56:06 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:56:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:56:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:56:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:56:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:56:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:56:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:56:06 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:56:06 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:56:07 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:56:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:56:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:56:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:56:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:56:07 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:56:08 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:56:08 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:56:08 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:56:08 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:56:08 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:56:08 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 04:56:09 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 04:56:09 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:56:09 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:56:09 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:56:09 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:56:09 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 04:56:10 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 04:56:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:56:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:56:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:56:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:56:10 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 04:56:11 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 04:56:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:56:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:56:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:56:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:56:11 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 04:56:12 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 04:56:12 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 04:56:13 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 04:56:13 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 04:56:14 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 04:56:14 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 04:56:15 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 04:56:15 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 04:56:16 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 04:56:16 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 04:56:16 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 04:56:17 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-27 04:56:17 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-27 04:56:18 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-27 04:56:18 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-27 04:56:19 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-27 04:56:19 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-27 04:56:20 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-27 04:56:20 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-27 04:56:21 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-27 04:56:21 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-27 04:56:22 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-27 04:56:22 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-27 04:56:23 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-27 04:56:23 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-27 04:56:24 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-27 04:56:24 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-27 04:56:25 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2025-04-27 04:56:25 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2025-04-27 04:56:25 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2025-04-27 04:56:26 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2025-04-27 04:56:26 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2025-04-27 04:56:27 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2025-04-27 04:56:27 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2025-04-27 04:56:28 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2025-04-27 04:56:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:56:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:56:28 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:56:28 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:56:28 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:56:28 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:56:28 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:56:28 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:56:28 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:56:28 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:56:28 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:56:28 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:56:28 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4703 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:56:28 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:56:28 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4703 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:56:28 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4703 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:56:28 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4703 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:56:28 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4703 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:56:28 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4703 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:56:28 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4704 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:56:28 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4704 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:56:28 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4704 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:56:28 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4704 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:56:28 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4704 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:56:28 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4704 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:56:28 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4704 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:56:28 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4704 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:56:33 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:56:33 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:56:33 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:56:33 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:56:33 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:56:33 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:56:33 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:56:33 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:56:33 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:56:33 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:56:33 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:56:33 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:56:33 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:56:33 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:56:33 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:56:33 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:56:33 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:56:33 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:56:33 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:56:33 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:56:33 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:56:33 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:56:33 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:56:33 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:56:33 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:56:33 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:56:33 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:56:33 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:56:33 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:56:33 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:56:33 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:56:33 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:56:33 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:56:33 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:56:33 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:56:33 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:56:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:56:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:56:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:56:33 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:56:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:56:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:56:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:56:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:56:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:56:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:56:33 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:56:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:56:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:56:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:56:33 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:56:33 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:56:33 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:56:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:56:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:56:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:56:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:56:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:56:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:56:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:56:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:56:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:56:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:56:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:56:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:56:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:56:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:56:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:56:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:56:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:56:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:56:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:56:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:56:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:56:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:56:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:56:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:56:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:56:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:56:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:56:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:56:33 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:56:33 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:56:33 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:56:33 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:56:33 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:56:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:56:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:56:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:56:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:56:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:56:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:56:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:56:33 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:56:33 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:56:34 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:56:34 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:56:34 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:56:34 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:56:34 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:56:34 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:56:35 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:56:35 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:56:35 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:56:35 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:56:35 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:56:35 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 04:56:36 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 04:56:36 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:56:36 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:56:36 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:56:36 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:56:36 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 04:56:37 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 04:56:37 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:56:37 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:56:37 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:56:37 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:56:37 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 04:56:38 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 04:56:38 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:56:38 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:56:38 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:56:38 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:56:38 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 04:56:39 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 04:56:39 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 04:56:40 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 04:56:40 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 04:56:41 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 04:56:41 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 04:56:42 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 04:56:42 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 04:56:42 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 04:56:43 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 04:56:43 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 04:56:44 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-27 04:56:44 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-27 04:56:45 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-27 04:56:45 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-27 04:56:46 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-27 04:56:46 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-27 04:56:47 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-27 04:56:47 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-27 04:56:48 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-27 04:56:48 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-27 04:56:49 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-27 04:56:49 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-27 04:56:50 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-27 04:56:50 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-27 04:56:51 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-27 04:56:51 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-27 04:56:51 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2025-04-27 04:56:52 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2025-04-27 04:56:52 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2025-04-27 04:56:53 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2025-04-27 04:56:53 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2025-04-27 04:56:54 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2025-04-27 04:56:54 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2025-04-27 04:56:55 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2025-04-27 04:56:55 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2025-04-27 04:56:56 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2025-04-27 04:56:56 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2025-04-27 04:56:57 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2025-04-27 04:56:57 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2025-04-27 04:56:58 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2025-04-27 04:56:58 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2025-04-27 04:56:59 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2025-04-27 04:56:59 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2025-04-27 04:57:00 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2025-04-27 04:57:00 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2025-04-27 04:57:01 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2025-04-27 04:57:01 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2025-04-27 04:57:02 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2025-04-27 04:57:02 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2025-04-27 04:57:03 [DEBUG] clck_gen.py:102 IND CLOCK 6324
2025-04-27 04:57:03 [DEBUG] clck_gen.py:102 IND CLOCK 6426
2025-04-27 04:57:03 [DEBUG] clck_gen.py:102 IND CLOCK 6528
2025-04-27 04:57:04 [DEBUG] clck_gen.py:102 IND CLOCK 6630
2025-04-27 04:57:04 [DEBUG] clck_gen.py:102 IND CLOCK 6732
2025-04-27 04:57:05 [DEBUG] clck_gen.py:102 IND CLOCK 6834
2025-04-27 04:57:05 [DEBUG] clck_gen.py:102 IND CLOCK 6936
2025-04-27 04:57:06 [DEBUG] clck_gen.py:102 IND CLOCK 7038
2025-04-27 04:57:06 [DEBUG] clck_gen.py:102 IND CLOCK 7140
2025-04-27 04:57:07 [DEBUG] clck_gen.py:102 IND CLOCK 7242
2025-04-27 04:57:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:57:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:57:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:57:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:57:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:57:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:57:07 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:57:07 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:57:07 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:57:07 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:57:07 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:57:07 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:57:07 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:57:07 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=7280 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:57:07 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=7280 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:57:07 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=7280 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:57:07 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=7280 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:57:07 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=7280 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:57:07 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=7281 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:57:07 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=7281 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:57:07 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=7281 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:57:07 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=7281 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:57:07 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=7281 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:57:07 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=7281 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:57:07 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=7281 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:57:07 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=7281 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:57:12 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:57:12 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:57:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:57:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:57:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:57:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:57:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:57:12 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:57:12 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:57:12 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:57:12 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:57:12 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:57:12 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:57:12 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:57:12 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:57:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:57:12 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:57:12 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:57:12 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:57:12 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:57:12 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:57:12 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:57:12 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:57:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:57:12 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:57:12 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:57:12 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:57:12 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:57:12 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:57:12 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:57:12 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:57:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:57:12 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:57:12 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:57:12 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:57:12 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:57:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:57:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:57:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:57:12 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:57:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:57:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:57:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:57:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:57:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:57:12 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:57:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:57:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:57:12 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:57:12 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:57:12 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:57:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:57:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:57:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:57:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:57:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:57:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:57:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:57:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:57:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:57:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:57:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:57:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:57:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:57:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:57:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:57:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:57:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:57:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:57:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:57:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:57:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:57:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:57:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:57:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:57:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:57:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:57:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:57:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:57:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:57:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:57:12 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:57:13 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:57:13 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:57:13 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:57:13 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:57:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:57:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:57:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:57:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:57:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:57:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:57:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:57:13 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:57:13 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:57:13 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:57:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:57:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:57:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:57:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:57:13 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:57:14 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:57:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:57:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:57:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:57:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:57:14 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 04:57:15 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 04:57:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:57:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:57:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:57:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:57:15 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 04:57:16 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 04:57:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:57:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:57:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:57:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:57:16 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 04:57:17 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 04:57:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:57:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:57:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:57:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:57:17 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 04:57:18 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 04:57:18 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 04:57:19 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 04:57:19 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 04:57:20 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 04:57:20 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 04:57:21 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 04:57:21 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 04:57:22 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 04:57:22 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 04:57:23 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 04:57:23 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-27 04:57:23 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-27 04:57:24 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-27 04:57:24 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-27 04:57:25 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-27 04:57:25 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-27 04:57:26 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-27 04:57:26 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-27 04:57:27 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-27 04:57:27 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-27 04:57:28 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-27 04:57:28 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-27 04:57:29 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-27 04:57:29 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-27 04:57:30 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-27 04:57:30 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-27 04:57:31 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2025-04-27 04:57:31 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2025-04-27 04:57:32 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2025-04-27 04:57:32 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2025-04-27 04:57:32 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2025-04-27 04:57:33 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2025-04-27 04:57:33 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2025-04-27 04:57:34 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2025-04-27 04:57:34 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2025-04-27 04:57:35 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2025-04-27 04:57:35 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2025-04-27 04:57:36 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2025-04-27 04:57:36 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2025-04-27 04:57:37 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2025-04-27 04:57:37 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2025-04-27 04:57:38 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2025-04-27 04:57:38 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2025-04-27 04:57:39 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2025-04-27 04:57:39 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2025-04-27 04:57:40 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2025-04-27 04:57:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:57:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:57:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:57:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:57:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:57:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:57:40 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:57:40 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:57:40 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:57:40 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:57:40 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:57:40 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:57:40 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:57:40 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=6013 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:57:40 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=6013 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:57:40 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=6013 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:57:40 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=6013 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:57:40 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=6013 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:57:40 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=6013 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:57:45 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:57:45 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:57:45 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:57:45 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:57:45 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:57:45 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:57:45 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:57:45 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:57:45 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:57:45 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:57:45 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:57:45 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:57:45 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:57:45 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:57:45 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:57:45 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:57:45 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:57:45 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:57:45 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:57:45 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:57:45 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:57:45 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:57:45 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:57:45 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:57:45 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:57:45 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:57:45 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:57:45 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:57:45 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:57:45 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:57:45 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:57:45 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:57:45 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:57:45 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:57:45 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:57:45 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:57:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:57:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:57:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:57:45 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:57:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:57:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:57:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:57:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:57:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:57:45 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:57:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:57:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:57:45 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:57:45 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:57:45 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:57:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:57:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:57:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:57:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:57:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:57:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:57:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:57:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:57:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:57:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:57:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:57:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:57:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:57:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:57:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:57:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:57:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:57:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:57:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:57:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:57:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:57:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:57:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:57:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:57:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:57:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:57:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:57:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:57:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:57:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:57:45 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:57:46 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:57:46 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:57:46 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:57:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:57:46 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:57:46 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:57:46 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:57:46 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:57:46 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:57:46 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:57:46 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:57:46 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:57:46 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:57:46 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:57:46 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:57:46 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:57:46 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=126 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:57:46 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=126 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:57:46 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=126 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:57:46 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=126 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:57:46 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=126 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:57:46 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=127 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:57:46 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=127 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:57:46 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=127 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:57:46 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=127 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:57:46 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=127 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:57:46 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=127 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:57:46 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=127 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:57:46 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=127 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:57:46 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=128 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:57:46 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=128 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:57:46 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=128 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:57:46 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=128 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:57:46 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=128 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:57:46 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=128 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:57:46 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=128 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:57:46 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=128 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:57:51 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:57:51 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:57:51 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:57:51 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:57:51 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:57:51 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:57:51 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:57:51 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:57:51 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:57:51 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:57:51 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:57:51 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:57:51 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:57:51 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:57:51 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:57:51 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:57:51 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:57:51 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:57:51 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:57:51 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:57:51 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:57:51 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:57:51 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:57:51 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:57:51 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:57:51 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:57:51 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:57:51 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:57:51 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:57:51 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:57:51 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:57:51 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:57:51 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:57:51 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:57:51 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:57:51 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:57:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:57:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:57:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:57:51 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:57:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:57:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:57:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:57:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:57:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:57:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:57:51 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:57:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:57:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:57:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:57:51 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:57:51 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:57:51 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:57:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:57:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:57:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:57:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:57:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:57:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:57:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:57:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:57:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:57:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:57:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:57:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:57:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:57:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:57:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:57:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:57:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:57:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:57:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:57:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:57:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:57:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:57:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:57:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:57:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:57:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:57:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:57:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:57:51 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:57:51 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:57:51 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:57:51 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:57:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:57:51 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:57:51 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:57:51 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:57:51 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:57:51 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:57:51 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:57:51 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:57:51 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:57:51 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:57:51 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:57:51 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:57:51 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:57:51 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=124 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:57:51 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=124 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:57:51 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=124 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:57:51 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=124 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:57:51 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=124 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:57:56 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:57:56 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:57:56 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:57:56 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:57:56 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:57:56 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:57:56 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:57:56 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:57:56 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:57:56 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:57:56 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:57:56 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:57:56 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:57:56 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:57:56 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:57:56 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:57:56 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:57:56 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:57:56 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:57:56 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:57:56 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:57:56 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:57:56 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:57:56 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:57:56 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:57:56 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:57:56 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:57:56 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:57:56 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:57:56 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:57:56 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:57:56 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:57:56 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:57:56 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:57:56 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:57:56 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:57:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:57:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:57:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:57:56 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:57:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:57:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:57:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:57:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:57:56 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:57:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:57:56 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:57:56 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:57:56 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:57:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:57:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:57:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:57:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:57:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:57:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:57:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:57:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:57:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:57:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:57:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:57:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:57:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:57:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:57:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:57:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:57:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:57:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:57:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:57:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:57:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:57:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:57:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:57:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:57:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:57:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:57:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:57:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:57:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:57:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:57:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:57:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:57:56 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:57:57 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:57:57 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:57:57 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:57:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:57:57 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:57:57 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:57:57 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:57:57 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:57:57 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:57:57 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:57:57 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:57:57 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:57:57 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:57:57 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:57:57 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:57:57 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:57:57 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=123 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:57:57 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=123 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:57:57 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=123 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:57:57 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=123 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:57:57 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=123 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:57:57 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=123 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:57:57 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=124 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:57:57 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=124 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:57:57 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=124 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:57:57 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=124 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:57:57 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=124 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:57:57 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=124 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:57:57 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=124 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:57:57 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=124 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:58:02 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:58:02 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:58:02 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:58:02 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:58:02 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:58:02 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:58:02 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:58:02 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:58:02 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:58:02 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:58:02 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:58:02 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:58:02 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:58:02 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:58:02 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:58:02 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:58:02 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:58:02 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:58:02 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:58:02 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:58:02 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:58:02 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:58:02 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:58:02 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:58:02 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:58:02 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:58:02 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:58:02 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:58:02 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:58:02 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:58:02 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:58:02 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:58:02 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:58:02 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:58:02 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:58:02 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:58:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:58:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:58:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:58:02 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:58:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:58:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:58:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:58:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:58:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:58:02 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:58:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:58:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:58:02 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:58:02 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:58:02 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:58:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:58:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:58:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:58:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:58:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:58:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:58:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:58:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:58:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:58:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:58:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:58:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:58:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:58:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:58:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:58:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:58:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:58:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:58:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:58:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:58:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:58:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:58:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:58:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:58:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:58:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:58:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:58:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:58:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:58:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:58:02 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:58:02 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:58:02 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:58:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:58:03 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:58:03 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:58:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:58:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:58:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:58:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:58:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:58:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:58:03 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:58:03 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:58:03 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:58:03 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:58:03 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:58:03 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:58:03 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:58:03 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:58:04 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:58:04 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:58:04 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:58:04 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:58:04 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:58:04 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 04:58:05 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 04:58:05 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:58:05 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:58:05 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:58:05 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:58:05 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 04:58:06 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 04:58:06 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:58:06 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:58:06 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:58:06 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:58:06 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 04:58:07 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 04:58:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:58:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:58:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:58:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:58:07 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 04:58:08 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 04:58:08 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 04:58:09 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 04:58:09 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 04:58:10 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 04:58:10 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 04:58:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:58:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:58:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:58:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:58:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:58:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:58:11 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:58:11 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:58:11 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:58:11 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:58:11 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:58:11 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:58:11 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:58:11 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1837 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:58:11 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1837 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:58:11 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1837 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:58:11 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1837 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:58:11 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1837 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:58:11 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1837 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:58:11 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1838 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:58:11 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1838 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:58:11 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1838 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:58:11 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1838 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:58:11 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1838 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:58:11 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1838 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:58:11 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1838 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:58:11 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1838 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:58:16 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:58:16 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:58:16 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:58:16 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:58:16 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:58:16 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:58:16 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:58:16 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:58:16 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:58:16 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:58:16 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:58:16 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:58:16 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:58:16 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:58:16 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:58:16 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:58:16 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:58:16 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:58:16 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:58:16 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:58:16 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:58:16 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:58:16 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:58:16 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:58:16 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:58:16 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:58:16 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:58:16 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:58:16 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:58:16 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:58:16 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:58:16 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:58:16 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:58:16 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:58:16 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:58:16 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:58:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:58:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:58:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:58:16 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:58:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:58:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:58:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:58:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:58:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:58:16 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:58:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:58:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:58:16 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:58:16 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:58:16 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:58:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:58:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:58:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:58:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:58:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:58:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:58:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:58:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:58:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:58:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:58:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:58:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:58:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:58:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:58:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:58:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:58:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:58:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:58:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:58:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:58:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:58:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:58:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:58:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:58:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:58:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:58:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:58:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:58:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:58:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:58:16 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:58:16 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:58:16 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:58:16 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:58:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:58:16 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:58:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:58:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:58:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:58:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:58:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:58:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:58:16 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:58:16 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:58:17 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:58:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:58:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:58:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:58:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:58:17 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:58:18 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:58:18 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:58:18 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:58:18 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:58:18 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:58:18 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 04:58:18 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 04:58:19 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:58:19 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:58:19 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:58:19 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:58:19 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 04:58:19 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 04:58:20 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:58:20 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:58:20 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:58:20 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:58:20 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 04:58:20 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 04:58:21 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:58:21 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:58:21 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:58:21 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:58:21 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 04:58:21 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 04:58:22 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 04:58:22 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 04:58:23 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 04:58:23 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 04:58:24 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 04:58:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:58:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:58:24 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:58:24 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:58:24 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:58:24 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:58:24 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:58:24 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:58:24 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:58:24 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:58:24 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:58:24 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:58:24 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:58:24 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1827 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:58:24 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1827 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:58:24 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1827 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:58:24 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1827 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:58:24 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1827 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:58:24 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1827 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:58:29 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:58:29 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:58:29 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:58:29 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:58:29 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:58:29 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:58:29 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:58:29 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:58:29 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:58:29 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:58:29 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:58:29 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:58:29 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:58:29 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:58:29 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:58:29 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:58:29 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:58:29 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:58:29 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:58:29 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:58:29 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:58:29 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:58:29 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:58:29 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:58:29 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:58:29 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:58:29 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:58:29 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:58:29 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:58:29 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:58:29 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:58:29 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:58:29 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:58:29 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:58:29 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:58:29 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:58:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:58:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:58:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:58:29 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:58:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:58:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:58:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:58:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:58:29 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:58:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:58:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:58:29 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:58:29 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:58:29 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:58:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:58:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:58:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:58:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:58:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:58:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:58:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:58:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:58:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:58:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:58:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:58:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:58:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:58:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:58:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:58:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:58:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:58:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:58:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:58:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:58:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:58:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:58:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:58:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:58:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:58:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:58:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:58:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:58:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:58:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:58:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:58:29 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:58:30 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:58:30 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:58:30 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:58:30 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:58:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:58:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:58:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:58:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:58:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:58:30 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:58:30 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:58:30 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:58:30 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:58:30 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:58:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:58:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:58:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:58:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:58:31 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:58:31 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:58:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:58:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:58:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:58:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:58:32 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 04:58:32 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 04:58:32 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:58:32 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:58:32 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:58:32 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:58:33 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 04:58:33 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 04:58:33 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:58:33 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:58:33 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:58:33 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:58:33 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 04:58:34 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 04:58:34 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:58:34 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:58:34 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:58:34 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:58:34 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 04:58:35 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 04:58:35 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 04:58:36 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 04:58:36 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 04:58:37 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 04:58:37 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 04:58:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:58:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:58:38 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:58:38 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:58:38 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:58:38 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:58:38 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:58:38 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:58:38 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:58:38 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:58:38 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:58:38 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:58:38 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:58:43 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:58:43 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:58:43 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:58:43 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:58:43 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:58:43 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:58:43 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:58:43 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:58:43 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:58:43 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:58:43 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:58:43 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:58:43 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:58:43 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:58:43 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:58:43 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:58:43 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:58:43 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:58:43 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:58:43 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:58:43 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:58:43 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:58:43 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:58:43 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:58:43 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:58:43 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:58:43 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:58:43 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:58:43 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:58:43 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:58:43 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:58:43 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:58:43 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:58:43 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:58:43 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:58:43 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:58:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:58:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:58:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:58:43 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:58:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:58:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:58:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:58:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:58:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:58:43 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:58:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:58:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:58:43 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:58:43 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:58:43 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:58:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:58:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:58:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:58:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:58:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:58:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:58:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:58:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:58:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:58:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:58:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:58:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:58:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:58:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:58:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:58:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:58:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:58:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:58:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:58:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:58:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:58:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:58:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:58:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:58:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:58:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:58:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:58:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:58:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:58:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:58:43 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:58:43 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:58:43 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:58:43 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:58:43 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:58:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:58:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:58:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:58:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:58:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:58:43 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:58:43 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:58:43 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:58:43 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:58:44 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:58:44 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:58:44 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:58:44 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:58:44 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:58:44 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:58:45 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:58:45 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:58:45 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:58:45 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:58:45 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:58:45 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 04:58:46 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 04:58:46 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:58:46 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:58:46 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:58:46 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:58:46 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 04:58:47 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 04:58:47 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:58:47 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:58:47 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:58:47 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:58:47 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 04:58:48 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 04:58:48 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:58:48 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:58:48 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:58:48 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:58:48 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 04:58:48 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 04:58:49 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 04:58:49 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 04:58:50 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 04:58:50 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 04:58:51 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 04:58:51 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:58:51 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:58:51 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 04:58:51 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:58:51 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:58:51 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:58:51 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:58:51 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:58:51 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:58:51 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:58:51 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:58:51 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:58:51 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:58:51 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:58:56 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:58:56 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:58:56 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:58:56 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:58:56 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:58:56 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:58:56 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:58:56 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:58:56 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:58:56 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:58:56 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:58:56 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:58:56 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:58:56 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:58:56 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:58:56 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:58:56 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:58:56 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:58:56 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:58:56 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:58:56 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:58:56 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:58:56 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:58:56 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:58:56 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:58:56 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:58:56 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:58:56 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:58:56 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:58:56 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:58:56 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:58:56 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:58:56 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:58:56 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:58:56 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:58:56 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:58:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:58:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:58:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:58:56 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:58:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:58:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:58:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:58:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:58:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:58:56 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:58:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:58:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:58:56 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:58:56 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:58:56 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:58:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:58:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:58:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:58:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:58:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:58:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:58:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:58:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:58:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:58:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:58:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:58:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:58:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:58:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:58:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:58:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:58:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:58:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:58:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:58:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:58:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:58:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:58:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:58:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:58:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:58:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:58:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:58:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:58:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:58:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:58:56 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:58:57 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:58:57 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:58:57 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:58:57 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:58:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:58:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:58:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:58:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:58:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:58:57 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:58:57 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:58:57 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:58:57 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:58:57 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:58:57 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:58:57 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:58:57 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:58:57 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:58:58 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:58:58 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:58:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:58:58 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:58:58 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:58:58 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:58:59 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 04:58:59 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 04:58:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:58:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:58:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:58:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:59:00 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 04:59:00 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 04:59:00 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:59:00 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:59:00 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:59:00 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:59:01 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 04:59:01 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 04:59:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:59:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:59:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:59:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:59:02 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 04:59:02 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 04:59:03 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 04:59:03 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 04:59:04 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 04:59:04 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 04:59:04 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 04:59:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:59:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:59:05 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:59:05 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:59:05 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:59:05 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:59:05 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:59:05 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:59:05 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:59:05 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:59:05 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:59:05 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1828 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:59:05 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:59:05 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:59:05 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1828 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:59:05 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1828 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:59:05 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1828 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:59:05 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1828 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:59:05 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1828 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:59:10 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:59:10 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:59:10 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:59:10 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:59:10 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:59:10 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:59:10 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:59:10 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:59:10 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:59:10 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:59:10 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:59:10 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:59:10 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:59:10 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:59:10 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:59:10 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:59:10 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:59:10 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:59:10 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:59:10 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:59:10 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:59:10 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:59:10 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:59:10 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:59:10 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:59:10 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:59:10 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:59:10 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:59:10 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:59:10 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:59:10 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:59:10 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:59:10 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:59:10 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:59:10 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:59:10 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:59:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:59:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:59:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:59:10 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:59:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:59:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:59:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:59:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:59:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:59:10 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:59:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:59:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:59:10 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:59:10 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:59:10 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:59:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:59:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:59:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:59:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:59:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:59:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:59:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:59:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:59:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:59:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:59:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:59:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:59:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:59:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:59:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:59:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:59:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:59:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:59:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:59:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:59:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:59:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:59:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:59:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:59:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:59:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:59:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:59:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:59:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:59:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:59:10 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:59:10 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:59:10 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:59:10 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:59:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:59:10 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:59:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:59:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:59:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:59:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:59:10 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:59:10 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:59:10 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:59:10 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:59:11 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:59:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:59:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:59:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:59:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:59:11 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:59:12 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:59:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:59:12 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:59:12 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:59:12 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:59:12 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 04:59:13 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 04:59:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:59:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:59:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:59:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:59:13 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 04:59:14 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 04:59:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:59:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:59:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:59:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:59:14 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 04:59:15 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 04:59:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:59:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:59:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:59:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:59:15 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 04:59:16 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 04:59:16 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 04:59:17 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 04:59:17 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 04:59:18 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 04:59:18 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 04:59:19 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 04:59:19 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 04:59:19 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 04:59:20 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 04:59:20 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 04:59:21 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-27 04:59:21 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-27 04:59:22 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-27 04:59:22 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-27 04:59:23 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-27 04:59:23 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-27 04:59:24 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-27 04:59:24 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-27 04:59:25 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-27 04:59:25 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-27 04:59:26 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-27 04:59:26 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-27 04:59:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:59:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:59:27 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:59:27 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:59:27 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:59:27 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:59:27 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:59:27 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:59:27 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:59:27 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:59:27 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:59:27 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3553 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:59:27 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:59:27 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:59:27 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3554 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:59:27 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3554 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:59:27 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3554 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:59:27 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3554 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:59:27 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3554 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:59:27 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3554 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:59:27 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3554 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:59:27 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3554 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:59:32 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:59:32 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:59:32 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:59:32 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:59:32 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:59:32 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:59:32 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:59:32 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:59:32 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:59:32 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:59:32 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:59:32 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:59:32 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:59:32 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:59:32 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:59:32 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:59:32 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:59:32 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:59:32 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:59:32 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:59:32 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:59:32 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:59:32 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:59:32 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:59:32 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:59:32 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:59:32 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:59:32 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:59:32 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:59:32 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:59:32 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:59:32 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:59:32 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:59:32 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:59:32 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:59:32 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:59:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:59:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:59:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:59:32 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:59:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:59:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:59:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:59:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:59:32 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:59:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:59:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:59:32 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:59:32 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:59:32 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:59:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:59:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:59:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:59:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:59:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:59:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:59:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:59:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:59:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:59:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:59:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:59:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:59:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:59:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:59:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:59:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:59:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:59:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:59:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:59:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:59:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:59:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:59:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:59:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:59:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:59:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:59:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:59:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:59:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:59:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:59:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:59:32 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:59:32 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:59:32 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:59:32 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:59:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:59:32 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:59:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:59:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:59:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:59:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:59:32 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:59:32 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:59:32 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:59:32 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:59:33 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:59:33 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:59:33 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:59:33 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:59:33 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:59:33 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:59:33 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:59:34 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:59:34 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:59:34 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:59:34 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:59:34 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 04:59:34 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 04:59:35 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:59:35 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:59:35 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:59:35 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:59:35 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 04:59:35 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 04:59:36 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:59:36 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:59:36 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:59:36 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:59:36 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 04:59:36 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 04:59:37 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:59:37 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:59:37 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:59:37 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:59:37 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 04:59:37 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 04:59:38 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 04:59:38 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 04:59:39 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 04:59:39 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 04:59:40 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 04:59:40 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 04:59:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:59:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:59:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:59:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:59:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:59:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:59:40 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:59:40 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:59:40 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:59:40 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:59:40 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 04:59:40 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:59:40 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:59:40 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1841 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:59:40 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1841 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:59:40 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1841 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:59:40 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1841 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:59:40 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1841 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:59:40 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1841 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 04:59:45 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 04:59:45 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 04:59:45 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:59:45 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:59:45 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:59:45 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:59:45 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 04:59:45 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:59:45 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:59:45 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 04:59:45 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 04:59:45 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 04:59:45 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 04:59:45 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:59:45 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:59:45 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 04:59:45 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 04:59:45 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 04:59:45 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 04:59:45 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 04:59:45 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 04:59:45 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:59:45 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:59:45 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 04:59:45 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 04:59:45 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 04:59:45 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 04:59:45 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 04:59:45 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 04:59:45 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:59:45 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 04:59:45 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 04:59:45 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 04:59:45 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 04:59:45 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 04:59:45 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 04:59:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 04:59:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 04:59:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 04:59:45 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 04:59:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 04:59:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 04:59:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 04:59:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:59:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 04:59:45 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 04:59:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:59:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:59:45 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 04:59:45 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 04:59:45 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 04:59:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:59:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:59:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:59:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 04:59:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:59:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:59:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:59:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:59:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:59:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:59:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:59:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:59:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:59:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:59:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:59:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:59:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:59:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 04:59:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:59:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:59:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:59:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:59:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:59:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:59:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:59:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 04:59:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:59:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 04:59:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:59:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 04:59:45 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 04:59:46 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 04:59:46 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 04:59:46 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 04:59:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 04:59:46 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 04:59:46 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 04:59:46 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 04:59:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 04:59:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 04:59:46 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 04:59:46 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 04:59:46 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 04:59:46 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 04:59:46 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 04:59:46 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:59:46 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:59:46 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:59:46 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:59:47 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 04:59:47 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 04:59:47 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:59:47 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:59:47 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:59:47 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:59:48 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 04:59:48 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 04:59:48 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:59:48 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:59:48 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:59:48 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:59:49 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 04:59:49 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 04:59:49 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:59:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:59:49 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:59:49 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:59:50 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 04:59:50 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 04:59:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 04:59:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 04:59:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 04:59:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 04:59:50 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 04:59:51 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 04:59:51 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 04:59:52 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 04:59:52 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 04:59:53 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 04:59:53 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 04:59:54 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 04:59:54 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 04:59:55 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 04:59:55 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 04:59:56 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 04:59:56 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-27 04:59:57 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-27 04:59:57 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-27 04:59:58 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-27 04:59:58 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-27 04:59:59 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-27 04:59:59 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-27 04:59:59 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-27 05:00:00 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-27 05:00:00 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-27 05:00:01 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-27 05:00:01 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-27 05:00:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:00:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:00:02 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:00:02 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:00:02 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:00:02 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:00:02 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:00:02 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:00:02 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:00:02 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:00:02 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:00:02 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:00:02 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:00:07 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:00:07 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:00:07 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:00:07 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:00:07 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:00:07 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:00:07 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:00:07 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:00:07 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:00:07 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:00:07 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:00:07 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:00:07 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:00:07 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:00:07 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:00:07 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:00:07 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:00:07 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:00:07 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:00:07 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:00:07 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:00:07 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:00:07 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:00:07 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:00:07 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:00:07 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:00:07 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:00:07 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:00:07 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:00:07 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:00:07 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:00:07 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:00:07 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:00:07 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:00:07 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:00:07 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:00:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:00:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:00:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:00:07 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:00:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:00:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:00:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:00:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:00:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:00:07 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:00:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:00:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:00:07 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:00:07 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:00:07 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:00:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:00:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:00:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:00:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:00:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:00:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:00:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:00:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:00:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:00:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:00:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:00:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:00:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:00:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:00:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:00:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:00:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:00:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:00:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:00:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:00:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:00:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:00:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:00:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:00:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:00:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:00:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:00:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:00:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:00:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:00:07 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:00:07 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:00:07 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:00:07 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:00:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:00:07 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:00:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:00:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:00:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:00:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:00:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:00:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:00:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:00:07 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:00:07 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:00:07 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:00:07 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:00:07 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:00:07 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:00:07 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=123 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:00:07 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:00:07 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=123 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:00:07 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=123 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:00:07 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=123 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:00:07 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=123 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:00:07 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=123 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:00:07 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=124 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:00:07 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=124 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:00:07 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=124 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:00:07 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=124 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:00:07 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=124 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:00:07 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=124 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:00:07 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=124 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:00:07 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=124 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:00:12 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:00:12 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:00:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:00:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:00:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:00:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:00:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:00:12 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:00:12 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:00:12 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:00:12 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:00:12 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:00:12 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:00:12 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:00:12 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:00:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:00:12 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:00:12 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:00:12 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:00:12 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:00:12 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:00:12 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:00:12 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:00:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:00:12 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:00:12 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:00:12 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:00:12 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:00:12 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:00:12 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:00:12 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:00:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:00:12 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:00:12 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:00:12 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:00:12 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:00:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:00:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:00:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:00:12 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:00:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:00:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:00:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:00:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:00:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:00:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:00:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:00:12 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:00:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:00:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:00:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:00:12 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:00:12 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:00:12 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:00:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:00:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:00:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:00:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:00:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:00:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:00:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:00:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:00:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:00:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:00:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:00:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:00:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:00:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:00:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:00:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:00:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:00:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:00:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:00:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:00:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:00:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:00:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:00:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:00:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:00:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:00:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:00:12 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:00:13 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:00:13 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:00:13 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:00:13 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:00:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:00:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:00:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:00:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:00:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:00:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:00:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:00:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:00:13 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:00:13 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:00:13 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:00:13 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:00:13 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:00:13 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:00:13 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:00:13 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=123 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:00:13 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=123 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:00:13 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=123 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:00:13 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=123 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:00:13 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=123 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:00:13 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=123 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:00:18 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:00:18 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:00:18 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:00:18 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:00:18 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:00:18 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:00:18 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:00:18 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:00:18 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:00:18 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:00:18 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:00:18 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:00:18 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:00:18 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:00:18 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:00:18 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:00:18 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:00:18 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:00:18 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:00:18 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:00:18 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:00:18 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:00:18 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:00:18 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:00:18 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:00:18 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:00:18 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:00:18 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:00:18 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:00:18 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:00:18 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:00:18 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:00:18 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:00:18 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:00:18 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:00:18 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:00:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:00:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:00:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:00:18 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:00:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:00:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:00:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:00:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:00:18 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:00:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:00:18 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:00:18 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:00:18 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:00:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:00:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:00:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:00:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:00:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:00:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:00:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:00:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:00:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:00:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:00:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:00:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:00:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:00:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:00:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:00:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:00:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:00:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:00:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:00:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:00:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:00:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:00:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:00:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:00:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:00:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:00:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:00:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:00:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:00:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:00:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:00:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:00:18 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:00:19 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:00:19 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:00:19 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:00:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:00:19 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:00:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:00:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:00:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:00:19 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:00:19 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:00:19 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:00:19 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:00:19 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:00:19 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:00:19 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:00:19 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:00:19 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:00:19 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:00:19 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:00:19 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=128 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:00:19 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=128 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:00:19 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=128 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:00:19 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=128 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:00:19 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=129 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:00:19 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=129 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:00:19 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=129 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:00:19 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=129 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:00:19 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=129 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:00:19 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=129 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:00:19 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=129 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:00:19 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=129 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:00:24 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:00:24 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:00:24 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:00:24 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:00:24 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:00:24 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:00:24 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:00:24 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:00:24 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:00:24 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:00:24 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:00:24 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:00:24 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:00:24 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:00:24 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:00:24 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:00:24 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:00:24 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:00:24 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:00:24 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:00:24 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:00:24 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:00:24 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:00:24 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:00:24 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:00:24 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:00:24 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:00:24 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:00:24 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:00:24 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:00:24 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:00:24 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:00:24 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:00:24 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:00:24 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:00:24 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:00:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:00:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:00:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:00:24 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:00:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:00:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:00:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:00:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:00:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:00:24 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:00:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:00:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:00:24 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:00:24 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:00:24 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:00:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:00:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:00:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:00:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:00:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:00:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:00:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:00:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:00:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:00:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:00:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:00:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:00:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:00:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:00:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:00:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:00:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:00:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:00:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:00:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:00:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:00:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:00:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:00:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:00:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:00:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:00:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:00:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:00:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:00:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:00:24 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:00:24 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:00:24 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:00:24 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:00:24 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:00:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:00:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:00:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:00:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:00:24 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:00:24 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:00:24 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:00:24 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:00:24 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:00:24 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:00:24 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:00:24 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:00:24 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:00:24 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:00:24 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:00:24 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=126 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:00:24 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=126 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:00:24 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=126 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:00:24 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=126 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:00:24 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=126 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:00:24 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=126 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:00:24 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=127 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:00:24 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=127 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:00:24 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=127 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:00:24 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=127 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:00:24 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=127 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:00:24 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=127 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:00:24 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=127 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:00:24 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=127 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:00:29 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:00:29 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:00:29 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:00:29 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:00:29 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:00:29 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:00:29 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:00:29 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:00:29 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:00:29 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:00:29 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:00:29 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:00:29 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:00:29 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:00:29 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:00:29 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:00:29 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:00:29 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:00:29 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:00:29 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:00:29 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:00:29 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:00:29 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:00:29 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:00:29 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:00:29 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:00:29 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:00:29 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:00:29 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:00:29 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:00:29 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:00:29 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:00:29 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:00:29 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:00:29 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:00:29 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:00:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:00:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:00:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:00:29 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:00:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:00:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:00:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:00:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:00:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:00:29 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:00:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:00:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:00:29 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:00:29 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:00:29 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:00:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:00:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:00:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:00:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:00:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:00:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:00:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:00:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:00:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:00:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:00:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:00:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:00:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:00:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:00:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:00:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:00:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:00:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:00:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:00:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:00:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:00:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:00:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:00:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:00:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:00:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:00:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:00:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:00:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:00:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:00:29 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:00:30 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:00:30 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:00:30 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:00:30 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:00:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:00:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:00:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:00:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:00:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:00:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:00:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:00:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:00:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:00:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:00:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:00:30 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:00:30 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:00:30 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:00:30 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:00:30 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:00:30 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:00:30 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:00:30 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=126 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:00:30 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=126 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:00:30 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=126 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:00:30 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=126 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:00:30 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=126 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:00:30 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=126 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:00:35 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:00:35 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:00:35 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:00:35 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:00:35 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:00:35 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:00:35 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:00:35 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:00:35 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:00:35 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:00:35 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:00:35 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:00:35 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:00:35 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:00:35 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:00:35 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:00:35 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:00:35 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:00:35 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:00:35 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:00:35 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:00:35 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:00:35 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:00:35 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:00:35 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:00:35 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:00:35 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:00:35 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:00:35 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:00:35 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:00:35 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:00:35 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:00:35 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:00:35 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:00:35 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:00:35 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:00:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:00:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:00:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:00:35 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:00:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:00:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:00:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:00:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:00:35 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:00:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:00:35 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:00:35 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:00:35 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:00:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:00:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:00:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:00:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:00:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:00:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:00:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:00:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:00:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:00:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:00:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:00:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:00:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:00:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:00:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:00:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:00:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:00:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:00:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:00:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:00:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:00:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:00:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:00:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:00:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:00:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:00:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:00:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:00:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:00:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:00:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:00:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:00:35 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:00:35 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:00:35 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:00:35 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:00:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:00:35 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:00:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:00:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:00:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:00:36 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:00:36 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:00:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:00:36 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:00:36 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:00:36 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:00:36 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:00:36 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:00:36 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:00:36 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:00:36 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:00:36 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:00:36 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:00:36 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:00:36 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=126 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:00:36 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=126 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:00:36 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=126 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:00:36 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=126 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:00:36 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=126 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:00:36 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=126 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:00:36 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=126 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:00:41 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:00:41 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:00:41 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:00:41 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:00:41 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:00:41 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:00:41 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:00:41 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:00:41 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:00:41 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:00:41 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:00:41 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:00:41 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:00:41 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:00:41 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:00:41 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:00:41 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:00:41 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:00:41 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:00:41 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:00:41 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:00:41 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:00:41 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:00:41 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:00:41 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:00:41 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:00:41 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:00:41 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:00:41 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:00:41 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:00:41 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:00:41 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:00:41 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:00:41 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:00:41 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:00:41 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:00:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:00:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:00:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:00:41 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:00:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:00:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:00:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:00:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:00:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:00:41 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:00:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:00:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:00:41 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:00:41 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:00:41 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:00:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:00:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:00:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:00:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:00:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:00:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:00:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:00:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:00:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:00:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:00:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:00:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:00:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:00:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:00:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:00:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:00:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:00:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:00:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:00:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:00:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:00:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:00:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:00:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:00:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:00:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:00:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:00:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:00:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:00:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:00:41 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:00:41 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:00:41 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:00:41 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:00:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:00:41 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:00:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:00:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:00:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:00:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:00:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:00:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:00:41 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:00:41 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:00:42 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:00:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:00:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:00:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:00:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:00:42 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 05:00:42 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 05:00:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:00:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:00:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:00:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:00:43 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 05:00:43 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 05:00:44 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:00:44 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:00:44 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:00:44 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:00:44 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 05:00:44 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 05:00:45 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:00:45 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:00:45 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:00:45 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:00:45 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 05:00:45 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 05:00:46 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:00:46 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:00:46 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:00:46 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:00:46 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 05:00:46 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 05:00:47 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 05:00:47 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 05:00:48 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 05:00:48 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 05:00:49 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 05:00:49 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 05:00:50 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 05:00:50 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 05:00:51 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 05:00:51 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 05:00:52 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-27 05:00:52 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-27 05:00:52 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-27 05:00:53 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-27 05:00:53 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-27 05:00:54 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-27 05:00:54 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-27 05:00:55 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-27 05:00:55 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-27 05:00:56 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-27 05:00:56 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-27 05:00:57 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-27 05:00:57 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-27 05:00:58 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-27 05:00:58 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-27 05:00:59 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-27 05:00:59 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2025-04-27 05:01:00 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2025-04-27 05:01:00 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2025-04-27 05:01:01 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2025-04-27 05:01:01 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2025-04-27 05:01:02 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2025-04-27 05:01:02 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2025-04-27 05:01:02 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2025-04-27 05:01:03 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2025-04-27 05:01:03 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2025-04-27 05:01:04 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2025-04-27 05:01:04 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2025-04-27 05:01:05 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2025-04-27 05:01:05 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2025-04-27 05:01:06 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2025-04-27 05:01:06 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2025-04-27 05:01:07 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2025-04-27 05:01:07 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2025-04-27 05:01:08 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2025-04-27 05:01:08 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2025-04-27 05:01:09 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2025-04-27 05:01:09 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2025-04-27 05:01:10 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2025-04-27 05:01:10 [DEBUG] clck_gen.py:102 IND CLOCK 6324
2025-04-27 05:01:11 [DEBUG] clck_gen.py:102 IND CLOCK 6426
2025-04-27 05:01:11 [DEBUG] clck_gen.py:102 IND CLOCK 6528
2025-04-27 05:01:12 [DEBUG] clck_gen.py:102 IND CLOCK 6630
2025-04-27 05:01:12 [DEBUG] clck_gen.py:102 IND CLOCK 6732
2025-04-27 05:01:13 [DEBUG] clck_gen.py:102 IND CLOCK 6834
2025-04-27 05:01:13 [DEBUG] clck_gen.py:102 IND CLOCK 6936
2025-04-27 05:01:13 [DEBUG] clck_gen.py:102 IND CLOCK 7038
2025-04-27 05:01:14 [DEBUG] clck_gen.py:102 IND CLOCK 7140
2025-04-27 05:01:14 [DEBUG] clck_gen.py:102 IND CLOCK 7242
2025-04-27 05:01:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:01:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:01:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:01:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:01:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:01:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:01:15 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:01:15 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:01:15 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:01:15 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:01:15 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:01:15 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:01:15 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:01:15 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=7279 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:01:15 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=7279 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:01:15 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=7279 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:01:15 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=7279 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:01:15 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=7279 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:01:15 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=7279 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:01:15 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=7280 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:01:15 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=7280 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:01:15 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=7280 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:01:15 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=7280 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:01:15 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=7280 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:01:15 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=7280 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:01:15 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=7280 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:01:15 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=7280 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:01:20 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:01:20 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:01:20 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:01:20 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:01:20 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:01:20 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:01:20 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:01:20 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:01:20 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:01:20 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:01:20 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:01:20 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:01:20 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:01:20 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:01:20 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:01:20 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:01:20 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:01:20 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:01:20 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:01:20 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:01:20 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:01:20 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:01:20 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:01:20 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:01:20 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:01:20 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:01:20 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:01:20 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:01:20 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:01:20 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:01:20 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:01:20 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:01:20 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:01:20 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:01:20 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:01:20 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:01:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:01:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:01:20 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:01:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:01:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:01:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:01:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:01:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:01:20 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:01:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:01:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:01:20 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:01:20 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:01:20 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:01:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:01:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:01:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:01:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:01:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:01:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:01:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:01:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:01:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:01:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:01:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:01:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:01:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:01:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:01:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:01:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:01:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:01:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:01:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:01:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:01:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:01:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:01:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:01:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:01:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:01:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:01:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:01:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:01:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:01:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:01:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:01:20 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:01:20 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:01:20 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:01:20 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:01:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:01:20 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:01:21 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:01:21 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:01:21 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:01:21 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:01:21 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:01:21 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 05:01:22 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 05:01:22 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:01:22 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:01:22 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:01:22 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:01:22 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 05:01:23 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 05:01:23 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:01:23 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:01:23 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:01:23 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:01:23 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 05:01:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:01:23 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:01:23 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:01:23 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:01:23 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:01:23 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:01:23 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:01:23 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:01:23 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:01:23 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:01:23 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:01:23 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:01:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=757 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:01:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=757 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:01:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=757 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:01:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=757 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:01:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=757 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:01:28 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:01:28 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:01:28 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:01:28 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:01:28 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:01:28 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:01:28 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:01:28 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:01:28 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:01:28 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:01:28 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:01:28 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:01:28 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:01:28 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:01:28 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:01:28 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:01:28 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:01:28 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:01:28 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:01:28 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:01:28 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:01:28 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:01:28 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:01:28 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:01:28 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:01:28 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:01:28 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:01:28 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:01:28 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:01:28 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:01:28 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:01:28 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:01:28 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:01:28 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:01:28 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:01:28 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:01:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:01:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:01:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:01:28 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:01:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:01:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:01:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:01:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:01:28 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:01:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:01:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:01:28 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:01:28 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:01:28 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:01:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:01:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:01:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:01:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:01:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:01:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:01:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:01:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:01:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:01:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:01:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:01:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:01:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:01:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:01:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:01:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:01:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:01:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:01:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:01:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:01:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:01:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:01:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:01:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:01:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:01:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:01:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:01:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:01:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:01:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:01:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:01:28 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:01:29 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:01:29 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:01:29 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:01:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:01:29 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:01:29 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:01:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:01:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:01:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:01:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:01:30 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 05:01:30 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 05:01:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:01:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:01:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:01:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:01:31 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 05:01:31 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 05:01:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:01:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:01:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:01:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:01:32 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 05:01:32 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 05:01:32 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:01:32 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:01:32 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:01:32 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:01:33 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 05:01:33 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 05:01:33 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:01:33 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:01:33 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:01:33 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:01:33 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 05:01:34 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 05:01:34 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 05:01:35 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:01:35 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:01:35 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:01:35 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:01:35 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:01:35 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:01:35 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:01:35 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:01:35 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:01:35 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:01:35 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:01:35 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1400 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:01:35 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1400 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:01:35 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1400 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:01:35 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1400 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:01:35 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1400 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:01:40 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:01:40 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:01:40 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:01:40 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:01:40 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:01:40 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:01:40 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:01:40 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:01:40 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:01:40 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:01:40 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:01:40 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:01:40 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:01:40 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:01:40 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:01:40 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:01:40 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:01:40 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:01:40 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:01:40 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:01:40 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:01:40 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:01:40 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:01:40 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:01:40 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:01:40 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:01:40 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:01:40 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:01:40 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:01:40 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:01:40 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:01:40 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:01:40 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:01:40 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:01:40 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:01:40 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:01:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:01:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:01:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:01:40 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:01:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:01:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:01:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:01:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:01:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:01:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:01:40 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:01:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:01:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:01:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:01:40 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:01:40 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:01:40 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:01:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:01:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:01:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:01:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:01:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:01:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:01:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:01:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:01:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:01:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:01:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:01:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:01:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:01:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:01:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:01:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:01:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:01:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:01:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:01:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:01:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:01:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:01:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:01:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:01:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:01:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:01:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:01:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:01:40 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:01:40 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:01:40 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:01:40 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:01:40 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:01:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:01:41 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:01:41 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:01:41 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:01:41 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:01:41 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:01:41 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 05:01:42 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 05:01:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:01:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:01:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:01:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:01:42 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 05:01:43 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 05:01:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:01:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:01:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:01:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:01:43 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 05:01:44 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 05:01:44 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:01:44 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:01:44 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:01:44 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:01:44 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 05:01:45 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 05:01:45 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:01:45 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:01:45 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:01:45 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:01:45 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 05:01:46 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 05:01:46 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 05:01:46 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:01:46 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:01:46 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:01:46 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:01:46 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:01:46 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:01:46 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:01:46 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:01:46 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:01:46 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:01:46 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1400 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:01:46 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:01:46 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1400 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:01:46 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1400 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:01:46 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1400 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:01:46 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1400 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:01:51 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:01:51 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:01:51 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:01:51 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:01:51 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:01:51 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:01:51 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:01:51 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:01:51 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:01:51 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:01:51 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:01:51 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:01:51 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:01:51 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:01:51 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:01:51 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:01:51 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:01:51 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:01:51 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:01:51 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:01:51 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:01:51 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:01:51 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:01:51 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:01:51 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:01:51 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:01:51 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:01:51 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:01:51 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:01:51 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:01:51 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:01:51 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:01:51 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:01:51 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:01:51 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:01:51 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:01:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:01:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:01:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:01:51 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:01:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:01:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:01:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:01:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:01:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:01:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:01:51 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:01:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:01:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:01:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:01:51 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:01:51 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:01:51 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:01:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:01:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:01:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:01:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:01:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:01:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:01:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:01:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:01:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:01:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:01:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:01:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:01:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:01:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:01:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:01:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:01:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:01:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:01:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:01:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:01:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:01:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:01:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:01:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:01:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:01:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:01:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:01:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:01:51 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:01:52 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:01:52 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:01:52 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:01:52 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:01:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:01:52 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:01:52 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:01:52 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:01:52 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:01:52 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:01:53 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 05:01:53 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 05:01:53 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:01:53 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:01:53 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:01:53 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:01:54 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 05:01:54 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 05:01:54 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:01:54 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:01:54 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:01:54 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:01:55 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 05:01:55 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 05:01:55 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:01:55 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:01:55 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:01:55 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:01:56 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 05:01:56 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 05:01:56 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:01:56 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:01:56 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:01:56 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:01:57 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 05:01:57 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 05:01:58 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 05:01:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:01:58 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:01:58 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:01:58 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:01:58 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:01:58 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:01:58 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:01:58 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:01:58 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:01:58 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1395 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:01:58 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:01:58 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:01:58 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1395 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:01:58 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1395 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:02:03 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:02:03 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:02:03 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:02:03 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:02:03 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:02:03 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:02:03 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:02:03 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:02:03 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:02:03 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:02:03 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:02:03 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:02:03 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:02:03 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:02:03 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:02:03 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:02:03 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:02:03 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:02:03 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:02:03 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:02:03 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:02:03 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:02:03 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:02:03 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:02:03 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:02:03 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:02:03 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:02:03 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:02:03 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:02:03 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:02:03 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:02:03 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:02:03 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:02:03 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:02:03 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:02:03 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:02:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:02:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:02:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:02:03 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:02:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:02:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:02:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:02:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:02:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:02:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:02:03 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:02:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:02:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:02:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:02:03 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:02:03 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:02:03 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:02:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:02:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:02:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:02:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:02:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:02:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:02:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:02:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:02:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:02:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:02:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:02:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:02:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:02:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:02:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:02:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:02:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:02:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:02:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:02:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:02:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:02:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:02:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:02:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:02:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:02:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:02:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:02:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:02:03 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:02:03 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:02:03 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:02:03 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:02:03 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:02:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:02:04 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:02:04 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:02:04 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:02:04 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:02:04 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:02:04 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 05:02:05 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 05:02:05 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:02:05 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:02:05 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:02:05 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:02:05 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 05:02:06 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 05:02:06 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:02:06 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:02:06 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:02:06 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:02:06 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 05:02:07 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 05:02:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:02:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:02:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:02:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:02:07 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 05:02:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:02:08 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 05:02:08 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:02:08 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:02:08 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:02:08 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:02:08 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 05:02:09 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 05:02:09 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 05:02:10 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 05:02:10 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 05:02:11 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 05:02:11 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 05:02:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:02:12 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:02:12 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:02:12 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:02:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:02:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:02:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:02:12 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:02:12 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:02:12 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:02:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:02:12 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1827 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:02:12 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1827 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:02:12 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1827 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:02:12 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1827 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:02:12 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1827 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:02:12 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1827 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:02:12 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1828 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:02:12 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1828 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:02:12 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1828 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:02:12 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1828 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:02:12 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1828 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:02:12 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1828 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:02:12 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1828 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:02:12 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1828 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:02:17 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:02:17 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:02:17 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:02:17 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:02:17 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:02:17 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:02:17 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:02:17 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:02:17 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:02:17 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:02:17 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:02:17 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:02:17 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:02:17 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:02:17 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:02:17 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:02:17 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:02:17 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:02:17 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:02:17 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:02:17 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:02:17 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:02:17 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:02:17 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:02:17 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:02:17 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:02:17 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:02:17 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:02:17 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:02:17 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:02:17 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:02:17 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:02:17 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:02:17 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:02:17 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:02:17 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:02:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:02:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:02:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:02:17 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:02:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:02:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:02:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:02:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:02:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:02:17 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:02:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:02:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:02:17 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:02:17 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:02:17 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:02:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:02:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:02:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:02:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:02:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:02:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:02:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:02:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:02:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:02:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:02:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:02:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:02:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:02:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:02:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:02:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:02:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:02:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:02:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:02:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:02:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:02:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:02:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:02:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:02:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:02:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:02:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:02:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:02:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:02:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:02:17 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:02:17 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:02:17 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:02:17 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:02:17 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:02:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:02:18 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:02:18 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:02:18 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:02:18 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:02:18 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:02:18 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 05:02:18 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 05:02:19 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:02:19 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:02:19 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:02:19 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:02:19 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 05:02:19 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 05:02:20 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:02:20 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:02:20 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:02:20 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:02:20 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 05:02:20 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 05:02:21 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:02:21 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:02:21 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:02:21 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:02:21 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 05:02:21 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:02:21 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:02:21 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:02:21 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:02:21 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:02:21 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:02:21 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:02:21 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:02:21 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:02:21 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:02:21 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:02:21 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=974 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:02:21 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=974 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:02:21 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=974 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:02:21 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=974 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:02:21 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=974 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:02:21 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=974 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:02:21 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=974 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:02:26 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:02:26 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:02:26 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:02:26 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:02:26 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:02:26 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:02:26 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:02:26 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:02:26 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:02:26 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:02:26 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:02:26 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:02:26 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:02:26 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:02:26 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:02:26 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:02:26 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:02:26 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:02:26 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:02:26 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:02:26 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:02:26 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:02:26 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:02:26 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:02:26 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:02:26 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:02:26 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:02:26 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:02:26 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:02:26 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:02:26 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:02:26 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:02:26 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:02:26 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:02:26 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:02:26 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:02:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:02:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:02:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:02:26 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:02:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:02:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:02:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:02:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:02:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:02:26 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:02:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:02:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:02:26 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:02:26 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:02:26 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:02:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:02:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:02:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:02:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:02:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:02:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:02:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:02:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:02:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:02:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:02:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:02:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:02:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:02:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:02:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:02:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:02:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:02:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:02:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:02:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:02:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:02:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:02:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:02:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:02:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:02:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:02:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:02:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:02:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:02:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:02:26 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:02:27 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:02:27 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:02:27 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:02:27 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:02:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:02:27 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:02:27 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:02:27 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:02:27 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:02:27 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:02:27 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:02:27 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:02:27 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:02:27 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:02:27 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:02:27 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:02:27 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=123 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:02:27 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=123 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:02:27 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=123 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:02:27 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=123 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:02:27 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=123 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:02:27 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=123 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:02:32 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:02:32 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:02:32 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:02:32 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:02:32 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:02:32 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:02:32 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:02:32 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:02:32 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:02:32 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:02:32 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:02:32 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:02:32 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:02:32 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:02:32 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:02:32 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:02:32 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:02:32 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:02:32 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:02:32 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:02:32 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:02:32 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:02:32 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:02:32 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:02:32 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:02:32 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:02:32 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:02:32 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:02:32 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:02:32 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:02:32 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:02:32 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:02:32 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:02:32 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:02:32 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:02:32 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:02:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:02:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:02:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:02:32 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:02:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:02:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:02:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:02:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:02:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:02:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:02:32 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:02:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:02:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:02:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:02:32 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:02:32 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:02:32 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:02:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:02:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:02:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:02:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:02:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:02:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:02:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:02:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:02:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:02:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:02:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:02:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:02:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:02:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:02:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:02:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:02:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:02:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:02:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:02:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:02:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:02:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:02:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:02:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:02:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:02:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:02:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:02:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:02:32 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:02:32 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:02:32 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:02:32 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:02:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:02:32 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:02:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:02:32 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:02:32 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:02:32 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:02:32 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:02:32 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:02:32 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:02:32 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:02:32 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:02:32 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:02:32 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:02:32 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:02:32 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=123 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:02:32 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=123 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:02:32 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=123 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:02:32 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=123 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:02:32 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=123 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:02:32 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=123 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:02:37 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:02:37 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:02:37 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:02:37 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:02:37 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:02:37 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:02:37 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:02:37 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:02:37 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:02:37 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:02:37 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:02:37 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:02:37 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:02:37 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:02:37 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:02:37 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:02:37 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:02:37 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:02:37 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:02:37 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:02:37 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:02:37 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:02:37 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:02:37 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:02:37 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:02:37 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:02:37 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:02:37 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:02:37 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:02:37 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:02:37 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:02:37 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:02:37 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:02:37 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:02:37 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:02:37 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:02:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:02:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:02:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:02:37 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:02:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:02:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:02:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:02:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:02:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:02:37 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:02:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:02:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:02:37 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:02:37 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:02:37 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:02:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:02:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:02:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:02:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:02:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:02:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:02:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:02:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:02:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:02:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:02:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:02:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:02:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:02:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:02:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:02:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:02:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:02:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:02:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:02:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:02:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:02:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:02:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:02:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:02:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:02:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:02:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:02:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:02:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:02:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:02:37 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:02:38 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:02:38 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:02:38 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:02:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:02:38 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:02:38 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:02:38 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:02:38 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:02:38 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:02:38 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:02:38 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:02:38 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:02:38 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:02:38 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:02:38 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:02:38 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:02:38 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=124 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:02:38 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=124 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:02:38 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=124 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:02:38 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=124 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:02:38 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=124 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:02:38 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=124 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:02:43 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:02:43 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:02:43 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:02:43 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:02:43 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:02:43 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:02:43 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:02:43 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:02:43 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:02:43 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:02:43 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:02:43 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:02:43 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:02:43 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:02:43 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:02:43 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:02:43 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:02:43 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:02:43 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:02:43 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:02:43 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:02:43 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:02:43 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:02:43 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:02:43 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:02:43 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:02:43 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:02:43 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:02:43 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:02:43 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:02:43 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:02:43 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:02:43 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:02:43 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:02:43 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:02:43 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:02:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:02:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:02:43 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:02:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:02:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:02:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:02:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:02:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:02:43 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:02:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:02:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:02:43 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:02:43 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:02:43 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:02:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:02:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:02:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:02:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:02:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:02:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:02:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:02:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:02:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:02:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:02:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:02:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:02:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:02:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:02:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:02:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:02:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:02:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:02:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:02:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:02:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:02:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:02:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:02:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:02:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:02:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:02:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:02:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:02:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:02:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:02:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:02:43 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:02:43 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:02:43 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:02:43 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:02:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:02:43 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:02:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:02:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:02:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:02:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:02:44 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:02:44 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:02:44 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:02:44 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:02:44 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:02:44 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:02:44 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:02:44 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:02:44 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:02:44 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 05:02:45 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 05:02:45 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:02:45 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:02:45 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:02:45 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:02:45 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 05:02:46 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 05:02:46 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:02:46 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:02:46 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:02:46 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:02:46 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 05:02:47 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:02:47 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=0, maio=1, ma_len=2
2025-04-27 05:02:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:02:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:02:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:02:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:02:47 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:02:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:02:47 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:02:47 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:02:47 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:02:47 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:02:47 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:02:47 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:02:47 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:02:47 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:02:47 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:02:47 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:02:47 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:02:52 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:02:52 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:02:52 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:02:52 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:02:52 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:02:52 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:02:52 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:02:52 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:02:52 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:02:52 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:02:52 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:02:52 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:02:52 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:02:52 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:02:52 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:02:52 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:02:52 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:02:52 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:02:52 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:02:52 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:02:52 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:02:52 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:02:52 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:02:52 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:02:52 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:02:52 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:02:52 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:02:52 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:02:52 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:02:52 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:02:52 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:02:52 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:02:52 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:02:52 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:02:52 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:02:52 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:02:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:02:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:02:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:02:52 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:02:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:02:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:02:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:02:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:02:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:02:52 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:02:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:02:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:02:52 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:02:52 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:02:52 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:02:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:02:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:02:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:02:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:02:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:02:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:02:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:02:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:02:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:02:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:02:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:02:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:02:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:02:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:02:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:02:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:02:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:02:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:02:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:02:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:02:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:02:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:02:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:02:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:02:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:02:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:02:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:02:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:02:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:02:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:02:52 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:02:52 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:02:52 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:02:52 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:02:52 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:02:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:02:52 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:02:52 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:02:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:02:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:02:52 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:02:52 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:02:52 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:02:52 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:02:53 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:02:53 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:02:53 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:02:53 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:02:53 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:02:53 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 05:02:54 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 05:02:54 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:02:54 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:02:54 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:02:54 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:02:54 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 05:02:55 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 05:02:55 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:02:55 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:02:55 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:02:55 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:02:55 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 05:02:55 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:02:55 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=0, maio=1, ma_len=2
2025-04-27 05:02:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:02:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:02:55 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 05:02:56 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:02:56 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:02:56 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:02:56 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:02:56 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 05:02:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:02:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:02:56 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:02:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:02:56 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:02:56 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:02:56 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:02:56 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:02:56 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:02:56 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:02:56 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:02:56 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:02:56 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:02:56 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:02:56 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:02:56 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=924 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:02:56 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=924 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:02:56 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=924 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:02:56 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=924 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:02:56 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=924 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:02:56 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=924 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:03:01 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:03:01 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:03:01 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:03:01 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:03:01 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:03:01 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:03:01 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:03:01 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:03:01 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:03:01 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:03:01 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:03:01 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:03:01 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:03:01 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:03:01 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:03:01 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:03:01 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:03:01 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:03:01 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:03:01 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:03:01 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:03:01 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:03:01 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:03:01 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:03:01 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:03:01 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:03:01 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:03:01 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:03:01 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:03:01 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:03:01 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:03:01 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:03:01 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:03:01 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:03:01 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:03:01 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:03:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:03:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:03:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:03:01 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:03:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:03:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:03:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:03:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:03:01 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:03:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:03:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:03:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:03:01 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:03:01 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:03:01 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:03:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:03:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:03:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:03:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:03:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:03:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:03:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:03:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:03:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:03:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:03:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:03:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:03:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:03:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:03:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:03:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:03:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:03:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:03:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:03:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:03:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:03:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:03:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:03:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:03:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:03:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:03:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:03:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:03:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:03:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:03:01 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:03:02 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:03:02 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:03:02 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:03:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:03:02 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:03:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:03:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:03:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:03:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:03:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:03:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:03:02 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:03:02 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:03:02 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:03:02 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:03:02 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:03:02 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:03:02 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:03:03 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 05:03:03 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 05:03:03 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:03:03 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:03:03 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:03:03 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:03:03 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 05:03:04 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 05:03:04 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:03:04 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:03:04 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:03:04 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:03:04 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 05:03:05 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:03:05 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=0, maio=1, ma_len=2
2025-04-27 05:03:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:03:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:03:05 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 05:03:05 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:03:05 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:03:05 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:03:05 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:03:05 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 05:03:06 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 05:03:06 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:03:06 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:03:06 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:03:06 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:03:06 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 05:03:07 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 05:03:07 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 05:03:08 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 05:03:08 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 05:03:09 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 05:03:09 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 05:03:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:03:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:03:10 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:03:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:03:10 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 05:03:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:03:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:03:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:03:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:03:10 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:03:10 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:03:10 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:03:10 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:03:10 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:03:10 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:03:10 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:03:10 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1840 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:03:10 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1840 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:03:10 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1840 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:03:10 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1840 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:03:10 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1840 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:03:10 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1840 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:03:10 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1840 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:03:15 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:03:15 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:03:15 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:03:15 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:03:15 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:03:15 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:03:15 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:03:15 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:03:15 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:03:15 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:03:15 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:03:15 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:03:15 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:03:15 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:03:15 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:03:15 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:03:15 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:03:15 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:03:15 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:03:15 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:03:15 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:03:15 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:03:15 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:03:15 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:03:15 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:03:15 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:03:15 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:03:15 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:03:15 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:03:15 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:03:15 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:03:15 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:03:15 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:03:15 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:03:15 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:03:15 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:03:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:03:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:03:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:03:15 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:03:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:03:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:03:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:03:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:03:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:03:15 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:03:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:03:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:03:15 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:03:15 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:03:15 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:03:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:03:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:03:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:03:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:03:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:03:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:03:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:03:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:03:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:03:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:03:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:03:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:03:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:03:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:03:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:03:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:03:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:03:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:03:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:03:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:03:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:03:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:03:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:03:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:03:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:03:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:03:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:03:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:03:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:03:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:03:15 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:03:15 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:03:15 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:03:15 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:03:15 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:03:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:03:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:03:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:03:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:03:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:03:15 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:03:15 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:03:15 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:03:15 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:03:16 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:03:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:03:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:03:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:03:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:03:16 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 05:03:17 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 05:03:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:03:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:03:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:03:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:03:17 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 05:03:18 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 05:03:18 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:03:18 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:03:18 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:03:18 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:03:18 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 05:03:18 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:03:18 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=0, maio=1, ma_len=2
2025-04-27 05:03:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:03:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:03:19 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 05:03:19 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:03:19 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:03:19 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:03:19 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:03:19 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 05:03:19 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 05:03:20 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:03:20 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:03:20 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:03:20 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:03:20 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 05:03:20 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 05:03:21 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 05:03:21 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 05:03:22 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 05:03:22 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 05:03:23 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 05:03:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:03:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:03:23 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:03:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:03:23 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:03:23 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:03:23 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:03:23 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:03:23 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:03:23 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:03:23 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:03:23 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:03:23 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:03:23 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:03:23 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:03:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1833 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:03:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1833 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:03:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1833 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:03:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1833 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:03:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1833 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:03:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1833 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:03:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1833 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:03:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1834 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:03:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1834 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:03:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1834 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:03:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1834 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:03:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1834 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:03:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1834 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:03:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1834 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:03:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1834 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:03:28 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:03:28 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:03:28 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:03:28 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:03:28 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:03:28 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:03:28 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:03:28 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:03:28 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:03:28 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:03:28 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:03:28 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:03:28 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:03:28 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:03:28 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:03:28 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:03:28 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:03:28 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:03:28 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:03:28 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:03:28 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:03:28 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:03:28 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:03:28 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:03:28 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:03:28 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:03:28 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:03:28 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:03:28 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:03:28 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:03:28 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:03:28 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:03:28 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:03:28 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:03:28 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:03:28 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:03:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:03:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:03:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:03:28 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:03:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:03:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:03:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:03:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:03:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:03:28 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:03:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:03:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:03:28 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:03:28 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:03:28 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:03:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:03:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:03:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:03:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:03:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:03:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:03:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:03:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:03:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:03:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:03:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:03:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:03:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:03:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:03:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:03:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:03:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:03:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:03:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:03:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:03:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:03:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:03:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:03:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:03:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:03:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:03:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:03:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:03:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:03:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:03:28 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:03:29 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:03:29 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:03:29 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:03:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:03:29 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:03:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:03:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:03:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:03:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:03:29 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:03:29 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:03:29 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:03:29 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:03:29 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:03:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:03:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:03:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:03:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:03:30 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 05:03:30 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 05:03:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:03:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:03:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:03:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:03:31 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 05:03:31 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 05:03:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:03:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:03:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:03:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:03:32 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 05:03:32 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:03:32 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=0, maio=1, ma_len=2
2025-04-27 05:03:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:03:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:03:32 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 05:03:32 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:03:32 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:03:32 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:03:32 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:03:33 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 05:03:33 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 05:03:33 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:03:33 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:03:33 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:03:33 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:03:34 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 05:03:34 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 05:03:34 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 05:03:35 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 05:03:35 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 05:03:36 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 05:03:36 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 05:03:37 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 05:03:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:03:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:03:37 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:03:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:03:37 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:03:37 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:03:37 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:03:37 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:03:37 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:03:37 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:03:37 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:03:37 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:03:37 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:03:37 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:03:37 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:03:42 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:03:42 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:03:42 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:03:42 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:03:42 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:03:42 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:03:42 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:03:42 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:03:42 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:03:42 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:03:42 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:03:42 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:03:42 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:03:42 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:03:42 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:03:42 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:03:42 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:03:42 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:03:42 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:03:42 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:03:42 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:03:42 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:03:42 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:03:42 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:03:42 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:03:42 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:03:42 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:03:42 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:03:42 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:03:42 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:03:42 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:03:42 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:03:42 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:03:42 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:03:42 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:03:42 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:03:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:03:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:03:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:03:42 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:03:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:03:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:03:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:03:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:03:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:03:42 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:03:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:03:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:03:42 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:03:42 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:03:42 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:03:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:03:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:03:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:03:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:03:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:03:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:03:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:03:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:03:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:03:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:03:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:03:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:03:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:03:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:03:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:03:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:03:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:03:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:03:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:03:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:03:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:03:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:03:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:03:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:03:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:03:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:03:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:03:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:03:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:03:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:03:42 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:03:42 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:03:42 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:03:42 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:03:42 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:03:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:03:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:03:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:03:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:03:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:03:42 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:03:42 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:03:42 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:03:42 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:03:42 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:03:42 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=0, maio=1, ma_len=2
2025-04-27 05:03:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:03:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:03:43 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:03:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:03:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:03:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:03:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:03:43 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 05:03:44 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 05:03:44 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:03:44 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:03:44 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:03:44 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:03:44 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 05:03:45 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 05:03:45 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:03:45 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:03:45 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:03:45 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:03:45 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 05:03:46 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 05:03:46 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:03:46 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:03:46 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:03:46 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:03:46 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 05:03:47 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 05:03:47 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:03:47 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:03:47 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:03:47 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:03:47 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 05:03:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:03:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:03:47 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:03:48 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:03:48 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:03:48 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:03:48 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:03:48 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:03:48 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:03:48 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:03:48 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:03:48 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:03:48 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:03:48 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:03:48 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1190 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:03:48 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1190 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:03:48 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1190 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:03:48 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1190 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:03:48 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1190 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:03:48 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1190 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:03:53 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:03:53 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:03:53 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:03:53 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:03:53 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:03:53 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:03:53 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:03:53 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:03:53 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:03:53 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:03:53 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:03:53 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:03:53 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:03:53 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:03:53 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:03:53 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:03:53 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:03:53 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:03:53 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:03:53 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:03:53 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:03:53 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:03:53 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:03:53 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:03:53 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:03:53 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:03:53 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:03:53 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:03:53 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:03:53 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:03:53 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:03:53 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:03:53 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:03:53 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:03:53 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:03:53 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:03:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:03:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:03:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:03:53 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:03:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:03:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:03:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:03:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:03:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:03:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:03:53 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:03:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:03:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:03:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:03:53 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:03:53 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:03:53 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:03:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:03:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:03:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:03:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:03:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:03:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:03:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:03:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:03:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:03:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:03:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:03:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:03:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:03:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:03:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:03:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:03:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:03:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:03:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:03:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:03:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:03:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:03:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:03:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:03:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:03:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:03:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:03:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:03:53 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:03:53 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:03:53 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:03:53 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:03:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:03:53 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:03:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:03:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:03:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:03:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:03:53 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:03:53 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:03:53 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:03:53 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:03:53 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:03:54 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:03:54 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:03:54 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:03:54 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:03:54 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 05:03:54 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 05:03:55 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:03:55 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:03:55 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:03:55 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:03:55 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 05:03:55 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 05:03:56 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:03:56 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:03:56 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:03:56 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:03:56 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 05:03:56 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:03:56 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=0, maio=1, ma_len=2
2025-04-27 05:03:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:03:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:03:56 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 05:03:57 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:03:57 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:03:57 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:03:57 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:03:57 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 05:03:57 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 05:03:58 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:03:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:03:58 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:03:58 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:03:58 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 05:03:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:03:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:03:58 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:03:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:03:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:03:58 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:03:58 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:03:58 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:03:58 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:03:58 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:03:58 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:03:58 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:03:58 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:03:58 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:03:58 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:03:58 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1195 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:03:58 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1195 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:03:58 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1195 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:03:58 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1195 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:03:58 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1195 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:03:58 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1195 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:03:58 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1196 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:03:58 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1196 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:03:58 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1196 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:03:58 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1196 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:03:58 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1196 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:03:58 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1196 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:03:58 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1196 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:03:58 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1196 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:04:03 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:04:03 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:04:03 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:04:03 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:04:03 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:04:03 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:04:03 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:04:03 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:04:03 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:04:03 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:04:03 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:04:03 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:04:03 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:04:03 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:04:03 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:04:03 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:04:03 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:04:03 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:04:03 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:04:03 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:04:03 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:04:03 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:04:03 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:04:03 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:04:03 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:04:03 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:04:03 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:04:03 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:04:03 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:04:03 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:04:03 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:04:03 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:04:03 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:04:03 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:04:03 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:04:03 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:04:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:04:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:04:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:04:03 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:04:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:04:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:04:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:04:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:04:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:04:03 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:04:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:04:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:04:03 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:04:03 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:04:03 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:04:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:04:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:04:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:04:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:04:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:04:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:04:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:04:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:04:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:04:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:04:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:04:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:04:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:04:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:04:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:04:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:04:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:04:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:04:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:04:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:04:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:04:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:04:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:04:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:04:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:04:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:04:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:04:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:04:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:04:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:04:03 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:04:04 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:04:04 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:04:04 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:04:04 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:04:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:04:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:04:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:04:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:04:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:04:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:04:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:04:04 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:04:04 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:04:04 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:04:04 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:04:04 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:04:04 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:04:04 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:04:05 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 05:04:05 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 05:04:05 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:04:05 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:04:05 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:04:05 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:04:06 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 05:04:06 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 05:04:06 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:04:06 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:04:06 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:04:06 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:04:06 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 05:04:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:04:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:04:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:04:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:04:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:04:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:04:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:04:07 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:04:07 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:04:07 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:04:07 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:04:07 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=775 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:04:07 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:04:07 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:04:07 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:04:07 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=775 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:04:07 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=775 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:04:07 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=776 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:04:07 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=776 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:04:07 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=776 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:04:07 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=776 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:04:07 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=776 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:04:07 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=776 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:04:07 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=776 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:04:07 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=776 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:04:12 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:04:12 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:04:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:04:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:04:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:04:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:04:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:04:12 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:04:12 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:04:12 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:04:12 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:04:12 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:04:12 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:04:12 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:04:12 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:04:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:04:12 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:04:12 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:04:12 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:04:12 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:04:12 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:04:12 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:04:12 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:04:12 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:04:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:04:12 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:04:12 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:04:12 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:04:12 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:04:12 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:04:12 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:04:12 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:04:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:04:12 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:04:12 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:04:12 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:04:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:04:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:04:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:04:12 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:04:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:04:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:04:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:04:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:04:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:04:12 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:04:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:04:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:04:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:04:12 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:04:12 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:04:12 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:04:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:04:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:04:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:04:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:04:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:04:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:04:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:04:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:04:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:04:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:04:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:04:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:04:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:04:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:04:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:04:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:04:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:04:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:04:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:04:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:04:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:04:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:04:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:04:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:04:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:04:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:04:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:04:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:04:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:04:12 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:04:12 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:04:12 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:04:12 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:04:12 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:04:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:04:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:04:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:04:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:04:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:04:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:04:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:04:12 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:04:12 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:04:13 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:04:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:04:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:04:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:04:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:04:13 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 05:04:14 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 05:04:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:04:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:04:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:04:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:04:14 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 05:04:15 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 05:04:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:04:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:04:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:04:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:04:15 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 05:04:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:04:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:04:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:04:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:04:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:04:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:04:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:04:15 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:04:15 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:04:15 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:04:15 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:04:15 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=785 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:04:15 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:04:15 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:04:15 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:04:15 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=785 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:04:15 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=786 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:04:15 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=786 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:04:15 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=786 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:04:15 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=786 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:04:15 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=786 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:04:15 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=786 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:04:15 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=786 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:04:15 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=786 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:04:20 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:04:20 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:04:20 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:04:20 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:04:20 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:04:20 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:04:20 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:04:20 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:04:20 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:04:20 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:04:20 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:04:21 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:04:21 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:04:21 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:04:21 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:04:21 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:04:21 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:04:21 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:04:21 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:04:21 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:04:21 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:04:21 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:04:21 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:04:21 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:04:21 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:04:21 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:04:21 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:04:21 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:04:21 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:04:21 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:04:21 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:04:21 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:04:21 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:04:21 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:04:21 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:04:21 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:04:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:04:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:04:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:04:21 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:04:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:04:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:04:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:04:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:04:21 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:04:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:04:21 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:04:21 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:04:21 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:04:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:04:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:04:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:04:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:04:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:04:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:04:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:04:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:04:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:04:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:04:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:04:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:04:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:04:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:04:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:04:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:04:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:04:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:04:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:04:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:04:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:04:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:04:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:04:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:04:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:04:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:04:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:04:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:04:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:04:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:04:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:04:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:04:21 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:04:21 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:04:21 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:04:21 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:04:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:04:21 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:04:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:04:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:04:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:04:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:04:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:04:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:04:21 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:04:21 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:04:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:04:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:04:21 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:04:21 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:04:21 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:04:21 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:04:21 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:04:21 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:04:21 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:04:21 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:04:21 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:04:21 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=173 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:04:21 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:04:21 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:04:21 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=173 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:04:21 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=173 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:04:21 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=173 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:04:21 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=173 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:04:21 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=174 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:04:21 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=174 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:04:21 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=174 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:04:21 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=174 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:04:21 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=174 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:04:21 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=174 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:04:21 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=174 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:04:21 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=174 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:04:26 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:04:26 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:04:26 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:04:26 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:04:26 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:04:26 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:04:26 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:04:26 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:04:26 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:04:26 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:04:26 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:04:26 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:04:26 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:04:26 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:04:26 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:04:26 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:04:26 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:04:26 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:04:26 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:04:26 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:04:26 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:04:26 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:04:26 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:04:26 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:04:26 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:04:26 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:04:26 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:04:26 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:04:26 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:04:26 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:04:26 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:04:26 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:04:26 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:04:26 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:04:26 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:04:26 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:04:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:04:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:04:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:04:26 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:04:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:04:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:04:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:04:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:04:26 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:04:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:04:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:04:26 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:04:26 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:04:26 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:04:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:04:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:04:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:04:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:04:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:04:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:04:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:04:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:04:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:04:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:04:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:04:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:04:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:04:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:04:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:04:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:04:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:04:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:04:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:04:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:04:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:04:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:04:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:04:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:04:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:04:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:04:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:04:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:04:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:04:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:04:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:04:26 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:04:27 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:04:27 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:04:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:04:27 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:04:27 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:04:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:04:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:04:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:04:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:04:27 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:04:27 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:04:27 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:04:27 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:04:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:04:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:04:27 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:04:27 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:04:27 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:04:27 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:04:27 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:04:27 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:04:27 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:04:27 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:04:27 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:04:27 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:04:27 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:04:32 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:04:32 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:04:32 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:04:32 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:04:32 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:04:32 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:04:32 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:04:32 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:04:32 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:04:32 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:04:32 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:04:32 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:04:32 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:04:32 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:04:32 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:04:32 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:04:32 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:04:32 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:04:32 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:04:32 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:04:32 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:04:32 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:04:32 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:04:32 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:04:32 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:04:32 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:04:32 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:04:32 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:04:32 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:04:32 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:04:32 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:04:32 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:04:32 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:04:32 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:04:32 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:04:32 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:04:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:04:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:04:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:04:32 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:04:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:04:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:04:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:04:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:04:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:04:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:04:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:04:32 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:04:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:04:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:04:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:04:32 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:04:32 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:04:32 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:04:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:04:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:04:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:04:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:04:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:04:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:04:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:04:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:04:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:04:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:04:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:04:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:04:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:04:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:04:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:04:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:04:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:04:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:04:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:04:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:04:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:04:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:04:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:04:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:04:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:04:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:04:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:04:32 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:04:33 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:04:33 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:04:33 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:04:33 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:04:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:04:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:04:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:04:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:04:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:04:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:04:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:04:33 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:04:33 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:04:33 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:04:33 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:04:33 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:04:33 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:04:33 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:04:34 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 05:04:34 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 05:04:34 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:04:34 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:04:34 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:04:34 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:04:35 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 05:04:35 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 05:04:35 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:04:35 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:04:35 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:04:35 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:04:36 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 05:04:36 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 05:04:36 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:04:36 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:04:36 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:04:36 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:04:36 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 05:04:37 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 05:04:37 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:04:37 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:04:37 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:04:37 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:04:37 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 05:04:38 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 05:04:38 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 05:04:39 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 05:04:39 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 05:04:40 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 05:04:40 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 05:04:41 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 05:04:41 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 05:04:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:04:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:04:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:04:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:04:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:04:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:04:42 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:04:42 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:04:42 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:04:42 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:04:42 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:04:42 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:04:42 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:04:42 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2010 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:04:42 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2010 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:04:42 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2010 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:04:42 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2010 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:04:42 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2010 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:04:42 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2010 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:04:42 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2011 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:04:42 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2011 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:04:42 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2011 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:04:42 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2011 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:04:42 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2011 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:04:42 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2011 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:04:42 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2011 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:04:42 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2011 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:04:47 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:04:47 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:04:47 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:04:47 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:04:47 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:04:47 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:04:47 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:04:47 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:04:47 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:04:47 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:04:47 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:04:47 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:04:47 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:04:47 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:04:47 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:04:47 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:04:47 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:04:47 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:04:47 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:04:47 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:04:47 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:04:47 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:04:47 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:04:47 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:04:47 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:04:47 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:04:47 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:04:47 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:04:47 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:04:47 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:04:47 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:04:47 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:04:47 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:04:47 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:04:47 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:04:47 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:04:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:04:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:04:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:04:47 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:04:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:04:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:04:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:04:47 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:04:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:04:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:04:47 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:04:47 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:04:47 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:04:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:04:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:04:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:04:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:04:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:04:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:04:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:04:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:04:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:04:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:04:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:04:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:04:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:04:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:04:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:04:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:04:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:04:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:04:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:04:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:04:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:04:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:04:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:04:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:04:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:04:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:04:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:04:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:04:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:04:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:04:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:04:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:04:47 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:04:47 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:04:47 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:04:47 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:04:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:04:47 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:04:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:04:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:04:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:04:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:04:47 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:04:47 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:04:47 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:04:47 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:04:48 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:04:48 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:04:48 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:04:48 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:04:48 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:04:48 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 05:04:49 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 05:04:49 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:04:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:04:49 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:04:49 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:04:49 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 05:04:49 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 05:04:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:04:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:04:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:04:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:04:50 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 05:04:50 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 05:04:51 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:04:51 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:04:51 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:04:51 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:04:51 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 05:04:51 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 05:04:52 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:04:52 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:04:52 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:04:52 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:04:52 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 05:04:52 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 05:04:53 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 05:04:53 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 05:04:54 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 05:04:54 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 05:04:55 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 05:04:55 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 05:04:56 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 05:04:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:04:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:04:56 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:04:56 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:04:56 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:04:56 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:04:56 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:04:56 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:04:56 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:04:56 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:04:56 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:04:56 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:04:56 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:04:56 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2023 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:04:56 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2023 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:04:56 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2023 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:04:56 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2023 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:04:56 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2023 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:04:56 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2023 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:04:56 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2024 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:04:56 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2024 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:04:56 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2024 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:04:56 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2024 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:04:56 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2024 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:04:56 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2024 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:04:56 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2024 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:04:56 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2024 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:04:56 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2025 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:04:56 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2025 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:04:56 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2025 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:04:56 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2025 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:04:56 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2025 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:04:56 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2025 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:04:56 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2025 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:04:56 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2025 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:05:01 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:05:01 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:05:01 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:05:01 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:05:01 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:05:01 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:05:01 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:05:01 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:05:01 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:05:01 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:05:01 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:05:01 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:05:01 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:05:01 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:05:01 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:05:01 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:05:01 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:05:01 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:05:01 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:05:01 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:05:01 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:05:01 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:05:01 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:05:01 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:05:01 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:05:01 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:05:01 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:05:01 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:05:01 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:05:01 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:05:01 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:05:01 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:05:01 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:05:01 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:05:01 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:05:01 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:05:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:05:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:05:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:05:01 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:05:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:05:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:05:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:05:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:05:01 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:05:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:05:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:05:01 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:05:01 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:05:01 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:05:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:05:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:05:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:05:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:05:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:05:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:05:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:05:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:05:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:05:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:05:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:05:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:05:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:05:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:05:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:05:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:05:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:05:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:05:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:05:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:05:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:05:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:05:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:05:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:05:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:05:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:05:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:05:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:05:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:05:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:05:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:05:01 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:05:02 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:05:02 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:05:02 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:05:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:05:02 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:05:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:05:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:05:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:05:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:05:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:05:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:05:02 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:05:02 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:05:02 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:05:02 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:05:02 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:05:02 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:05:02 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:05:03 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 05:05:03 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 05:05:03 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:05:03 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:05:03 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:05:03 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:05:03 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 05:05:04 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 05:05:04 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:05:04 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:05:04 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:05:04 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:05:04 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 05:05:05 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:05:05 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=0, maio=1, ma_len=2
2025-04-27 05:05:05 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:05:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:05:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:05:05 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 05:05:05 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:05:05 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:05:05 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:05:05 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:05:05 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 05:05:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:05:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:05:06 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:05:06 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:05:06 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:05:06 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:05:06 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:05:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:05:06 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:05:06 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:05:06 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:05:06 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:05:06 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:05:06 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:05:06 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:05:11 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:05:11 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:05:11 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:05:11 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:05:11 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:05:11 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:05:11 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:05:11 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:05:11 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:05:11 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:05:11 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:05:11 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:05:11 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:05:11 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:05:11 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:05:11 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:05:11 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:05:11 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:05:11 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:05:11 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:05:11 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:05:11 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:05:11 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:05:11 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:05:11 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:05:11 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:05:11 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:05:11 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:05:11 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:05:11 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:05:11 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:05:11 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:05:11 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:05:11 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:05:11 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:05:11 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:05:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:05:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:05:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:05:11 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:05:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:05:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:05:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:05:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:05:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:05:11 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:05:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:05:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:05:11 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:05:11 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:05:11 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:05:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:05:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:05:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:05:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:05:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:05:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:05:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:05:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:05:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:05:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:05:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:05:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:05:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:05:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:05:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:05:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:05:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:05:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:05:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:05:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:05:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:05:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:05:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:05:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:05:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:05:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:05:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:05:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:05:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:05:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:05:11 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:05:11 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:05:11 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:05:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:05:11 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:05:11 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:05:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:05:12 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:05:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:05:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:05:12 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:05:12 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:05:12 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:05:12 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:05:12 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:05:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:05:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:05:12 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=188 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:05:12 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=188 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:05:12 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=188 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:05:12 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=188 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:05:12 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=188 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:05:12 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=188 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:05:12 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=189 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:05:12 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=189 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:05:12 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=189 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:05:12 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=189 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:05:12 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=189 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:05:12 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=189 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:05:12 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=189 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:05:12 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=189 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:05:17 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:05:17 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:05:17 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:05:17 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:05:17 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:05:17 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:05:17 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:05:17 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:05:17 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:05:17 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:05:17 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:05:17 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:05:17 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:05:17 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:05:17 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:05:17 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:05:17 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:05:17 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:05:17 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:05:17 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:05:17 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:05:17 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:05:17 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:05:17 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:05:17 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:05:17 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:05:17 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:05:17 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:05:17 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:05:17 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:05:17 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:05:17 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:05:17 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:05:17 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:05:17 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:05:17 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:05:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:05:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:05:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:05:17 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:05:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:05:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:05:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:05:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:05:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:05:17 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:05:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:05:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:05:17 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:05:17 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:05:17 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:05:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:05:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:05:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:05:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:05:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:05:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:05:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:05:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:05:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:05:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:05:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:05:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:05:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:05:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:05:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:05:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:05:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:05:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:05:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:05:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:05:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:05:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:05:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:05:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:05:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:05:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:05:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:05:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:05:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:05:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:05:17 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:05:17 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:05:17 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:05:17 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:05:17 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:05:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:05:18 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:05:18 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:05:18 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:05:18 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:05:18 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:05:18 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 05:05:19 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 05:05:19 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:05:19 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:05:19 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:05:19 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:05:19 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 05:05:19 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 05:05:20 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:05:20 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:05:20 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:05:20 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:05:20 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 05:05:20 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 05:05:21 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:05:21 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:05:21 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:05:21 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:05:21 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 05:05:21 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 05:05:22 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:05:22 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:05:22 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:05:22 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:05:22 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 05:05:22 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 05:05:23 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 05:05:23 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 05:05:24 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 05:05:24 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 05:05:25 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 05:05:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:05:25 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:05:25 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:05:25 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:05:25 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:05:25 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:05:25 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:05:25 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:05:25 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:05:25 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:05:25 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:05:25 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:05:25 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1825 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:05:25 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1825 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:05:25 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1825 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:05:25 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1825 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:05:25 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1825 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:05:25 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1825 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:05:25 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1825 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:05:30 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:05:30 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:05:30 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:05:30 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:05:30 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:05:30 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:05:30 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:05:30 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:05:30 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:05:30 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:05:30 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:05:30 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:05:30 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:05:30 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:05:30 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:05:30 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:05:30 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:05:30 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:05:30 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:05:30 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:05:30 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:05:30 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:05:30 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:05:30 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:05:30 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:05:30 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:05:30 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:05:30 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:05:30 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:05:30 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:05:30 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:05:30 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:05:30 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:05:30 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:05:30 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:05:30 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:05:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:05:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:05:30 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:05:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:05:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:05:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:05:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:05:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:05:30 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:05:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:05:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:05:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:05:30 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:05:30 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:05:30 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:05:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:05:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:05:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:05:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:05:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:05:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:05:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:05:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:05:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:05:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:05:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:05:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:05:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:05:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:05:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:05:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:05:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:05:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:05:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:05:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:05:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:05:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:05:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:05:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:05:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:05:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:05:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:05:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:05:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:05:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:05:30 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:05:31 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:05:31 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:05:31 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:05:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:05:31 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:05:31 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:05:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:05:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:05:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:05:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:05:32 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 05:05:32 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 05:05:32 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:05:32 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:05:32 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:05:32 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:05:33 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 05:05:33 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 05:05:33 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:05:33 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:05:33 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:05:33 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:05:34 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 05:05:34 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 05:05:34 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:05:34 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:05:34 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:05:34 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:05:35 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 05:05:35 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 05:05:35 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:05:35 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:05:35 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:05:35 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:05:35 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 05:05:36 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 05:05:36 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 05:05:37 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 05:05:37 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 05:05:38 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 05:05:38 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 05:05:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:05:39 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:05:39 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:05:39 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:05:39 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:05:39 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:05:39 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:05:39 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:05:39 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:05:39 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:05:39 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:05:39 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:05:39 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1824 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:05:39 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1824 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:05:39 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1824 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:05:39 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1824 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:05:39 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1824 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:05:39 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1824 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:05:39 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1824 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:05:44 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:05:44 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:05:44 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:05:44 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:05:44 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:05:44 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:05:44 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:05:44 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:05:44 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:05:44 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:05:44 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:05:44 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:05:44 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:05:44 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:05:44 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:05:44 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:05:44 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:05:44 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:05:44 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:05:44 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:05:44 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:05:44 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:05:44 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:05:44 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:05:44 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:05:44 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:05:44 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:05:44 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:05:44 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:05:44 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:05:44 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:05:44 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:05:44 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:05:44 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:05:44 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:05:44 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:05:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:05:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:05:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:05:44 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:05:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:05:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:05:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:05:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:05:44 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:05:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:05:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:05:44 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:05:44 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:05:44 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:05:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:05:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:05:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:05:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:05:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:05:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:05:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:05:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:05:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:05:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:05:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:05:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:05:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:05:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:05:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:05:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:05:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:05:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:05:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:05:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:05:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:05:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:05:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:05:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:05:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:05:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:05:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:05:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:05:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:05:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:05:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:05:44 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:05:44 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:05:44 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:05:44 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:05:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:05:44 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:05:45 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:05:45 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:05:45 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:05:45 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:05:45 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:05:45 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 05:05:46 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 05:05:46 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:05:46 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:05:46 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:05:46 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:05:46 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 05:05:47 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 05:05:47 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:05:47 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:05:47 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:05:47 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:05:47 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 05:05:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:05:47 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:05:47 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:05:47 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:05:47 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:05:47 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:05:47 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:05:47 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:05:47 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:05:47 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:05:47 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:05:47 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:05:47 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=758 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:05:47 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=758 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:05:47 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=758 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:05:47 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=758 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:05:47 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=758 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:05:47 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=758 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:05:47 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=758 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:05:52 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:05:52 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:05:52 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:05:52 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:05:52 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:05:52 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:05:52 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:05:52 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:05:52 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:05:52 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:05:52 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:05:52 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:05:52 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:05:52 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:05:52 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:05:52 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:05:52 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:05:52 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:05:52 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:05:52 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:05:52 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:05:52 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:05:52 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:05:52 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:05:52 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:05:52 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:05:52 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:05:52 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:05:52 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:05:52 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:05:52 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:05:52 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:05:52 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:05:52 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:05:52 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:05:52 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:05:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:05:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:05:52 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:05:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:05:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:05:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:05:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:05:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:05:52 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:05:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:05:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:05:52 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:05:52 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:05:52 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:05:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:05:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:05:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:05:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:05:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:05:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:05:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:05:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:05:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:05:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:05:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:05:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:05:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:05:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:05:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:05:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:05:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:05:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:05:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:05:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:05:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:05:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:05:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:05:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:05:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:05:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:05:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:05:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:05:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:05:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:05:52 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:05:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:05:53 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:05:53 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:05:53 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:05:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:05:53 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:05:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:05:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:05:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:05:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:05:53 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:05:53 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:05:53 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:05:53 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:05:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:05:53 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:05:53 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:05:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:05:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:05:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:05:53 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:05:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:05:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:05:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:05:53 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:05:53 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:05:53 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:05:53 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:05:53 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:05:53 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:05:53 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:05:53 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:05:53 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:05:53 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:05:53 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:05:53 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=209 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:05:53 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=209 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:05:53 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=209 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:05:53 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=209 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:05:53 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=209 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:05:53 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=209 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:05:58 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:05:58 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:05:58 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:05:58 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:05:58 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:05:58 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:05:58 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:05:58 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:05:58 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:05:58 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:05:58 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:05:58 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:05:58 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:05:58 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:05:58 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:05:58 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:05:58 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:05:58 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:05:58 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:05:58 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:05:58 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:05:58 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:05:58 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:05:58 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:05:58 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:05:58 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:05:58 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:05:58 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:05:58 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:05:58 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:05:58 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:05:58 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:05:58 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:05:58 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:05:58 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:05:58 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:05:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:05:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:05:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:05:58 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:05:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:05:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:05:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:05:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:05:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:05:58 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:05:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:05:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:05:58 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:05:58 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:05:58 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:05:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:05:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:05:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:05:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:05:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:05:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:05:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:05:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:05:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:05:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:05:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:05:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:05:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:05:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:05:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:05:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:05:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:05:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:05:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:05:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:05:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:05:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:05:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:05:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:05:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:05:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:05:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:05:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:05:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:05:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:05:58 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:05:59 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:05:59 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:05:59 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:05:59 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:05:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:05:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:05:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:05:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:05:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:05:59 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:05:59 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:05:59 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:05:59 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:05:59 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:05:59 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:05:59 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:05:59 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=115 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:05:59 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=115 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:05:59 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=115 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:05:59 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=115 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:05:59 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=115 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:05:59 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=115 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:06:04 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:06:04 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:06:04 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:06:04 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:06:04 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:06:04 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:06:04 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:06:04 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:06:04 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:06:04 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:06:04 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:06:04 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:06:04 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:06:04 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:06:04 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:06:04 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:06:04 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:06:04 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:06:04 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:06:04 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:06:04 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:06:04 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:06:04 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:06:04 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:06:04 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:06:04 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:06:04 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:06:04 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:06:04 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:06:04 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:06:04 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:06:04 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:06:04 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:06:04 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:06:04 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:06:04 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:06:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:06:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:06:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:06:04 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:06:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:06:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:06:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:06:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:06:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:06:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:06:04 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:06:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:06:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:06:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:06:04 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:06:04 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:06:04 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:06:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:06:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:06:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:06:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:06:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:06:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:06:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:06:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:06:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:06:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:06:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:06:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:06:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:06:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:06:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:06:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:06:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:06:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:06:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:06:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:06:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:06:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:06:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:06:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:06:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:06:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:06:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:06:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:06:04 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:06:04 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:06:05 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:06:05 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:06:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:06:05 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:06:05 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:06:05 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:06:05 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:06:05 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:06:05 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:06:05 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 05:06:06 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 05:06:06 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:06:06 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:06:06 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:06:06 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:06:06 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 05:06:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:06:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:06:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:06:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:06:07 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:06:07 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:06:07 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:06:07 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:06:07 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=539 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:06:07 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:06:07 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:06:07 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:06:07 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=539 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:06:12 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:06:12 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:06:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:06:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:06:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:06:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:06:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:06:12 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:06:12 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:06:12 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:06:12 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:06:12 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:06:12 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:06:12 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:06:12 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:06:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:06:12 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:06:12 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:06:12 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:06:12 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:06:12 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:06:12 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:06:12 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:06:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:06:12 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:06:12 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:06:12 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:06:12 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:06:12 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:06:12 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:06:12 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:06:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:06:12 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:06:12 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:06:12 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:06:12 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:06:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:06:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:06:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:06:12 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:06:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:06:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:06:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:06:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:06:12 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:06:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:06:12 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:06:12 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:06:12 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:06:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:06:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:06:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:06:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:06:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:06:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:06:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:06:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:06:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:06:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:06:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:06:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:06:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:06:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:06:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:06:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:06:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:06:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:06:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:06:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:06:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:06:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:06:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:06:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:06:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:06:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:06:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:06:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:06:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:06:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:06:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:06:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:06:12 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:06:12 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:06:12 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:06:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:06:12 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:06:12 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:06:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:06:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:06:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:06:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:06:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:06:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:06:12 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:06:12 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:06:13 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:06:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:06:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:06:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:06:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:06:13 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 05:06:14 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 05:06:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:06:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:06:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:06:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:06:14 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 05:06:14 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 05:06:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:06:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:06:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:06:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:06:15 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 05:06:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:06:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:06:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:06:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:06:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:06:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:06:15 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:06:15 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:06:15 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:06:15 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:06:15 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:06:15 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:06:15 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:06:20 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:06:20 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:06:20 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:06:20 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:06:20 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:06:20 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:06:20 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:06:20 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:06:20 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:06:20 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:06:20 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:06:20 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:06:20 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:06:20 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:06:20 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:06:20 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:06:20 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:06:20 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:06:20 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:06:20 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:06:20 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:06:20 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:06:20 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:06:20 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:06:20 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:06:20 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:06:20 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:06:20 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:06:20 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:06:20 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:06:20 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:06:20 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:06:20 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:06:20 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:06:20 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:06:20 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:06:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:06:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:06:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:06:20 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:06:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:06:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:06:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:06:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:06:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:06:20 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:06:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:06:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:06:20 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:06:20 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:06:20 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:06:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:06:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:06:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:06:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:06:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:06:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:06:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:06:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:06:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:06:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:06:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:06:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:06:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:06:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:06:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:06:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:06:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:06:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:06:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:06:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:06:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:06:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:06:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:06:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:06:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:06:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:06:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:06:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:06:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:06:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:06:20 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:06:21 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:06:21 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:06:21 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:06:21 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:06:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:06:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:06:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:06:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:06:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:06:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:06:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:06:21 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:06:21 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:06:21 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:06:21 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:06:21 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:06:21 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:06:21 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:06:21 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 05:06:22 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 05:06:22 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:06:22 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:06:22 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:06:22 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:06:22 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 05:06:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:06:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:06:23 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:06:23 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:06:23 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:06:23 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:06:23 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:06:23 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:06:23 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:06:23 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:06:23 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:06:23 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:06:23 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:06:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=567 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:06:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=567 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:06:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=567 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:06:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=567 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:06:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=567 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:06:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=567 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:06:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=568 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:06:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=568 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:06:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=568 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:06:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=568 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:06:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=568 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:06:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=568 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:06:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=568 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:06:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=568 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:06:28 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:06:28 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:06:28 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:06:28 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:06:28 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:06:28 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:06:28 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:06:28 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:06:28 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:06:28 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:06:28 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:06:28 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:06:28 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:06:28 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:06:28 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:06:28 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:06:28 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:06:28 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:06:28 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:06:28 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:06:28 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:06:28 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:06:28 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:06:28 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:06:28 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:06:28 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:06:28 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:06:28 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:06:28 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:06:28 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:06:28 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:06:28 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:06:28 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:06:28 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:06:28 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:06:28 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:06:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:06:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:06:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:06:28 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:06:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:06:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:06:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:06:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:06:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:06:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:06:28 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:06:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:06:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:06:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:06:28 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:06:28 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:06:28 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:06:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:06:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:06:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:06:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:06:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:06:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:06:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:06:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:06:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:06:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:06:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:06:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:06:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:06:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:06:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:06:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:06:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:06:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:06:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:06:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:06:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:06:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:06:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:06:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:06:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:06:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:06:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:06:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:06:28 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:06:28 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:06:28 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:06:28 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:06:28 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:06:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:06:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:06:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:06:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:06:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:06:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:06:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:06:28 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:06:28 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:06:29 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:06:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:06:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:06:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:06:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:06:29 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 05:06:30 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 05:06:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:06:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:06:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:06:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:06:30 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 05:06:31 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 05:06:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:06:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:06:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:06:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:06:31 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 05:06:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:06:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:06:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:06:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:06:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:06:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:06:31 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:06:31 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:06:31 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:06:31 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:06:31 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:06:31 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:06:31 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=720 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:06:31 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:06:31 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=720 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:06:31 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=720 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:06:31 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=720 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:06:31 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=720 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:06:31 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=720 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:06:31 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=721 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:06:31 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=721 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:06:31 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=721 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:06:31 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=721 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:06:31 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=721 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:06:31 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=721 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:06:31 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=721 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:06:31 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=721 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:06:36 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:06:36 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:06:36 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:06:36 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:06:36 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:06:36 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:06:36 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:06:36 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:06:36 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:06:36 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:06:36 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:06:36 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:06:36 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:06:36 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:06:36 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:06:36 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:06:36 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:06:36 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:06:36 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:06:36 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:06:36 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:06:36 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:06:36 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:06:36 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:06:36 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:06:36 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:06:36 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:06:36 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:06:36 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:06:36 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:06:36 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:06:36 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:06:36 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:06:36 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:06:36 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:06:36 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:06:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:06:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:06:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:06:36 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:06:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:06:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:06:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:06:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:06:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:06:36 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:06:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:06:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:06:36 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:06:36 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:06:36 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:06:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:06:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:06:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:06:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:06:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:06:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:06:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:06:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:06:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:06:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:06:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:06:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:06:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:06:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:06:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:06:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:06:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:06:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:06:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:06:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:06:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:06:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:06:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:06:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:06:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:06:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:06:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:06:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:06:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:06:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:06:36 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:06:37 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:06:37 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:06:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:06:37 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:06:37 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:06:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:06:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:06:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:06:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:06:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:06:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:06:37 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:06:37 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:06:37 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:06:37 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:06:37 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:06:37 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:06:37 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:06:38 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 05:06:38 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 05:06:38 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:06:38 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:06:38 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:06:38 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:06:39 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 05:06:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:06:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:06:39 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:06:39 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:06:39 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:06:39 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:06:39 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:06:39 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:06:39 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:06:39 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:06:39 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:06:39 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=567 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:06:39 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:06:39 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:06:39 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=567 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:06:39 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=567 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:06:39 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=568 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:06:39 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=568 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:06:39 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=568 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:06:39 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=568 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:06:39 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=568 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:06:39 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=568 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:06:39 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=568 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:06:39 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=568 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:06:44 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:06:44 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:06:44 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:06:44 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:06:44 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:06:44 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:06:44 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:06:44 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:06:44 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:06:44 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:06:44 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:06:44 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:06:44 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:06:44 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:06:44 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:06:44 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:06:44 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:06:44 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:06:44 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:06:44 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:06:44 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:06:44 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:06:44 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:06:44 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:06:44 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:06:44 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:06:44 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:06:44 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:06:44 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:06:44 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:06:44 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:06:44 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:06:44 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:06:44 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:06:44 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:06:44 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:06:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:06:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:06:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:06:44 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:06:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:06:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:06:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:06:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:06:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:06:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:06:44 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:06:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:06:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:06:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:06:44 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:06:44 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:06:44 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:06:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:06:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:06:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:06:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:06:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:06:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:06:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:06:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:06:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:06:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:06:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:06:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:06:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:06:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:06:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:06:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:06:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:06:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:06:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:06:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:06:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:06:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:06:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:06:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:06:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:06:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:06:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:06:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:06:44 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:06:44 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:06:44 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:06:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:06:44 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:06:44 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:06:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:06:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:06:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:06:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:06:44 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:06:44 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:06:44 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:06:44 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:06:45 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:06:45 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:06:45 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:06:45 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:06:45 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:06:45 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 05:06:46 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 05:06:46 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:06:46 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:06:46 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:06:46 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:06:46 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 05:06:47 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 05:06:47 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:06:47 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:06:47 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:06:47 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:06:47 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 05:06:48 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 05:06:48 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:06:48 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:06:48 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:06:48 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:06:48 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 05:06:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:06:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:06:48 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:06:48 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:06:48 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:06:48 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:06:48 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:06:48 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:06:48 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:06:48 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:06:48 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:06:48 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:06:48 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:06:48 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=924 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:06:48 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=924 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:06:48 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=924 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:06:48 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=924 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:06:48 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=924 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:06:48 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=924 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:06:48 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=925 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:06:48 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=925 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:06:48 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=925 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:06:48 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=925 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:06:48 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=925 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:06:48 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=925 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:06:48 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=925 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:06:48 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=925 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:06:53 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:06:53 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:06:53 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:06:53 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:06:53 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:06:53 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:06:53 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:06:53 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:06:53 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:06:53 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:06:53 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:06:53 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:06:53 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:06:53 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:06:53 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:06:53 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:06:53 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:06:53 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:06:53 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:06:53 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:06:53 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:06:53 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:06:53 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:06:53 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:06:53 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:06:53 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:06:53 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:06:53 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:06:53 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:06:53 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:06:53 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:06:53 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:06:53 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:06:53 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:06:53 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:06:53 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:06:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:06:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:06:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:06:53 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:06:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:06:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:06:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:06:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:06:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:06:53 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:06:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:06:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:06:53 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:06:53 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:06:53 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:06:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:06:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:06:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:06:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:06:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:06:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:06:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:06:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:06:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:06:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:06:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:06:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:06:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:06:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:06:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:06:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:06:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:06:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:06:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:06:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:06:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:06:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:06:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:06:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:06:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:06:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:06:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:06:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:06:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:06:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:06:53 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:06:54 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:06:54 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:06:54 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:06:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:06:54 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:06:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:06:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:06:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:06:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:06:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:06:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:06:54 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:06:54 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:06:54 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:06:54 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:06:54 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:06:54 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:06:54 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:06:55 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 05:06:55 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 05:06:55 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:06:55 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:06:55 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:06:55 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:06:56 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 05:06:56 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 05:06:56 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:06:56 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:06:56 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:06:56 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:06:57 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 05:06:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:06:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:06:57 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:06:57 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:06:57 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:06:57 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:06:57 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:06:57 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:06:57 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:06:57 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:06:57 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:06:57 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:06:57 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:07:02 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:07:02 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:07:02 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:07:02 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:07:02 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:07:02 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:07:02 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:07:02 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:07:02 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:07:02 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:07:02 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:07:02 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:07:02 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:07:02 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:07:02 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:07:02 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:07:02 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:07:02 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:07:02 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:07:02 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:07:02 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:07:02 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:07:02 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:07:02 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:07:02 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:07:02 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:07:02 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:07:02 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:07:02 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:07:02 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:07:02 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:07:02 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:07:02 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:07:02 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:07:02 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:07:02 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:07:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:07:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:07:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:07:02 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:07:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:07:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:07:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:07:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:07:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:07:02 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:07:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:07:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:07:02 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:07:02 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:07:02 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:07:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:07:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:07:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:07:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:07:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:07:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:07:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:07:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:07:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:07:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:07:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:07:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:07:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:07:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:07:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:07:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:07:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:07:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:07:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:07:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:07:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:07:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:07:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:07:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:07:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:07:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:07:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:07:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:07:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:07:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:07:02 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:07:02 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:07:02 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:07:02 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:07:02 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:07:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:07:03 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:07:03 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:07:03 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:07:03 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:07:03 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:07:03 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 05:07:04 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 05:07:04 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:07:04 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:07:04 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:07:04 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:07:04 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 05:07:04 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:07:04 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:07:04 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:07:04 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:07:04 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:07:04 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:07:04 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:07:04 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:07:04 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:07:04 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:07:04 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:07:04 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=545 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:07:04 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=545 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:07:04 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=545 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:07:04 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=545 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:07:04 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=545 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:07:04 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=545 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:07:04 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=545 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:07:04 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=545 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:07:09 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:07:09 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:07:09 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:07:09 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:07:09 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:07:09 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:07:09 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:07:09 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:07:09 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:07:09 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:07:09 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:07:09 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:07:09 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:07:09 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:07:09 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:07:09 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:07:09 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:07:09 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:07:09 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:07:09 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:07:09 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:07:09 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:07:09 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:07:09 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:07:09 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:07:09 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:07:09 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:07:09 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:07:09 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:07:09 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:07:09 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:07:09 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:07:09 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:07:09 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:07:09 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:07:09 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:07:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:07:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:07:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:07:09 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:07:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:07:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:07:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:07:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:07:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:07:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:07:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:07:09 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:07:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:07:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:07:09 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:07:09 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:07:09 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:07:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:07:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:07:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:07:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:07:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:07:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:07:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:07:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:07:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:07:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:07:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:07:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:07:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:07:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:07:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:07:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:07:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:07:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:07:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:07:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:07:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:07:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:07:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:07:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:07:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:07:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:07:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:07:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:07:09 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:07:10 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:07:10 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:07:10 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:07:10 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:07:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:07:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:07:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:07:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:07:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:07:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:07:10 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:07:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:07:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:07:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:07:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:07:11 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 05:07:11 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 05:07:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:07:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:07:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:07:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:07:12 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 05:07:12 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 05:07:12 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:07:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:07:12 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:07:12 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:07:13 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 05:07:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:07:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:07:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:07:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:07:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:07:13 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:07:13 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:07:13 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:07:13 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:07:13 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:07:13 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:07:13 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:07:13 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=766 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:07:13 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=766 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:07:13 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=766 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:07:13 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=766 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:07:13 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=766 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:07:13 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=766 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:07:18 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:07:18 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:07:18 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:07:18 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:07:18 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:07:18 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:07:18 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:07:18 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:07:18 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:07:18 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:07:18 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:07:18 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:07:18 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:07:18 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:07:18 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:07:18 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:07:18 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:07:18 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:07:18 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:07:18 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:07:18 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:07:18 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:07:18 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:07:18 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:07:18 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:07:18 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:07:18 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:07:18 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:07:18 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:07:18 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:07:18 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:07:18 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:07:18 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:07:18 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:07:18 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:07:18 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:07:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:07:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:07:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:07:18 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:07:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:07:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:07:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:07:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:07:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:07:18 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:07:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:07:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:07:18 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:07:18 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:07:18 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:07:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:07:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:07:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:07:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:07:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:07:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:07:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:07:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:07:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:07:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:07:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:07:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:07:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:07:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:07:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:07:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:07:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:07:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:07:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:07:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:07:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:07:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:07:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:07:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:07:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:07:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:07:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:07:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:07:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:07:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:07:18 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:07:18 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:07:19 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:07:19 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:07:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:07:19 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:07:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:07:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:07:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:07:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:07:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:07:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:07:19 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:07:19 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:07:19 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:07:19 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:07:19 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:07:19 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:07:19 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:07:19 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:07:19 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:07:19 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:07:19 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=125 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:07:19 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:07:19 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=125 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:07:19 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=125 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:07:19 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=125 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:07:19 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=125 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:07:19 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=125 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:07:19 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=125 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:07:24 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:07:24 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:07:24 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:07:24 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:07:24 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:07:24 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:07:24 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:07:24 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:07:24 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:07:24 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:07:24 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:07:24 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:07:24 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:07:24 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:07:24 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:07:24 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:07:24 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:07:24 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:07:24 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:07:24 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:07:24 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:07:24 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:07:24 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:07:24 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:07:24 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:07:24 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:07:24 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:07:24 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:07:24 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:07:24 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:07:24 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:07:24 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:07:24 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:07:24 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:07:24 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:07:24 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:07:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:07:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:07:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:07:24 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:07:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:07:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:07:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:07:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:07:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:07:24 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:07:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:07:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:07:24 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:07:24 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:07:24 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:07:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:07:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:07:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:07:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:07:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:07:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:07:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:07:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:07:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:07:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:07:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:07:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:07:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:07:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:07:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:07:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:07:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:07:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:07:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:07:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:07:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:07:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:07:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:07:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:07:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:07:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:07:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:07:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:07:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:07:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:07:24 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:07:24 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:07:24 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:07:24 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:07:24 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:07:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:07:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:07:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:07:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:07:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:07:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:07:25 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:07:25 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:07:25 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:07:25 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:07:25 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:07:25 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 05:07:26 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 05:07:26 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:07:26 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:07:26 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:07:26 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:07:26 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 05:07:27 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 05:07:27 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:07:27 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:07:27 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:07:27 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:07:27 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 05:07:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:07:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:07:27 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:07:27 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:07:27 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:07:27 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:07:27 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:07:27 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:07:27 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:07:27 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:07:27 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:07:27 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=770 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:07:27 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:07:27 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:07:27 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=770 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:07:27 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=770 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:07:27 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=770 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:07:27 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=770 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:07:32 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:07:32 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:07:32 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:07:32 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:07:32 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:07:32 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:07:32 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:07:32 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:07:32 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:07:32 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:07:32 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:07:32 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:07:32 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:07:32 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:07:32 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:07:32 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:07:32 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:07:32 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:07:32 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:07:32 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:07:32 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:07:32 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:07:32 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:07:32 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:07:32 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:07:32 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:07:32 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:07:32 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:07:32 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:07:32 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:07:32 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:07:32 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:07:32 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:07:32 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:07:32 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:07:32 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:07:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:07:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:07:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:07:32 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:07:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:07:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:07:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:07:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:07:32 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:07:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:07:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:07:32 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:07:32 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:07:32 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:07:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:07:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:07:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:07:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:07:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:07:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:07:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:07:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:07:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:07:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:07:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:07:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:07:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:07:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:07:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:07:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:07:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:07:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:07:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:07:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:07:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:07:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:07:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:07:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:07:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:07:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:07:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:07:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:07:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:07:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:07:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:07:32 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:07:33 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:07:33 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:07:33 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:07:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:07:33 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:07:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:07:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:07:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:07:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:07:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:07:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:07:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:07:33 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:07:33 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:07:33 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:07:33 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:07:33 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:07:33 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:07:33 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:07:33 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:07:33 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:07:33 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:07:33 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:07:33 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=128 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:07:33 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=128 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:07:33 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=128 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:07:33 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=128 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:07:33 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=128 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:07:33 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=128 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:07:33 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=129 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:07:33 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=129 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:07:33 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=129 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:07:33 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=129 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:07:33 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=129 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:07:33 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=129 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:07:33 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=129 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:07:33 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=129 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:07:38 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:07:38 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:07:38 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:07:38 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:07:38 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:07:38 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:07:38 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:07:38 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:07:38 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:07:38 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:07:38 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:07:38 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:07:38 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:07:38 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:07:38 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:07:38 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:07:38 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:07:38 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:07:38 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:07:38 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:07:38 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:07:38 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:07:38 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:07:38 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:07:38 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:07:38 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:07:38 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:07:38 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:07:38 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:07:38 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:07:38 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:07:38 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:07:38 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:07:38 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:07:38 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:07:38 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:07:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:07:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:07:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:07:38 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:07:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:07:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:07:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:07:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:07:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:07:38 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:07:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:07:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:07:38 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:07:38 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:07:38 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:07:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:07:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:07:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:07:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:07:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:07:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:07:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:07:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:07:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:07:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:07:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:07:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:07:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:07:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:07:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:07:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:07:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:07:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:07:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:07:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:07:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:07:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:07:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:07:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:07:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:07:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:07:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:07:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:07:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:07:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:07:38 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:07:38 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:07:38 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:07:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:07:38 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:07:38 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:07:38 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:07:38 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:07:38 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:07:38 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:07:38 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:07:38 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:07:38 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:07:38 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:07:38 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:07:38 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:07:38 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:07:38 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=117 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:07:38 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=117 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:07:38 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=117 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:07:38 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=117 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:07:38 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=117 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:07:38 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=117 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:07:38 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=117 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:07:38 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=118 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:07:38 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=118 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:07:38 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=118 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:07:38 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=118 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:07:38 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=118 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:07:38 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=118 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:07:38 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=118 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:07:38 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=118 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:07:43 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:07:43 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:07:43 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:07:43 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:07:43 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:07:43 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:07:43 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:07:43 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:07:43 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:07:43 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:07:43 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:07:43 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:07:43 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:07:43 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:07:43 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:07:43 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:07:43 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:07:43 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:07:43 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:07:43 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:07:43 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:07:43 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:07:43 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:07:43 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:07:43 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:07:43 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:07:43 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:07:43 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:07:43 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:07:43 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:07:43 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:07:43 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:07:43 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:07:43 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:07:43 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:07:43 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:07:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:07:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:07:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:07:43 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:07:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:07:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:07:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:07:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:07:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:07:43 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:07:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:07:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:07:43 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:07:43 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:07:43 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:07:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:07:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:07:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:07:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:07:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:07:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:07:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:07:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:07:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:07:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:07:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:07:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:07:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:07:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:07:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:07:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:07:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:07:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:07:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:07:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:07:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:07:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:07:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:07:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:07:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:07:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:07:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:07:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:07:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:07:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:07:43 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:07:44 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:07:44 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:07:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:07:44 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:07:44 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:07:44 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:07:44 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:07:44 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:07:44 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:07:44 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:07:44 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:07:44 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:07:44 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:07:44 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:07:44 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:07:44 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:07:44 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=112 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:07:44 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=112 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:07:44 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=112 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:07:44 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=112 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:07:44 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=112 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:07:44 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=112 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:07:44 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=113 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:07:44 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=113 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:07:44 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=113 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:07:44 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=113 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:07:44 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=113 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:07:44 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=113 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:07:44 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=113 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:07:44 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=113 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:07:49 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:07:49 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:07:49 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:07:49 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:07:49 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:07:49 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:07:49 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:07:49 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:07:49 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:07:49 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:07:49 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:07:49 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:07:49 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:07:49 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:07:49 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:07:49 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:07:49 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:07:49 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:07:49 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:07:49 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:07:49 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:07:49 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:07:49 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:07:49 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:07:49 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:07:49 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:07:49 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:07:49 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:07:49 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:07:49 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:07:49 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:07:49 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:07:49 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:07:49 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:07:49 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:07:49 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:07:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:07:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:07:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:07:49 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:07:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:07:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:07:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:07:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:07:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:07:49 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:07:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:07:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:07:49 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:07:49 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:07:49 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:07:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:07:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:07:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:07:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:07:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:07:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:07:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:07:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:07:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:07:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:07:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:07:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:07:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:07:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:07:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:07:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:07:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:07:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:07:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:07:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:07:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:07:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:07:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:07:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:07:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:07:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:07:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:07:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:07:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:07:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:07:49 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:07:50 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:07:50 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:07:50 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:07:50 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:07:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:07:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:07:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:07:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:07:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:07:50 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:07:50 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:07:50 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:07:50 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:07:50 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:07:50 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:07:50 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:07:50 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=111 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:07:50 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=111 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:07:50 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=111 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:07:50 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=111 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:07:50 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=111 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:07:50 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=111 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:07:50 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=112 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:07:50 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=112 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:07:50 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=112 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:07:50 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=112 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:07:50 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=112 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:07:50 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=112 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:07:50 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=112 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:07:50 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=112 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:07:55 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:07:55 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:07:55 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:07:55 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:07:55 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:07:55 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:07:55 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:07:55 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:07:55 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:07:55 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:07:55 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:07:55 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:07:55 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:07:55 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:07:55 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:07:55 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:07:55 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:07:55 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:07:55 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:07:55 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:07:55 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:07:55 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:07:55 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:07:55 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:07:55 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:07:55 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:07:55 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:07:55 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:07:55 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:07:55 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:07:55 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:07:55 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:07:55 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:07:55 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:07:55 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:07:55 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:07:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:07:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:07:55 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:07:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:07:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:07:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:07:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:07:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:07:55 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:07:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:07:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:07:55 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:07:55 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:07:55 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:07:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:07:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:07:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:07:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:07:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:07:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:07:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:07:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:07:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:07:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:07:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:07:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:07:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:07:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:07:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:07:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:07:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:07:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:07:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:07:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:07:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:07:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:07:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:07:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:07:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:07:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:07:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:07:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:07:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:07:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:07:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:07:55 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:07:55 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:07:55 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:07:55 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:07:55 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:07:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:07:55 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:07:55 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:07:55 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:07:55 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:07:55 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:07:55 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:07:55 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:07:55 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:07:55 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:07:55 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:07:55 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:08:00 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:08:00 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:08:00 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:08:00 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:08:00 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:08:00 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:08:00 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:08:00 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:08:00 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:08:00 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:08:00 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:08:00 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:08:00 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:08:00 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:08:00 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:08:00 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:08:00 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:08:00 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:08:00 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:08:00 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:08:00 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:08:00 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:08:00 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:08:00 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:08:00 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:08:00 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:08:00 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:08:00 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:08:00 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:08:00 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:08:00 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:08:00 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:08:00 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:08:00 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:08:00 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:08:00 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:08:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:08:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:08:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:08:00 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:08:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:08:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:08:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:08:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:08:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:08:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:08:00 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:08:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:08:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:08:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:08:00 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:08:00 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:08:00 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:08:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:08:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:08:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:08:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:08:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:08:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:08:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:08:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:08:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:08:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:08:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:08:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:08:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:08:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:08:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:08:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:08:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:08:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:08:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:08:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:08:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:08:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:08:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:08:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:08:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:08:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:08:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:08:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:08:00 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:08:01 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:08:01 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:08:01 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:08:01 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:08:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:08:01 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:08:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:08:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:08:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:08:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:08:02 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 05:08:02 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 05:08:02 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:08:02 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:08:02 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:08:02 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:08:03 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 05:08:03 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 05:08:03 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:08:03 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:08:03 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:08:03 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:08:04 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 05:08:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:08:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:08:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:08:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:08:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:08:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:08:04 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:08:04 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:08:04 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 05:08:04 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:08:04 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:08:04 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:08:04 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:08:05 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 05:08:05 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 05:08:05 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:08:05 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:08:05 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:08:05 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:08:05 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 05:08:06 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 05:08:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:08:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:08:06 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:08:06 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:08:06 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:08:06 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:08:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:08:06 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:08:06 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:08:06 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:08:06 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:08:06 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:08:06 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:08:06 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:08:06 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1254 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:08:06 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1254 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:08:06 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1254 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:08:06 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1254 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:08:06 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1254 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:08:06 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1254 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:08:06 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1255 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:08:06 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1255 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:08:06 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1255 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:08:06 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1255 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:08:06 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1255 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:08:06 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1255 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:08:06 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1255 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:08:06 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1255 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:08:11 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:08:11 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:08:11 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:08:11 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:08:11 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:08:11 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:08:11 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:08:11 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:08:11 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:08:11 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:08:11 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:08:11 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:08:11 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:08:11 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:08:11 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:08:11 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:08:11 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:08:11 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:08:11 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:08:11 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:08:11 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:08:11 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:08:11 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:08:11 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:08:11 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:08:11 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:08:11 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:08:11 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:08:11 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:08:11 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:08:11 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:08:11 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:08:11 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:08:11 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:08:11 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:08:11 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:08:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:08:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:08:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:08:11 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:08:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:08:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:08:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:08:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:08:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:08:11 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:08:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:08:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:08:11 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:08:11 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:08:11 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:08:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:08:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:08:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:08:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:08:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:08:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:08:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:08:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:08:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:08:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:08:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:08:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:08:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:08:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:08:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:08:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:08:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:08:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:08:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:08:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:08:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:08:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:08:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:08:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:08:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:08:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:08:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:08:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:08:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:08:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:08:11 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:08:12 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:08:12 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:08:12 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:08:12 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:08:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:08:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:08:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:08:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:08:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:08:12 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:08:12 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:08:12 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:08:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:08:12 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:08:12 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:08:12 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:08:12 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=123 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:08:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:08:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:08:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:08:12 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=123 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:08:12 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=123 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:08:12 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=123 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:08:12 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=123 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:08:12 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=123 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:08:12 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=124 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:08:12 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=124 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:08:12 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=124 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:08:12 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=124 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:08:12 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=124 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:08:12 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=124 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:08:12 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=124 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:08:12 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=124 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:08:17 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:08:17 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:08:17 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:08:17 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:08:17 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:08:17 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:08:17 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:08:17 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:08:17 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:08:17 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:08:17 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:08:17 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:08:17 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:08:17 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:08:17 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:08:17 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:08:17 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:08:17 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:08:17 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:08:17 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:08:17 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:08:17 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:08:17 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:08:17 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:08:17 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:08:17 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:08:17 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:08:17 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:08:17 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:08:17 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:08:17 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:08:17 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:08:17 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:08:17 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:08:17 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:08:17 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:08:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:08:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:08:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:08:17 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:08:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:08:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:08:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:08:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:08:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:08:17 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:08:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:08:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:08:17 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:08:17 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:08:17 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:08:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:08:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:08:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:08:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:08:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:08:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:08:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:08:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:08:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:08:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:08:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:08:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:08:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:08:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:08:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:08:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:08:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:08:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:08:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:08:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:08:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:08:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:08:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:08:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:08:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:08:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:08:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:08:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:08:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:08:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:08:17 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:08:17 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:08:17 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:08:17 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:08:17 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:08:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:08:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:08:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:08:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:08:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:08:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:08:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:08:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:08:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:08:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:08:17 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:08:17 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:08:17 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:08:17 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:08:17 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=126 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:08:17 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:08:17 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:08:17 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:08:17 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=126 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:08:17 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=126 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:08:17 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=126 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:08:17 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=126 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:08:17 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=127 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:08:17 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=127 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:08:17 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=127 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:08:17 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=127 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:08:17 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=127 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:08:17 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=127 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:08:17 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=127 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:08:17 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=127 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:08:22 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:08:22 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:08:22 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:08:22 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:08:22 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:08:22 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:08:22 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:08:22 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:08:22 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:08:22 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:08:22 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:08:22 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:08:22 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:08:22 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:08:22 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:08:22 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:08:22 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:08:22 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:08:22 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:08:22 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:08:22 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:08:22 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:08:22 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:08:22 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:08:22 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:08:22 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:08:22 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:08:22 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:08:22 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:08:22 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:08:22 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:08:22 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:08:22 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:08:22 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:08:22 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:08:22 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:08:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:08:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:08:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:08:22 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:08:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:08:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:08:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:08:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:08:22 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:08:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:08:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:08:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:08:22 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:08:22 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:08:22 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:08:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:08:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:08:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:08:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:08:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:08:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:08:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:08:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:08:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:08:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:08:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:08:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:08:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:08:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:08:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:08:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:08:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:08:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:08:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:08:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:08:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:08:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:08:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:08:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:08:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:08:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:08:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:08:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:08:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:08:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:08:22 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:08:23 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:08:23 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:08:23 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:08:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:08:23 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:08:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:08:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:08:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:08:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:08:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:08:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:08:23 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:08:23 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:08:23 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:08:23 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:08:23 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:08:23 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:08:23 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:08:23 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:08:23 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:08:23 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:08:23 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:08:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=123 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:08:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=123 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:08:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=123 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:08:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=123 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:08:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=123 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:08:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=123 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:08:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=123 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:08:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=124 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:08:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=124 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:08:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=124 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:08:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=124 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:08:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=124 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:08:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=124 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:08:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=124 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:08:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=124 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:08:28 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:08:28 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:08:28 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:08:28 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:08:28 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:08:28 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:08:28 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:08:28 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:08:28 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:08:28 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:08:28 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:08:28 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:08:28 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:08:28 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:08:28 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:08:28 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:08:28 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:08:28 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:08:28 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:08:28 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:08:28 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:08:28 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:08:28 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:08:28 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:08:28 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:08:28 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:08:28 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:08:28 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:08:28 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:08:28 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:08:28 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:08:28 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:08:28 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:08:28 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:08:28 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:08:28 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:08:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:08:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:08:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:08:28 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:08:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:08:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:08:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:08:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:08:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:08:28 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:08:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:08:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:08:28 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:08:28 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:08:28 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:08:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:08:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:08:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:08:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:08:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:08:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:08:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:08:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:08:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:08:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:08:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:08:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:08:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:08:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:08:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:08:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:08:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:08:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:08:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:08:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:08:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:08:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:08:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:08:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:08:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:08:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:08:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:08:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:08:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:08:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:08:28 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:08:28 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:08:28 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:08:29 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:08:29 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:08:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:08:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:08:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:08:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:08:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:08:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:08:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:08:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:08:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:08:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:08:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:08:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:08:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:08:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:08:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:08:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:08:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:08:29 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:08:29 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:08:29 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:08:29 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:08:29 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:08:29 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:08:29 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:08:29 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=132 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:08:29 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=132 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:08:29 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=132 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:08:29 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=132 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:08:29 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=132 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:08:29 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=132 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:08:34 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:08:34 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:08:34 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:08:34 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:08:34 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:08:34 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:08:34 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:08:34 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:08:34 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:08:34 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:08:34 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:08:34 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:08:34 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:08:34 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:08:34 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:08:34 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:08:34 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:08:34 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:08:34 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:08:34 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:08:34 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:08:34 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:08:34 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:08:34 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:08:34 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:08:34 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:08:34 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:08:34 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:08:34 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:08:34 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:08:34 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:08:34 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:08:34 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:08:34 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:08:34 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:08:34 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:08:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:08:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:08:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:08:34 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:08:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:08:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:08:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:08:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:08:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:08:34 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:08:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:08:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:08:34 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:08:34 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:08:34 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:08:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:08:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:08:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:08:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:08:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:08:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:08:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:08:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:08:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:08:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:08:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:08:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:08:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:08:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:08:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:08:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:08:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:08:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:08:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:08:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:08:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:08:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:08:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:08:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:08:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:08:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:08:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:08:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:08:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:08:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:08:34 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:08:34 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:08:34 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:08:34 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:08:34 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:08:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:08:34 [DEBUG] fake_trx.py:376 (BTS@172.18.127.20:5700) Recv FAKE_TRXC_DELAY cmd
2025-04-27 05:08:34 [INFO] fake_trx.py:379 (BTS@172.18.127.20:5700) Artificial TRXC delay set to 200
2025-04-27 05:08:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD FAKE_TRXC_DELAY
2025-04-27 05:08:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:08:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:08:35 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:08:35 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:08:35 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:08:35 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:08:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:08:35 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:08:35 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 05:08:36 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 05:08:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:08:36 [DEBUG] fake_trx.py:376 (BTS@172.18.127.20:5700) Recv FAKE_TRXC_DELAY cmd
2025-04-27 05:08:36 [INFO] fake_trx.py:379 (BTS@172.18.127.20:5700) Artificial TRXC delay set to 0
2025-04-27 05:08:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD FAKE_TRXC_DELAY
2025-04-27 05:08:36 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:08:36 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:08:36 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:08:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:08:36 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:08:36 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:08:36 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:08:36 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:08:36 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:08:36 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:08:36 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:08:36 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:08:36 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:08:36 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=464 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:08:36 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:08:36 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:08:36 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=464 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:08:36 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=464 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:08:36 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=464 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:08:36 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=464 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:08:36 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=464 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:08:41 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:08:41 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:08:41 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:08:41 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:08:41 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:08:41 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:08:41 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:08:41 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:08:41 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:08:41 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:08:41 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:08:41 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:08:41 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:08:41 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:08:41 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:08:41 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:08:41 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:08:41 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:08:41 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:08:41 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:08:41 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:08:41 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:08:41 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:08:41 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:08:41 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:08:41 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:08:41 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:08:41 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:08:41 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:08:41 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:08:41 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:08:41 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:08:41 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:08:41 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:08:41 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:08:41 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:08:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:08:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:08:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:08:41 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:08:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:08:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:08:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:08:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:08:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:08:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:08:41 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:08:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:08:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:08:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:08:41 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:08:41 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:08:41 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:08:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:08:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:08:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:08:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:08:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:08:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:08:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:08:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:08:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:08:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:08:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:08:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:08:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:08:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:08:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:08:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:08:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:08:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:08:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:08:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:08:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:08:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:08:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:08:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:08:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:08:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:08:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:08:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:08:41 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:08:41 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:08:41 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:08:41 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:08:41 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:08:41 [DEBUG] fake_trx.py:376 (BTS@172.18.127.20:5700) Recv FAKE_TRXC_DELAY cmd
2025-04-27 05:08:41 [INFO] fake_trx.py:379 (BTS@172.18.127.20:5700) Artificial TRXC delay set to 200
2025-04-27 05:08:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD FAKE_TRXC_DELAY
2025-04-27 05:08:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:08:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:08:42 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:08:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:08:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:08:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:08:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:08:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:08:42 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 05:08:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:08:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:08:43 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 05:08:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:08:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:08:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:08:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:08:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:08:43 [DEBUG] fake_trx.py:376 (BTS@172.18.127.20:5700) Recv FAKE_TRXC_DELAY cmd
2025-04-27 05:08:43 [INFO] fake_trx.py:379 (BTS@172.18.127.20:5700) Artificial TRXC delay set to 0
2025-04-27 05:08:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD FAKE_TRXC_DELAY
2025-04-27 05:08:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:08:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:08:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:08:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:08:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:08:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:08:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:08:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:08:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:08:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:08:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:08:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:08:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:08:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:08:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:08:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:08:43 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:08:43 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:08:43 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:08:43 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:08:43 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:08:43 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:08:43 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:08:43 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=502 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:08:43 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=502 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:08:43 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=502 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:08:43 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=502 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:08:43 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=502 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:08:48 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:08:48 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:08:48 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:08:48 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:08:48 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:08:48 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:08:48 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:08:48 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:08:48 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:08:48 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:08:48 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:08:48 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:08:48 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:08:48 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:08:48 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:08:48 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:08:48 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:08:48 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:08:48 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:08:48 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:08:48 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:08:48 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:08:48 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:08:48 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:08:48 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:08:48 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:08:48 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:08:48 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:08:48 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:08:48 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:08:48 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:08:48 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:08:48 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:08:48 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:08:48 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:08:48 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:08:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:08:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:08:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:08:48 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:08:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:08:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:08:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:08:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:08:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:08:48 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:08:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:08:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:08:48 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:08:48 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:08:48 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:08:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:08:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:08:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:08:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:08:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:08:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:08:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:08:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:08:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:08:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:08:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:08:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:08:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:08:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:08:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:08:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:08:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:08:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:08:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:08:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:08:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:08:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:08:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:08:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:08:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:08:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:08:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:08:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:08:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:08:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:08:48 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:08:49 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:08:49 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:08:49 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:08:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:08:49 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:08:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:08:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:08:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:08:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:08:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:08:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:08:49 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:08:49 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:08:49 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:08:49 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:08:49 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:08:49 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:08:49 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:08:49 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:08:49 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:08:49 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:08:49 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=117 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:08:49 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=117 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:08:49 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=117 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:08:49 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=117 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:08:49 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=117 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:08:49 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=117 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:08:49 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=117 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:08:49 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=118 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:08:49 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=118 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:08:49 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=118 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:08:49 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=118 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:08:49 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=118 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:08:49 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=118 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:08:49 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=118 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:08:49 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=118 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:08:54 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:08:54 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:08:54 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:08:54 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:08:54 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:08:54 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:08:54 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:08:54 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:08:54 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:08:54 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:08:54 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:08:54 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:08:54 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:08:54 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:08:54 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:08:54 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:08:54 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:08:54 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:08:54 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:08:54 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:08:54 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:08:54 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:08:54 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:08:54 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:08:54 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:08:54 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:08:54 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:08:54 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:08:54 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:08:54 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:08:54 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:08:54 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:08:54 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:08:54 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:08:54 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:08:54 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:08:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:08:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:08:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:08:54 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:08:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:08:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:08:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:08:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:08:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:08:54 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:08:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:08:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:08:54 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:08:54 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:08:54 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:08:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:08:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:08:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:08:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:08:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:08:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:08:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:08:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:08:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:08:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:08:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:08:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:08:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:08:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:08:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:08:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:08:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:08:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:08:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:08:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:08:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:08:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:08:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:08:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:08:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:08:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:08:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:08:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:08:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:08:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:08:54 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:08:54 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:08:54 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:08:54 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:08:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:08:54 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:08:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:08:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:08:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:08:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:08:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:08:54 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:08:54 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:08:54 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:08:54 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:08:54 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:08:54 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:08:54 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:08:54 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:08:54 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:08:54 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:08:54 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:08:59 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:08:59 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:08:59 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:08:59 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:08:59 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:08:59 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:08:59 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:08:59 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:08:59 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:08:59 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:08:59 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:08:59 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:08:59 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:08:59 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:08:59 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:08:59 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:08:59 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:08:59 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:08:59 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:08:59 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:08:59 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:08:59 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:08:59 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:08:59 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:08:59 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:08:59 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:08:59 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:08:59 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:08:59 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:08:59 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:08:59 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:08:59 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:08:59 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:08:59 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:08:59 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:08:59 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:08:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:08:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:08:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:08:59 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:08:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:08:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:08:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:08:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:08:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:08:59 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:08:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:08:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:08:59 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:08:59 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:08:59 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:08:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:08:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:08:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:08:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:08:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:08:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:08:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:08:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:08:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:08:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:08:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:08:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:08:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:08:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:08:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:08:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:08:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:08:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:08:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:08:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:08:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:08:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:08:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:08:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:08:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:08:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:08:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:08:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:08:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:08:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:08:59 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:09:00 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:09:00 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:09:00 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:09:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:09:00 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:09:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:09:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:09:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:09:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:09:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:09:00 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:09:00 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:09:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:09:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:09:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:09:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:09:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:09:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:09:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:09:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:09:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:09:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:09:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:09:00 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:09:00 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:09:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:09:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:09:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:09:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:00 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:09:00 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:09:00 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:09:00 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:09:00 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:09:01 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 05:09:01 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 05:09:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:09:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:09:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:09:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:09:02 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 05:09:02 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 05:09:02 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:09:02 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:09:02 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:09:02 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:09:03 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 05:09:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:09:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:09:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:09:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:09:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:09:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:09:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:09:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:09:03 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:09:03 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:09:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:09:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:09:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:09:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:09:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:09:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:09:03 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 05:09:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:09:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:09:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:09:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:09:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:09:03 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:09:03 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:09:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:09:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:09:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:09:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:03 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:09:03 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:09:03 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:09:03 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:09:04 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 05:09:04 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 05:09:04 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:09:04 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:09:04 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:09:04 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:09:05 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 05:09:05 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 05:09:06 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 05:09:06 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 05:09:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:09:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:09:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:09:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:09:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:09:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:09:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:09:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:09:06 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:09:06 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:09:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:09:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:09:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:09:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:07 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 05:09:07 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 05:09:08 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 05:09:08 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 05:09:09 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 05:09:09 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 05:09:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:09:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:09:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:09:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:09:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:09:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:09:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:09:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:09:09 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:09:09 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:09:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:09:09 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 05:09:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:09:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:09:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:09:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:09:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:09:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:09:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:09:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:09:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:10 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:09:10 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:09:10 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:09:10 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:09:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:09:10 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:09:10 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:09:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:10 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 05:09:10 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-27 05:09:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:09:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:09:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:09:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:09:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:09:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:09:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:09:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:09:11 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:09:11 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:09:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:09:11 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:09:11 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-27 05:09:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:09:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:09:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:09:11 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:09:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:09:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:09:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:09:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:09:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:09:11 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:09:11 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:09:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:09:11 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:09:11 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-27 05:09:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:11 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-27 05:09:11 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-27 05:09:12 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-27 05:09:12 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-27 05:09:13 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-27 05:09:13 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-27 05:09:14 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-27 05:09:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:09:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:09:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:09:14 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:09:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:09:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:09:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:09:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:14 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:09:14 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:09:14 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:09:14 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:09:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:09:14 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:09:14 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-27 05:09:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:09:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:09:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:09:14 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:09:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:09:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:09:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:09:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:14 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:09:14 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:09:14 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:09:14 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:09:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:09:14 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:09:14 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-27 05:09:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:14 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-27 05:09:15 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-27 05:09:15 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-27 05:09:16 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-27 05:09:16 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-27 05:09:17 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-27 05:09:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:09:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:09:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:09:17 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:09:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:09:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:09:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:09:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:17 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:09:17 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:09:17 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:09:17 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:09:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:09:17 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:09:17 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-27 05:09:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:17 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-27 05:09:18 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-27 05:09:18 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2025-04-27 05:09:19 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2025-04-27 05:09:19 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2025-04-27 05:09:19 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2025-04-27 05:09:20 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2025-04-27 05:09:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:09:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:09:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:09:20 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:09:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:09:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:09:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:09:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:09:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:09:20 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:09:20 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:09:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:09:20 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:09:20 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-27 05:09:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:09:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:09:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:09:20 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:09:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:09:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:09:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:09:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:09:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:09:20 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:09:20 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:09:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:09:20 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:09:20 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-27 05:09:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:20 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2025-04-27 05:09:21 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2025-04-27 05:09:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:09:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:09:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:09:21 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:09:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:09:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:09:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:09:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:09:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:09:21 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:09:21 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:09:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:09:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:09:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:09:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:09:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:09:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:09:21 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2025-04-27 05:09:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:09:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:09:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:09:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:09:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:09:21 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:09:21 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:09:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:09:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:09:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:09:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:22 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2025-04-27 05:09:22 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2025-04-27 05:09:23 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2025-04-27 05:09:23 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2025-04-27 05:09:24 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2025-04-27 05:09:24 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2025-04-27 05:09:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:09:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:09:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:09:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:09:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:09:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:09:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:24 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:09:24 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:09:24 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:09:24 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:09:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:09:24 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:09:24 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:09:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:09:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:09:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:09:25 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2025-04-27 05:09:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:09:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:09:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:09:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:25 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:09:25 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:09:25 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:09:25 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:09:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:09:25 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:09:25 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:09:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:25 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2025-04-27 05:09:26 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2025-04-27 05:09:26 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2025-04-27 05:09:27 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2025-04-27 05:09:27 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2025-04-27 05:09:28 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2025-04-27 05:09:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:09:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:09:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:09:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:09:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:09:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:09:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:09:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:09:28 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:09:28 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:09:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:09:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:09:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:09:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:28 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2025-04-27 05:09:29 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2025-04-27 05:09:29 [DEBUG] clck_gen.py:102 IND CLOCK 6324
2025-04-27 05:09:30 [DEBUG] clck_gen.py:102 IND CLOCK 6426
2025-04-27 05:09:30 [DEBUG] clck_gen.py:102 IND CLOCK 6528
2025-04-27 05:09:30 [DEBUG] clck_gen.py:102 IND CLOCK 6630
2025-04-27 05:09:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:09:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:09:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:09:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:09:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:09:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:09:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:31 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:09:31 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:09:31 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:09:31 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:09:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:09:31 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:09:31 [DEBUG] clck_gen.py:102 IND CLOCK 6732
2025-04-27 05:09:31 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:09:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:09:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:09:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:09:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:09:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:09:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:09:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:31 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:09:31 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:09:31 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:09:31 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:09:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:09:31 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:09:31 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:09:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:31 [DEBUG] clck_gen.py:102 IND CLOCK 6834
2025-04-27 05:09:32 [DEBUG] clck_gen.py:102 IND CLOCK 6936
2025-04-27 05:09:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:09:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:09:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:09:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:09:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:09:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:09:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:32 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:09:32 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:09:32 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:09:32 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:09:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:09:32 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:09:32 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-27 05:09:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:09:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:09:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:09:32 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:09:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:09:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:09:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:09:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:32 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:09:32 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:09:32 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:09:32 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:09:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:09:32 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:09:32 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-27 05:09:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:32 [DEBUG] clck_gen.py:102 IND CLOCK 7038
2025-04-27 05:09:33 [DEBUG] clck_gen.py:102 IND CLOCK 7140
2025-04-27 05:09:33 [DEBUG] clck_gen.py:102 IND CLOCK 7242
2025-04-27 05:09:34 [DEBUG] clck_gen.py:102 IND CLOCK 7344
2025-04-27 05:09:34 [DEBUG] clck_gen.py:102 IND CLOCK 7446
2025-04-27 05:09:35 [DEBUG] clck_gen.py:102 IND CLOCK 7548
2025-04-27 05:09:35 [DEBUG] clck_gen.py:102 IND CLOCK 7650
2025-04-27 05:09:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:09:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:09:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:09:35 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:09:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:09:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:09:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:09:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:35 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:09:35 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:09:35 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:09:35 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:09:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:09:35 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:09:35 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-27 05:09:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:09:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:09:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:09:35 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:09:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:09:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:09:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:09:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:35 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:09:35 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:09:35 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:09:35 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:09:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:09:35 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:09:35 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-27 05:09:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:36 [DEBUG] clck_gen.py:102 IND CLOCK 7752
2025-04-27 05:09:36 [DEBUG] clck_gen.py:102 IND CLOCK 7854
2025-04-27 05:09:37 [DEBUG] clck_gen.py:102 IND CLOCK 7956
2025-04-27 05:09:37 [DEBUG] clck_gen.py:102 IND CLOCK 8058
2025-04-27 05:09:38 [DEBUG] clck_gen.py:102 IND CLOCK 8160
2025-04-27 05:09:38 [DEBUG] clck_gen.py:102 IND CLOCK 8262
2025-04-27 05:09:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:09:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:09:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:09:38 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:09:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:09:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:09:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:09:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:38 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:09:38 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:09:38 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:09:38 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:09:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:09:38 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:09:38 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-27 05:09:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:39 [DEBUG] clck_gen.py:102 IND CLOCK 8364
2025-04-27 05:09:39 [DEBUG] clck_gen.py:102 IND CLOCK 8466
2025-04-27 05:09:40 [DEBUG] clck_gen.py:102 IND CLOCK 8568
2025-04-27 05:09:40 [DEBUG] clck_gen.py:102 IND CLOCK 8670
2025-04-27 05:09:40 [DEBUG] clck_gen.py:102 IND CLOCK 8772
2025-04-27 05:09:41 [DEBUG] clck_gen.py:102 IND CLOCK 8874
2025-04-27 05:09:41 [DEBUG] clck_gen.py:102 IND CLOCK 8976
2025-04-27 05:09:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:09:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:09:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:09:41 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:09:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:09:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:09:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:09:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:09:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:09:41 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:09:41 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:09:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:09:41 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:09:41 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-27 05:09:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:09:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:09:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:09:42 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:09:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:09:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:09:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:09:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:42 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:09:42 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:09:42 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:09:42 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:09:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:09:42 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:09:42 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-27 05:09:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:42 [DEBUG] clck_gen.py:102 IND CLOCK 9078
2025-04-27 05:09:42 [DEBUG] clck_gen.py:102 IND CLOCK 9180
2025-04-27 05:09:43 [DEBUG] clck_gen.py:102 IND CLOCK 9282
2025-04-27 05:09:43 [DEBUG] clck_gen.py:102 IND CLOCK 9384
2025-04-27 05:09:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:09:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:09:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:09:44 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:09:44 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:09:44 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:09:44 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:09:44 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:09:44 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:09:44 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:09:44 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:09:44 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:09:44 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:09:44 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:09:44 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:09:44 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=9487 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:09:44 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=9487 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:09:44 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=9487 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:09:44 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=9487 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:09:44 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=9487 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:09:44 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=9487 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:09:44 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=9487 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:09:49 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:09:49 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:09:49 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:09:49 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:09:49 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:09:49 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:09:49 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:09:49 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:09:49 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:09:49 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:09:49 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:09:49 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:09:49 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:09:49 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:09:49 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:09:49 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:09:49 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:09:49 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:09:49 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:09:49 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:09:49 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:09:49 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:09:49 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:09:49 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:09:49 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:09:49 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:09:49 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:09:49 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:09:49 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:09:49 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:09:49 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:09:49 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:09:49 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:09:49 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:09:49 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:09:49 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:09:49 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:09:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:09:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:09:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:09:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:09:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:09:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:09:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:09:49 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:09:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:09:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:09:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:09:49 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:09:49 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:09:49 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:09:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:09:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:09:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:09:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:09:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:09:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:09:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:09:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:09:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:09:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:09:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:09:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:09:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:09:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:09:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:09:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:09:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:09:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:09:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:09:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:09:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:09:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:09:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:09:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:09:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:09:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:09:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:09:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:09:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:09:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:09:49 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:09:49 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:09:49 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:09:49 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:09:49 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:09:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:09:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:09:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:09:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:09:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:49 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:09:49 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:09:49 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:09:49 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:09:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:09:49 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:09:49 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:09:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:09:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:09:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:09:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:09:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:09:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:09:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:50 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:09:50 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:09:50 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:09:50 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:09:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:09:50 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:09:50 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-27 05:09:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:09:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:09:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:09:50 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:09:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:09:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:09:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:09:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:50 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:09:50 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:09:50 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:09:50 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:09:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:09:50 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:09:50 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:09:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:09:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:09:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:09:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:09:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:09:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:09:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:50 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:09:50 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:09:50 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:09:50 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:09:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:09:50 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:09:50 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-27 05:09:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:50 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:09:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:09:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:09:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:09:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:09:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:09:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:09:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:09:50 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:09:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:09:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:09:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:09:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:09:50 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:09:50 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:09:50 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:09:50 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:09:50 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=227 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:09:50 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:09:50 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:09:50 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:09:50 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=227 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:09:50 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=227 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:09:50 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=227 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:09:50 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=227 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:09:55 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:09:55 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:09:55 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:09:55 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:09:55 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:09:55 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:09:55 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:09:55 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:09:55 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:09:55 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:09:55 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:09:55 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:09:55 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:09:55 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:09:55 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:09:55 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:09:55 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:09:55 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:09:55 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:09:55 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:09:55 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:09:55 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:09:55 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:09:55 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:09:55 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:09:55 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:09:55 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:09:55 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:09:55 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:09:55 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:09:55 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:09:55 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:09:55 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:09:55 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:09:55 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:09:55 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:09:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:09:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:09:55 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:09:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:09:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:09:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:09:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:09:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:09:55 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:09:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:09:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:09:55 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:09:55 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:09:55 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:09:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:09:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:09:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:09:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:09:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:09:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:09:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:09:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:09:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:09:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:09:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:09:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:09:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:09:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:09:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:09:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:09:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:09:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:09:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:09:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:09:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:09:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:09:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:09:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:09:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:09:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:09:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:09:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:09:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:09:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:09:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:09:55 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:09:55 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:09:55 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:09:55 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:09:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:09:55 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:09:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:09:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:09:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:09:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:56 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:09:56 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:09:56 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:09:56 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:09:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:09:56 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:09:56 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:09:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:56 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:09:56 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:09:56 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:09:56 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:09:56 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:09:56 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 05:09:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:09:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:09:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:09:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:09:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:09:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:09:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:56 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:09:56 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:09:56 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:09:56 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:09:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:09:57 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:09:57 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-27 05:09:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:57 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 05:09:57 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:09:57 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:09:57 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:09:57 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:09:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:09:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:09:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:09:57 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:09:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:09:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:09:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:09:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:57 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:09:57 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:09:57 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:09:57 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:09:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:09:57 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:09:57 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:09:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:09:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:09:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:09:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:09:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:09:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:09:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:57 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:09:57 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:09:57 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:09:57 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:09:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:09:57 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:09:57 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-27 05:09:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:57 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 05:09:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:09:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:09:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:09:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:09:58 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:09:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:09:58 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:09:58 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:09:58 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:09:58 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:09:58 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:09:58 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:09:58 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:09:58 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:09:58 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:09:58 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:10:03 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:10:03 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:10:03 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:10:03 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:10:03 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:10:03 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:10:03 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:10:03 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:10:03 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:10:03 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:10:03 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:10:03 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:10:03 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:10:03 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:10:03 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:10:03 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:10:03 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:10:03 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:10:03 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:10:03 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:10:03 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:10:03 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:10:03 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:10:03 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:10:03 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:10:03 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:10:03 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:10:03 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:10:03 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:10:03 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:10:03 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:10:03 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:10:03 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:10:03 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:10:03 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:10:03 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:10:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:10:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:10:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:10:03 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:10:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:10:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:10:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:10:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:10:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:10:03 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:10:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:10:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:10:03 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:10:03 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:10:03 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:10:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:10:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:10:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:10:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:10:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:10:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:10:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:10:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:10:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:10:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:10:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:10:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:10:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:10:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:10:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:10:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:10:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:10:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:10:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:10:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:10:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:10:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:10:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:10:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:10:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:10:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:10:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:10:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:10:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:10:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:10:03 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:10:03 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:10:03 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:10:03 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:10:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:10:03 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:10:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:10:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:10:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:10:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:10:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:10:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:10:03 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:10:03 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:10:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:10:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:10:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:10:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:10:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:10:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:10:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:10:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:10:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:10:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:10:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:10:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:10:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:10:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:10:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:10:04 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:10:04 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:10:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:10:04 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:10:04 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-27 05:10:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:10:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:10:04 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:10:04 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:10:04 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:10:04 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:10:04 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:10:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:10:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:10:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:10:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:10:04 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:10:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:10:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:10:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:10:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:10:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:10:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:10:04 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:10:04 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:10:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:10:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:10:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:10:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:10:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:10:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:10:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:10:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:10:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:10:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:10:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:10:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:10:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:10:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:10:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:10:04 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:10:04 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:10:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:10:04 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:10:04 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-27 05:10:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:10:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:10:04 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 05:10:05 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 05:10:05 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:10:05 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:10:05 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:10:05 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:10:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:10:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:10:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:10:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:10:05 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:10:05 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:10:05 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:10:05 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:10:05 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:10:05 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:10:05 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:10:05 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:10:05 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:10:05 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:10:05 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:10:05 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:10:10 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:10:10 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:10:10 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:10:10 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:10:10 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:10:10 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:10:10 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:10:10 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:10:10 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:10:10 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:10:10 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:10:10 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:10:10 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:10:10 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:10:10 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:10:10 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:10:10 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:10:10 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:10:10 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:10:10 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:10:10 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:10:10 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:10:10 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:10:10 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:10:10 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:10:10 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:10:10 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:10:10 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:10:10 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:10:10 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:10:10 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:10:10 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:10:10 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:10:10 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:10:10 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:10:10 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:10:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:10:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:10:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:10:10 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:10:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:10:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:10:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:10:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:10:10 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:10:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:10:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:10:10 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:10:10 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:10:10 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:10:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:10:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:10:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:10:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:10:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:10:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:10:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:10:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:10:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:10:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:10:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:10:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:10:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:10:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:10:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:10:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:10:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:10:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:10:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:10:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:10:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:10:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:10:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:10:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:10:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:10:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:10:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:10:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:10:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:10:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:10:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:10:10 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:10:11 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:10:11 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:10:11 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:10:11 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:10:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:10:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:10:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:10:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:10:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:10:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:10:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:10:11 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:10:11 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:10:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:10:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:10:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:10:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:10:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:10:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:10:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:10:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:10:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:10:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:10:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:10:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:10:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:10:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:10:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:10:11 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:10:11 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:10:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:10:11 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:10:11 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-27 05:10:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:10:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:10:11 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:10:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:10:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:10:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:10:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:10:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:10:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:10:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:10:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:10:11 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:10:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:10:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:10:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:10:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:10:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:10:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:10:11 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:10:11 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:10:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:10:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:10:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:10:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:10:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:10:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:10:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:10:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:10:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:10:12 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 05:10:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:10:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:10:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:10:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:10:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:10:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:10:12 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:10:12 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:10:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:10:12 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:10:12 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-27 05:10:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:10:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:10:12 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 05:10:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:10:12 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:10:12 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:10:12 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:10:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:10:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:10:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:10:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:10:13 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:10:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:10:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:10:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:10:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:10:13 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:10:13 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:10:13 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:10:13 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:10:13 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:10:13 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:10:13 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:10:18 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:10:18 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:10:18 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:10:18 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:10:18 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:10:18 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:10:18 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:10:18 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:10:18 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:10:18 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:10:18 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:10:18 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:10:18 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:10:18 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:10:18 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:10:18 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:10:18 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:10:18 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:10:18 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:10:18 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:10:18 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:10:18 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:10:18 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:10:18 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:10:18 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:10:18 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:10:18 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:10:18 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:10:18 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:10:18 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:10:18 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:10:18 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:10:18 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:10:18 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:10:18 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:10:18 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:10:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:10:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:10:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:10:18 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:10:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:10:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:10:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:10:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:10:18 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:10:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:10:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:10:18 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:10:18 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:10:18 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:10:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:10:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:10:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:10:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:10:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:10:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:10:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:10:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:10:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:10:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:10:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:10:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:10:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:10:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:10:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:10:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:10:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:10:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:10:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:10:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:10:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:10:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:10:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:10:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:10:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:10:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:10:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:10:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:10:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:10:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:10:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:10:18 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:10:18 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:10:18 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:10:18 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:10:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:10:18 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:10:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:10:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:10:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:10:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:10:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:10:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:10:18 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:10:18 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:10:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:10:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:10:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:10:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:10:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:10:19 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:10:19 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:10:19 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:10:19 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:10:19 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:10:19 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 05:10:19 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 05:10:20 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:10:20 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:10:20 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:10:20 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:10:20 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 05:10:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:10:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:10:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:10:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:10:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:10:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:10:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:10:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:10:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:10:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:10:20 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:10:20 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:10:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:10:20 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:10:20 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-27 05:10:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:10:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:10:20 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 05:10:21 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:10:21 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:10:21 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:10:21 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:10:21 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 05:10:21 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 05:10:22 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:10:22 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:10:22 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:10:22 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:10:22 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 05:10:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:10:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:10:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:10:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:10:22 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:10:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:10:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:10:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:10:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:10:22 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:10:22 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:10:22 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:10:22 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:10:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:10:22 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:10:22 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:10:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:10:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:10:22 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 05:10:23 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:10:23 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:10:23 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:10:23 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:10:23 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 05:10:23 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 05:10:24 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 05:10:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:10:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:10:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:10:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:10:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:10:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:10:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:10:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:10:24 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:10:24 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:10:24 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:10:24 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:10:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:10:24 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:10:24 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-27 05:10:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:10:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:10:24 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 05:10:25 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 05:10:25 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 05:10:26 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 05:10:26 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 05:10:27 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 05:10:27 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 05:10:28 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 05:10:28 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 05:10:29 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-27 05:10:29 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-27 05:10:30 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-27 05:10:30 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-27 05:10:30 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-27 05:10:31 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-27 05:10:31 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-27 05:10:32 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-27 05:10:32 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-27 05:10:33 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-27 05:10:33 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-27 05:10:34 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-27 05:10:34 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-27 05:10:35 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-27 05:10:35 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-27 05:10:36 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-27 05:10:36 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2025-04-27 05:10:37 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2025-04-27 05:10:37 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2025-04-27 05:10:38 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2025-04-27 05:10:38 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2025-04-27 05:10:39 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2025-04-27 05:10:39 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2025-04-27 05:10:40 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2025-04-27 05:10:40 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2025-04-27 05:10:41 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2025-04-27 05:10:41 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2025-04-27 05:10:41 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2025-04-27 05:10:42 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2025-04-27 05:10:42 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2025-04-27 05:10:43 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2025-04-27 05:10:43 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2025-04-27 05:10:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:10:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:10:44 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:10:44 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:10:44 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:10:44 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:10:44 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:10:44 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:10:44 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:10:44 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:10:44 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:10:44 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:10:44 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:10:44 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:10:44 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=5611 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:10:44 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=5611 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:10:44 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=5611 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:10:44 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=5611 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:10:44 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=5611 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:10:44 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=5612 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:10:44 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=5612 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:10:44 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=5612 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:10:44 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=5612 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:10:44 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=5612 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:10:44 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=5612 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:10:44 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=5612 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:10:44 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=5612 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:10:49 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:10:49 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:10:49 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:10:49 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:10:49 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:10:49 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:10:49 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:10:49 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:10:49 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:10:49 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:10:49 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:10:49 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:10:49 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:10:49 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:10:49 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:10:49 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:10:49 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:10:49 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:10:49 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:10:49 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:10:49 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:10:49 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:10:49 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:10:49 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:10:49 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:10:49 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:10:49 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:10:49 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:10:49 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:10:49 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:10:49 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:10:49 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:10:49 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:10:49 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:10:49 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:10:49 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:10:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:10:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:10:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:10:49 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:10:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:10:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:10:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:10:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:10:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:10:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:10:49 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:10:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:10:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:10:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:10:49 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:10:49 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:10:49 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:10:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:10:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:10:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:10:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:10:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:10:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:10:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:10:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:10:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:10:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:10:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:10:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:10:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:10:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:10:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:10:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:10:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:10:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:10:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:10:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:10:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:10:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:10:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:10:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:10:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:10:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:10:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:10:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:10:49 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:10:49 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:10:49 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:10:49 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:10:49 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:10:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:10:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:10:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:10:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:10:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:10:49 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:10:49 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:10:49 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:10:49 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:10:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:10:49 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:10:49 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:10:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:10:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:10:50 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:10:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:10:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:10:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:10:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:10:50 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 05:10:51 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 05:10:51 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:10:51 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:10:51 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:10:51 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:10:51 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 05:10:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:10:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:10:51 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:10:51 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:10:51 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:10:51 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:10:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:10:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:10:51 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:10:51 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:10:51 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:10:51 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:10:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:10:51 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:10:51 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-27 05:10:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:10:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:10:52 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 05:10:52 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:10:52 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:10:52 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:10:52 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:10:52 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 05:10:53 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 05:10:53 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:10:53 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:10:53 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:10:53 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:10:53 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 05:10:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:10:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:10:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:10:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:10:53 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:10:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:10:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:10:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:10:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:10:53 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:10:53 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:10:53 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:10:53 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:10:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:10:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:10:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:10:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:10:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:10:54 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 05:10:54 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:10:54 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:10:54 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:10:54 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:10:54 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 05:10:55 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 05:10:55 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 05:10:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:10:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:10:55 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:10:55 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:10:55 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:10:55 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:10:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:10:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:10:55 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:10:55 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:10:55 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:10:55 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:10:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:10:55 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:10:55 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-27 05:10:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:10:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:10:56 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 05:10:56 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 05:10:56 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 05:10:57 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 05:10:57 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 05:10:58 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 05:10:58 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 05:10:59 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 05:10:59 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 05:11:00 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-27 05:11:00 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-27 05:11:01 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-27 05:11:01 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-27 05:11:02 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-27 05:11:02 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-27 05:11:03 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-27 05:11:03 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-27 05:11:04 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-27 05:11:04 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-27 05:11:05 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-27 05:11:05 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-27 05:11:05 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-27 05:11:06 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-27 05:11:06 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-27 05:11:07 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-27 05:11:07 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2025-04-27 05:11:08 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2025-04-27 05:11:08 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2025-04-27 05:11:09 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2025-04-27 05:11:09 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2025-04-27 05:11:10 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2025-04-27 05:11:10 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2025-04-27 05:11:11 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2025-04-27 05:11:11 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2025-04-27 05:11:12 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2025-04-27 05:11:12 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2025-04-27 05:11:13 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2025-04-27 05:11:13 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2025-04-27 05:11:14 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2025-04-27 05:11:14 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2025-04-27 05:11:15 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2025-04-27 05:11:15 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2025-04-27 05:11:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:11:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:11:15 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:11:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:11:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:11:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:11:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:11:15 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:11:15 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:11:15 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:11:15 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:11:15 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:11:15 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:11:15 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:11:15 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=5630 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:11:15 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=5630 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:11:15 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=5630 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:11:15 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=5630 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:11:15 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=5630 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:11:15 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=5630 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:11:15 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=5630 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:11:20 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:11:20 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:11:20 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:11:20 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:11:20 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:11:20 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:11:20 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:11:20 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:11:20 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:11:20 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:11:20 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:11:20 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:11:20 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:11:20 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:11:20 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:11:20 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:11:20 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:11:20 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:11:20 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:11:20 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:11:20 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:11:20 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:11:20 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:11:20 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:11:20 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:11:20 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:11:20 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:11:20 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:11:20 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:11:20 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:11:20 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:11:20 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:11:20 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:11:20 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:11:20 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:11:20 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:11:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:11:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:11:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:11:20 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:11:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:11:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:11:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:11:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:11:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:11:20 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:11:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:11:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:11:20 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:11:20 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:11:20 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:11:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:11:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:11:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:11:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:11:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:11:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:11:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:11:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:11:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:11:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:11:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:11:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:11:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:11:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:11:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:11:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:11:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:11:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:11:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:11:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:11:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:11:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:11:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:11:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:11:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:11:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:11:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:11:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:11:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:11:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:11:20 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:11:21 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:11:21 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:11:21 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:11:21 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:11:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:11:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:11:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:11:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:11:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:11:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:11:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:11:21 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:11:21 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:11:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:11:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:11:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:11:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:11:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:11:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:11:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:11:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:11:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:11:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:11:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:11:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:11:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:11:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:11:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:11:21 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:11:21 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:11:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:11:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:11:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:11:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:11:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:11:21 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:11:21 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:11:21 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:11:21 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:11:21 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:11:22 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 05:11:22 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 05:11:22 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:11:22 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:11:22 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:11:22 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:11:23 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 05:11:23 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 05:11:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:11:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:11:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:11:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:11:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:11:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:11:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:11:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:11:23 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:11:23 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:11:23 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:11:23 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:11:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:11:23 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:11:23 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:11:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:11:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:11:23 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:11:23 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:11:23 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:11:23 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:11:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:11:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:11:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:11:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:11:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:11:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:11:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:11:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:11:23 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:11:23 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:11:23 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:11:23 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:11:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:11:23 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:11:23 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:11:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:11:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:11:23 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 05:11:24 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 05:11:24 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:11:24 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:11:24 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:11:24 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:11:24 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 05:11:25 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 05:11:25 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:11:25 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:11:25 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:11:25 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:11:25 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 05:11:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:11:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:11:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:11:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:11:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:11:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:11:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:11:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:11:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:11:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:11:26 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:11:26 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:11:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:11:26 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:11:26 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-27 05:11:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:11:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:11:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:11:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:11:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:11:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:11:26 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:11:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:11:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:11:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:11:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:11:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:11:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:11:26 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:11:26 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:11:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:11:26 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 05:11:26 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:11:26 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-27 05:11:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:11:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:11:26 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 05:11:27 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 05:11:27 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 05:11:28 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 05:11:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:11:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:11:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:11:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:11:28 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:11:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:11:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:11:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:11:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:11:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:11:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:11:28 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:11:28 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:11:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:11:28 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:11:28 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-27 05:11:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:11:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:11:28 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 05:11:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:11:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:11:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:11:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:11:29 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:11:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:11:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:11:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:11:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:11:29 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:11:29 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:11:29 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:11:29 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:11:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:11:29 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:11:29 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-27 05:11:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:11:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:11:29 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 05:11:29 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 05:11:30 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 05:11:30 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 05:11:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:11:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:11:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:11:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:11:31 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:11:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:11:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:11:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:11:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:11:31 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:11:31 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:11:31 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:11:31 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:11:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:11:31 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:11:31 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:11:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:11:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:11:31 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 05:11:31 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-27 05:11:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:11:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:11:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:11:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:11:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:11:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:11:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:11:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:11:31 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:11:31 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:11:31 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:11:31 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:11:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:11:31 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:11:31 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:11:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:11:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:11:32 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-27 05:11:32 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-27 05:11:33 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-27 05:11:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:11:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:11:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:11:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:11:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:11:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:11:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:11:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:11:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:11:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:11:33 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:11:33 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:11:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:11:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:11:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:11:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:11:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:11:33 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-27 05:11:34 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-27 05:11:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:11:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:11:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:11:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:11:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:11:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:11:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:11:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:11:34 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:11:34 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:11:34 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:11:34 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:11:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:11:34 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:11:34 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:11:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:11:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:11:34 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-27 05:11:34 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-27 05:11:35 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-27 05:11:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:11:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:11:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:11:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:11:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:11:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:11:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:11:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:11:35 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:11:35 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:11:35 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:11:35 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:11:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:11:35 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:11:35 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-27 05:11:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:11:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:11:35 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-27 05:11:36 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-27 05:11:36 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-27 05:11:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:11:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:11:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:11:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:11:37 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:11:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:11:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:11:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:11:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:11:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:11:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:11:37 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:11:37 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:11:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:11:37 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:11:37 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-27 05:11:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:11:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:11:37 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-27 05:11:37 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-27 05:11:38 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-27 05:11:38 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-27 05:11:39 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2025-04-27 05:11:39 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2025-04-27 05:11:40 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2025-04-27 05:11:40 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2025-04-27 05:11:41 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2025-04-27 05:11:41 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2025-04-27 05:11:42 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2025-04-27 05:11:42 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2025-04-27 05:11:43 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2025-04-27 05:11:43 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2025-04-27 05:11:43 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2025-04-27 05:11:44 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2025-04-27 05:11:44 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2025-04-27 05:11:45 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2025-04-27 05:11:45 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2025-04-27 05:11:46 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2025-04-27 05:11:46 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2025-04-27 05:11:47 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2025-04-27 05:11:47 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2025-04-27 05:11:48 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2025-04-27 05:11:48 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2025-04-27 05:11:49 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2025-04-27 05:11:49 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2025-04-27 05:11:50 [DEBUG] clck_gen.py:102 IND CLOCK 6324
2025-04-27 05:11:50 [DEBUG] clck_gen.py:102 IND CLOCK 6426
2025-04-27 05:11:51 [DEBUG] clck_gen.py:102 IND CLOCK 6528
2025-04-27 05:11:51 [DEBUG] clck_gen.py:102 IND CLOCK 6630
2025-04-27 05:11:52 [DEBUG] clck_gen.py:102 IND CLOCK 6732
2025-04-27 05:11:52 [DEBUG] clck_gen.py:102 IND CLOCK 6834
2025-04-27 05:11:53 [DEBUG] clck_gen.py:102 IND CLOCK 6936
2025-04-27 05:11:53 [DEBUG] clck_gen.py:102 IND CLOCK 7038
2025-04-27 05:11:53 [DEBUG] clck_gen.py:102 IND CLOCK 7140
2025-04-27 05:11:54 [DEBUG] clck_gen.py:102 IND CLOCK 7242
2025-04-27 05:11:54 [DEBUG] clck_gen.py:102 IND CLOCK 7344
2025-04-27 05:11:55 [DEBUG] clck_gen.py:102 IND CLOCK 7446
2025-04-27 05:11:55 [DEBUG] clck_gen.py:102 IND CLOCK 7548
2025-04-27 05:11:56 [DEBUG] clck_gen.py:102 IND CLOCK 7650
2025-04-27 05:11:56 [DEBUG] clck_gen.py:102 IND CLOCK 7752
2025-04-27 05:11:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:11:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:11:57 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:11:57 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:11:57 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:11:57 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:11:57 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:11:57 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:11:57 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:11:57 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:11:57 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:11:57 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:11:57 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:11:57 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:11:57 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=7830 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:11:57 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=7830 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:11:57 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=7830 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:11:57 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=7830 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:11:57 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=7830 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:11:57 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=7830 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:12:02 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:12:02 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:12:02 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:12:02 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:12:02 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:12:02 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:12:02 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:12:02 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:12:02 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:12:02 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:12:02 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:12:02 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:12:02 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:12:02 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:12:02 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:12:02 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:12:02 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:12:02 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:12:02 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:12:02 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:12:02 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:12:02 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:12:02 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:12:02 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:12:02 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:12:02 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:12:02 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:12:02 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:12:02 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:12:02 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:12:02 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:12:02 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:12:02 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:12:02 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:12:02 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:12:02 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:12:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:12:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:12:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:12:02 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:12:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:12:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:12:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:12:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:12:02 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:12:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:12:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:12:02 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:12:02 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:12:02 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:12:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:12:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:12:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:12:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:12:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:12:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:12:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:12:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:12:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:12:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:12:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:12:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:12:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:12:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:12:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:12:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:12:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:12:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:12:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:12:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:12:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:12:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:12:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:12:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:12:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:12:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:12:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:12:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:12:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:12:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:12:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:12:02 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:12:02 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:12:02 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:12:02 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:12:02 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:12:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:12:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:12:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:12:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:12:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:12:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:12:02 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:12:02 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:12:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:12:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:12:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:12:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:12:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:12:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:12:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:12:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:12:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:12:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:12:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:12:02 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:12:02 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:12:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:12:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:12:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:12:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:12:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:12:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:12:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:12:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:12:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:12:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:12:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:12:02 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:12:02 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:12:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:12:03 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:12:03 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-27 05:12:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:12:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:12:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:12:03 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:12:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:12:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:12:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:12:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:12:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:12:03 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:12:03 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:12:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:12:03 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:12:03 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-27 05:12:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:03 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:12:03 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:12:03 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:12:03 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:12:03 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:12:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:12:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:12:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:12:03 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:12:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:12:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:12:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:12:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:12:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:12:03 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:12:03 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:12:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:12:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:12:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:12:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:12:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:12:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:12:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:12:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:12:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:12:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:12:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:12:03 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:12:03 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:12:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:12:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:12:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:12:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:12:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:12:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:12:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:12:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:12:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:12:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:12:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:12:03 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:12:03 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:12:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:12:03 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 05:12:03 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:12:03 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-27 05:12:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:12:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:12:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:12:03 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:12:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:12:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:12:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:12:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:12:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:12:03 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:12:03 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:12:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:12:03 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:12:03 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-27 05:12:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:12:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:12:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:12:03 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:12:04 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:12:04 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:12:04 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:12:04 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:12:04 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:12:04 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:12:04 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:12:04 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:12:04 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:12:04 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:12:04 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:12:09 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:12:09 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:12:09 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:12:09 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:12:09 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:12:09 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:12:09 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:12:09 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:12:09 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:12:09 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:12:09 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:12:09 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:12:09 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:12:09 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:12:09 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:12:09 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:12:09 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:12:09 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:12:09 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:12:09 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:12:09 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:12:09 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:12:09 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:12:09 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:12:09 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:12:09 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:12:09 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:12:09 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:12:09 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:12:09 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:12:09 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:12:09 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:12:09 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:12:09 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:12:09 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:12:09 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:12:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:12:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:12:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:12:09 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:12:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:12:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:12:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:12:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:12:09 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:12:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:12:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:12:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:12:09 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:12:09 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:12:09 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:12:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:12:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:12:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:12:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:12:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:12:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:12:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:12:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:12:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:12:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:12:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:12:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:12:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:12:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:12:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:12:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:12:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:12:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:12:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:12:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:12:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:12:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:12:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:12:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:12:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:12:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:12:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:12:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:12:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:12:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:12:09 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:12:09 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:12:09 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:12:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:12:09 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:12:09 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:12:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:12:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:12:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:12:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:12:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:12:09 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:12:09 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:12:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:12:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:12:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:12:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:10 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:12:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:12:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:12:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:12:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:12:10 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 05:12:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:12:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:12:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:12:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:12:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:12:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:12:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:10 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:12:10 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:12:10 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:12:10 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:12:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:12:10 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:12:10 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:12:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:10 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 05:12:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:12:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:12:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:12:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:12:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:12:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:12:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:12:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:12:11 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:12:11 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:12:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:12:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:12:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:12:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:12:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:12:11 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:12:11 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-27 05:12:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:11 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 05:12:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:12:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:12:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:12:11 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:12:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:12:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:12:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:12:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:12:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:12:11 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:12:11 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:12:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:12:11 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:12:11 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-27 05:12:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:11 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 05:12:12 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:12:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:12:12 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:12:12 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:12:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:12:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:12:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:12:12 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:12:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:12:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:12:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:12:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:12:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:12:12 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:12:12 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:12:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:12:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:12:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:12:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:12:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:12:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:12:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:12:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:12:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:12:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:12:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:12:12 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:12:12 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:12:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:12:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:12:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:12:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:12 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 05:12:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:12:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:12:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:12:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:12:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:12:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:12:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:12:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:12:12 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:12:12 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:12:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:12:12 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:12:12 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-27 05:12:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:12 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 05:12:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:12:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:12:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:12:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:12:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:12:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:12:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:12:13 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:12:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:12:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:12:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:12:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:12:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:12:13 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:12:13 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:12:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:12:13 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 05:12:13 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:12:13 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-27 05:12:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:12:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:12:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:12:13 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:12:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:12:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:12:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:12:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:12:13 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:12:13 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:12:13 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:12:13 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:12:13 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1007 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:12:13 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:12:13 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:12:13 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:12:18 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:12:18 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:12:18 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:12:18 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:12:18 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:12:18 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:12:18 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:12:18 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:12:18 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:12:18 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:12:18 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:12:18 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:12:18 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:12:18 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:12:18 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:12:18 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:12:18 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:12:18 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:12:18 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:12:18 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:12:18 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:12:18 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:12:18 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:12:18 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:12:18 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:12:18 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:12:18 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:12:18 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:12:18 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:12:18 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:12:18 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:12:18 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:12:18 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:12:18 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:12:18 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:12:18 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:12:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:12:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:12:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:12:18 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:12:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:12:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:12:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:12:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:12:18 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:12:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:12:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:12:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:12:18 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:12:18 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:12:18 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:12:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:12:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:12:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:12:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:12:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:12:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:12:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:12:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:12:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:12:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:12:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:12:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:12:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:12:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:12:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:12:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:12:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:12:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:12:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:12:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:12:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:12:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:12:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:12:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:12:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:12:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:12:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:12:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:12:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:12:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:12:18 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:12:19 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:12:19 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:12:19 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:12:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:12:19 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:12:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:12:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:12:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:12:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:19 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:12:19 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:12:19 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:12:19 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:12:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:12:19 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:12:19 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:12:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:12:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:12:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:12:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:12:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:12:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:12:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:19 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:12:19 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:12:19 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:12:19 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:12:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:12:19 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:12:19 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:12:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:12:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:12:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:12:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:12:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:12:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:12:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:19 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:12:19 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:12:19 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:12:19 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:12:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:12:19 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:12:19 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-27 05:12:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:12:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:12:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:12:19 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:12:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:12:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:12:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:12:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:19 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:12:19 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:12:19 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:12:19 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:12:19 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:12:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:12:19 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:12:19 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-27 05:12:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:19 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:12:19 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:12:19 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:12:19 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:12:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:12:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:12:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:12:19 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:12:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:12:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:12:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:12:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:19 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:12:19 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:12:19 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:12:19 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:12:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:12:19 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:12:19 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:12:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:12:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:12:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:12:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:12:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:12:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:12:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:19 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:12:19 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:12:19 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:12:19 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:12:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:12:19 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:12:19 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:12:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:12:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:12:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:12:20 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 05:12:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:12:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:12:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:12:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:12:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:12:20 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:12:20 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:12:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:12:20 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:12:20 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-27 05:12:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:20 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 05:12:20 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:12:20 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:12:20 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:12:20 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:12:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:12:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:12:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:12:20 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:12:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:12:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:12:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:12:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:12:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:12:20 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:12:20 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:12:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:12:20 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:12:20 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-27 05:12:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:12:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:12:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:12:21 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:12:21 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:12:21 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:12:21 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:12:21 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:12:21 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:12:21 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:12:21 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:12:21 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:12:21 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:12:21 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:12:21 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:12:26 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:12:26 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:12:26 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:12:26 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:12:26 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:12:26 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:12:26 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:12:26 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:12:26 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:12:26 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:12:26 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:12:26 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:12:26 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:12:26 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:12:26 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:12:26 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:12:26 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:12:26 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:12:26 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:12:26 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:12:26 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:12:26 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:12:26 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:12:26 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:12:26 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:12:26 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:12:26 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:12:26 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:12:26 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:12:26 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:12:26 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:12:26 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:12:26 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:12:26 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:12:26 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:12:26 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:12:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:12:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:12:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:12:26 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:12:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:12:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:12:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:12:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:12:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:12:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:12:26 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:12:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:12:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:12:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:12:26 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:12:26 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:12:26 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:12:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:12:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:12:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:12:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:12:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:12:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:12:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:12:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:12:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:12:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:12:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:12:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:12:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:12:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:12:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:12:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:12:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:12:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:12:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:12:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:12:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:12:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:12:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:12:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:12:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:12:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:12:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:12:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:12:26 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:12:26 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:12:26 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:12:26 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:12:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:12:26 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:12:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:12:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:12:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:12:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:12:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:12:26 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:12:26 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:12:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:12:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:12:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:12:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:27 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:12:27 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:12:27 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:12:27 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:12:27 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:12:27 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 05:12:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:12:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:12:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:12:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:12:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:12:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:12:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:27 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:12:27 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:12:27 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:12:27 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:12:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:12:27 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:12:27 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:12:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:27 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 05:12:28 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:12:28 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:12:28 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:12:28 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:12:28 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 05:12:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:12:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:12:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:12:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:12:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:12:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:12:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:12:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:12:28 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:12:28 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:12:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:12:28 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:12:28 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-27 05:12:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:28 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 05:12:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:12:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:12:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:12:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:12:29 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 05:12:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:12:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:12:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:12:29 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:12:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:12:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:12:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:12:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:29 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:12:29 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:12:29 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:12:29 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:12:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:12:29 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:12:29 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-27 05:12:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:29 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 05:12:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:12:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:12:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:12:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:12:30 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 05:12:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:12:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:12:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:12:30 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:12:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:12:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:12:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:12:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:30 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:12:30 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:12:30 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:12:30 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:12:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:12:30 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:12:30 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:12:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:30 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 05:12:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:12:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:12:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:12:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:12:31 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 05:12:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:12:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:12:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:12:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:12:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:12:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:12:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:31 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:12:31 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:12:31 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:12:31 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:12:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:12:31 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:12:31 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:12:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:31 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 05:12:32 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 05:12:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:12:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:12:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:12:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:12:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:12:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:12:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:32 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:12:32 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:12:32 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:12:32 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:12:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:12:32 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:12:32 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-27 05:12:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:32 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 05:12:33 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 05:12:33 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 05:12:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:12:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:12:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:12:34 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:12:34 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 05:12:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:12:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:12:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:12:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:34 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:12:34 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:12:34 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:12:34 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:12:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:12:34 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:12:34 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-27 05:12:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:34 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 05:12:35 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 05:12:35 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 05:12:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:12:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:36 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:12:36 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:12:36 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:12:36 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:12:36 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:12:36 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:12:36 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:12:36 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:12:36 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:12:36 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:12:36 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:12:36 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:12:36 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:12:36 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:12:36 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2143 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:12:36 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2143 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:12:36 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2143 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:12:36 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2143 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:12:36 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2143 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:12:36 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2143 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:12:36 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2144 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:12:36 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2144 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:12:36 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2144 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:12:36 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2144 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:12:36 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2144 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:12:36 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2144 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:12:36 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2144 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:12:36 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2144 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:12:36 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2145 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:12:36 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2145 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:12:36 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2145 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:12:36 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2145 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:12:36 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2145 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:12:36 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2145 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:12:36 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2145 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:12:36 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2145 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:12:41 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:12:41 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:12:41 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:12:41 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:12:41 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:12:41 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:12:41 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:12:41 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:12:41 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:12:41 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:12:41 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:12:41 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:12:41 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:12:41 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:12:41 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:12:41 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:12:41 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:12:41 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:12:41 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:12:41 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:12:41 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:12:41 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:12:41 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:12:41 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:12:41 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:12:41 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:12:41 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:12:41 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:12:41 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:12:41 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:12:41 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:12:41 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:12:41 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:12:41 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:12:41 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:12:41 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:12:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:12:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:12:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:12:41 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:12:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:12:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:12:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:12:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:12:41 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:12:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:12:41 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:12:41 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:12:41 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:12:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:12:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:12:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:12:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:12:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:12:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:12:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:12:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:12:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:12:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:12:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:12:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:12:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:12:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:12:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:12:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:12:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:12:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:12:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:12:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:12:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:12:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:12:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:12:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:12:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:12:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:12:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:12:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:12:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:12:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:12:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:12:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:12:41 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:12:41 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:12:41 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:12:41 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:12:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:12:41 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:12:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:12:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:12:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:12:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:12:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:12:41 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:12:41 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:12:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:12:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:12:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:12:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:12:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:12:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:12:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:12:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:12:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:12:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:12:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:12:41 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:12:41 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:12:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:12:41 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:12:41 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-27 05:12:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:12:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:12:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:12:42 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:12:42 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:12:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:12:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:12:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:12:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:42 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:12:42 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:12:42 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:12:42 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:12:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:12:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:12:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:12:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:12:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:12:42 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:12:42 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:12:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:12:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:12:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:12:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:12:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:12:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:12:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:42 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:12:42 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:12:42 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:12:42 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:12:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:12:42 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:12:42 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-27 05:12:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:42 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 05:12:43 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 05:12:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:12:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:12:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:12:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:12:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:12:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:12:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:12:43 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:12:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:12:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:12:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:12:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:12:43 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:12:43 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:12:43 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:12:43 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:12:43 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:12:43 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:12:43 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:12:43 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=447 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:12:43 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=447 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:12:43 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=447 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:12:43 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=447 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:12:43 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=447 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:12:43 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=447 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:12:43 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=447 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:12:48 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:12:48 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:12:48 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:12:48 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:12:48 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:12:48 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:12:48 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:12:48 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:12:48 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:12:48 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:12:48 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:12:48 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:12:48 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:12:48 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:12:48 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:12:48 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:12:48 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:12:48 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:12:48 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:12:48 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:12:48 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:12:48 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:12:48 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:12:48 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:12:48 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:12:48 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:12:48 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:12:48 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:12:48 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:12:48 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:12:48 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:12:48 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:12:48 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:12:48 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:12:48 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:12:48 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:12:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:12:48 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:12:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:12:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:12:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:12:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:12:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:12:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:12:48 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:12:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:12:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:12:48 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:12:48 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:12:48 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:12:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:12:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:12:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:12:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:12:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:12:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:12:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:12:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:12:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:12:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:12:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:12:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:12:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:12:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:12:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:12:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:12:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:12:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:12:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:12:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:12:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:12:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:12:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:12:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:12:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:12:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:12:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:12:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:12:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:12:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:12:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:12:48 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:12:48 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:12:48 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:12:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:12:48 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:12:48 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:12:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:12:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:12:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:12:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:48 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:12:48 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:12:48 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:12:48 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:12:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:12:48 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:12:48 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:12:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:12:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:12:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:12:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:12:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:12:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:12:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:48 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:12:48 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:12:48 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:12:48 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:12:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:12:48 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:12:48 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-27 05:12:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:12:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:12:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:12:49 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:12:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:12:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:12:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:12:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:49 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:12:49 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:12:49 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:12:49 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:12:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:12:49 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:12:49 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:12:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:49 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:12:49 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:12:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:12:49 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:12:49 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:12:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:12:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:12:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:12:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:12:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:12:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:12:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:49 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:12:49 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:12:49 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:12:49 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:12:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:12:49 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:12:49 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-27 05:12:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:49 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 05:12:50 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 05:12:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:12:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:12:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:12:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:12:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:12:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:12:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:12:50 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:12:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:12:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:12:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:12:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:12:50 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:12:50 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:12:50 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:12:50 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:12:50 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:12:50 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:12:50 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:12:50 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=447 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:12:50 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=447 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:12:50 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=447 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:12:50 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=447 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:12:50 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=447 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:12:50 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=447 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:12:50 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=448 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:12:50 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=448 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:12:50 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=448 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:12:50 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=448 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:12:50 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=448 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:12:50 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=448 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:12:50 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=448 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:12:50 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=448 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:12:55 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:12:55 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:12:55 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:12:55 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:12:55 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:12:55 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:12:55 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:12:55 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:12:55 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:12:55 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:12:55 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:12:55 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:12:55 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:12:55 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:12:55 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:12:55 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:12:55 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:12:55 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:12:55 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:12:55 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:12:55 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:12:55 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:12:55 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:12:55 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:12:55 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:12:55 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:12:55 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:12:55 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:12:55 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:12:55 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:12:55 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:12:55 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:12:55 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:12:55 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:12:55 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:12:55 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:12:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:12:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:12:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:12:55 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:12:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:12:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:12:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:12:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:12:55 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:12:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:12:55 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:12:55 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:12:55 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:12:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:12:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:12:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:12:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:12:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:12:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:12:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:12:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:12:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:12:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:12:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:12:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:12:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:12:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:12:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:12:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:12:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:12:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:12:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:12:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:12:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:12:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:12:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:12:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:12:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:12:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:12:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:12:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:12:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:12:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:12:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:12:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:12:55 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:12:55 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:12:55 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:12:55 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:12:55 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:12:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:12:55 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:12:55 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:12:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:12:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:55 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:12:55 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:12:55 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:12:55 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:12:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:12:55 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:12:55 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:12:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:12:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:12:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:12:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:12:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:12:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:12:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:56 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:12:56 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:12:56 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:12:56 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:12:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:12:56 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:12:56 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-27 05:12:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:12:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:12:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:12:56 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:12:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:12:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:12:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:12:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:56 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:12:56 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:12:56 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:12:56 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:12:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:12:56 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:12:56 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:12:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:56 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:12:56 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:12:56 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:12:56 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:12:56 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:12:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:12:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:12:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:12:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:12:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:12:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:12:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:56 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:12:56 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:12:56 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:12:56 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:12:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:12:56 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:12:56 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-27 05:12:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:56 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 05:12:57 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 05:12:57 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:12:57 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:12:57 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:12:57 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:12:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:12:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:12:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:12:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:12:57 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:12:57 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:12:57 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:12:57 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:12:57 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:12:57 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:12:57 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:12:57 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:12:57 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:12:57 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:12:57 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:12:57 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:13:02 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:13:02 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:13:02 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:13:02 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:13:02 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:13:02 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:13:02 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:13:02 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:13:02 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:13:02 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:13:02 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:13:02 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:13:02 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:13:02 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:13:02 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:13:02 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:13:02 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:13:02 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:13:02 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:13:02 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:13:02 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:13:02 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:13:02 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:13:02 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:13:02 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:13:02 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:13:02 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:13:02 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:13:02 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:13:02 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:13:02 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:13:02 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:13:02 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:13:02 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:13:02 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:13:02 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:13:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:13:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:13:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:13:02 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:13:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:13:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:13:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:13:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:13:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:13:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:13:02 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:13:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:13:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:13:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:13:02 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:13:02 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:13:02 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:13:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:13:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:13:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:13:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:13:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:13:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:13:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:13:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:13:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:13:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:13:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:13:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:13:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:13:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:13:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:13:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:13:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:13:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:13:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:13:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:13:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:13:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:13:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:13:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:13:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:13:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:13:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:13:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:13:02 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:13:03 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:13:03 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:13:03 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:13:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:13:03 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:13:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:13:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:13:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:13:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:13:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:13:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:13:03 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:13:03 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:13:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:13:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:13:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:13:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:13:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:13:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:13:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:13:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:13:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:13:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:13:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:13:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:13:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:13:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:13:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:13:03 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:13:03 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:13:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:13:03 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:13:03 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-27 05:13:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:13:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:13:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:13:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:13:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:13:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:13:03 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:13:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:13:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:13:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:13:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:13:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:13:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:13:03 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:13:03 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:13:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:13:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:13:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:13:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:13:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:13:03 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:13:03 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:13:03 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:13:03 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:13:03 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:13:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:13:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:13:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:13:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:13:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:13:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:13:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:13:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:13:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:13:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:13:03 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:13:03 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:13:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:13:03 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:13:03 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-27 05:13:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:13:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:13:03 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 05:13:04 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 05:13:04 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:13:04 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:13:04 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:13:04 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:13:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:13:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:13:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:13:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:13:04 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:13:04 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:13:04 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:13:04 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:13:04 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:13:04 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:13:04 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:13:04 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:13:04 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:13:04 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:13:04 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:13:04 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:13:04 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=447 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:13:04 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=447 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:13:04 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=447 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:13:04 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=447 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:13:04 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=447 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:13:04 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=447 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:13:04 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=447 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:13:09 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:13:09 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:13:09 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:13:09 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:13:09 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:13:09 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:13:09 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:13:09 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:13:09 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:13:09 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:13:09 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:13:09 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:13:09 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:13:09 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:13:09 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:13:09 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:13:09 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:13:09 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:13:09 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:13:09 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:13:09 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:13:09 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:13:09 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:13:09 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:13:09 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:13:09 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:13:09 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:13:09 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:13:09 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:13:09 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:13:09 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:13:09 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:13:09 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:13:09 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:13:09 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:13:09 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:13:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:13:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:13:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:13:09 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:13:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:13:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:13:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:13:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:13:09 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:13:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:13:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:13:09 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:13:09 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:13:09 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:13:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:13:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:13:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:13:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:13:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:13:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:13:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:13:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:13:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:13:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:13:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:13:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:13:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:13:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:13:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:13:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:13:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:13:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:13:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:13:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:13:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:13:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:13:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:13:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:13:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:13:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:13:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:13:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:13:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:13:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:13:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:13:09 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:13:10 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:13:10 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:13:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:13:10 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:13:10 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:13:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:13:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:13:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:13:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:13:10 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:13:10 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:13:10 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:13:10 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:13:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:13:10 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:13:10 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:13:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:13:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:13:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:13:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:13:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:13:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:13:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:13:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:13:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:13:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:13:10 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:13:10 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:13:10 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:13:10 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:13:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:13:10 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:13:10 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:13:10 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-27 05:13:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:13:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:13:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:13:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:13:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:13:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:13:11 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 05:13:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:13:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:13:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:13:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:13:11 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:13:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:13:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:13:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:13:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:13:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:13:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:13:11 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:13:11 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:13:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:13:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:13:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:13:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:13:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:13:11 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 05:13:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:13:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:13:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:13:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:13:12 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 05:13:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:13:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:13:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:13:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:13:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:13:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:13:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:13:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:13:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:13:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:13:12 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:13:12 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:13:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:13:12 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:13:12 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-27 05:13:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:13:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:13:12 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 05:13:12 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:13:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:13:12 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:13:12 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:13:12 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 05:13:13 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 05:13:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:13:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:13:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:13:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:13:13 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 05:13:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:13:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:13:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:13:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:13:14 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:13:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:13:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:13:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:13:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:13:14 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:13:14 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:13:14 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:13:14 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:13:14 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=991 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:13:14 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:13:14 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:13:14 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:13:14 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=991 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:13:14 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=991 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:13:14 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=991 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:13:14 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=991 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:13:19 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:13:19 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:13:19 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:13:19 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:13:19 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:13:19 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:13:19 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:13:19 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:13:19 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:13:19 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:13:19 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:13:19 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:13:19 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:13:19 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:13:19 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:13:19 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:13:19 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:13:19 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:13:19 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:13:19 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:13:19 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:13:19 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:13:19 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:13:19 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:13:19 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:13:19 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:13:19 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:13:19 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:13:19 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:13:19 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:13:19 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:13:19 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:13:19 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:13:19 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:13:19 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:13:19 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:13:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:13:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:13:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:13:19 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:13:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:13:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:13:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:13:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:13:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:13:19 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:13:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:13:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:13:19 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:13:19 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:13:19 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:13:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:13:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:13:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:13:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:13:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:13:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:13:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:13:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:13:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:13:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:13:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:13:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:13:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:13:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:13:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:13:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:13:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:13:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:13:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:13:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:13:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:13:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:13:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:13:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:13:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:13:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:13:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:13:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:13:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:13:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:13:19 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:13:19 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:13:19 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:13:19 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:13:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:13:19 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:13:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:13:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:13:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:13:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:13:19 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:13:19 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:13:19 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:13:19 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:13:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:13:19 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:13:19 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:13:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:13:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:13:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:13:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:13:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:13:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:13:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:13:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:13:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:13:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:13:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:13:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:13:20 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:13:20 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:13:20 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:13:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:13:20 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:13:20 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-27 05:13:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:13:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:13:20 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:13:20 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:13:20 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:13:20 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:13:20 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 05:13:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:13:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:13:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:13:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:13:20 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:13:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:13:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:13:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:13:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:13:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:13:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:13:20 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:13:20 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:13:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:13:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:13:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:13:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:13:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:13:21 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 05:13:21 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:13:21 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:13:21 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:13:21 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:13:21 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 05:13:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:13:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:13:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:13:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:13:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:13:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:13:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:13:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:13:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:13:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:13:21 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:13:21 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:13:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:13:21 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:13:21 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-27 05:13:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:13:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:13:22 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 05:13:22 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:13:22 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:13:22 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:13:22 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:13:22 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 05:13:23 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 05:13:23 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:13:23 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:13:23 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:13:23 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:13:23 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 05:13:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:13:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:13:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:13:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:13:23 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:13:23 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:13:23 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:13:23 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:13:23 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:13:23 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:13:23 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:13:23 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:13:23 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:13:23 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:13:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=991 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:13:23 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:13:23 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:13:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=991 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:13:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=991 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:13:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=991 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:13:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=992 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:13:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=992 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:13:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=992 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:13:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=992 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:13:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=992 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:13:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=992 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:13:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=992 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:13:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=992 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:13:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=993 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:13:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=993 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:13:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=993 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:13:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=993 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:13:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=993 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:13:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=993 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:13:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=993 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:13:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=993 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:13:28 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:13:28 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:13:28 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:13:28 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:13:28 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:13:28 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:13:28 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:13:28 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:13:28 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:13:28 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:13:28 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:13:28 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:13:28 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:13:28 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:13:28 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:13:28 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:13:28 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:13:28 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:13:28 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:13:28 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:13:28 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:13:28 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:13:28 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:13:28 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:13:28 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:13:28 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:13:28 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:13:28 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:13:28 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:13:28 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:13:28 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:13:28 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:13:28 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:13:28 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:13:28 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:13:28 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:13:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:13:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:13:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:13:28 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:13:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:13:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:13:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:13:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:13:28 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:13:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:13:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:13:28 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:13:28 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:13:28 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:13:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:13:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:13:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:13:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:13:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:13:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:13:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:13:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:13:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:13:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:13:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:13:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:13:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:13:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:13:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:13:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:13:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:13:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:13:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:13:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:13:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:13:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:13:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:13:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:13:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:13:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:13:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:13:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:13:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:13:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:13:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:13:28 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:13:29 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:13:29 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:13:29 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:13:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:13:29 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:13:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:13:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:13:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:13:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:13:29 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:13:29 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:13:29 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:13:29 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:13:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:13:29 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:13:29 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:13:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:13:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:13:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:13:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:13:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:13:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:13:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:13:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:13:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:13:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:13:29 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:13:29 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:13:29 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:13:29 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:13:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:13:29 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:13:29 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-27 05:13:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:13:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:13:29 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:13:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:13:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:13:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:13:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:13:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:13:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:13:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:13:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:13:30 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:13:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:13:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:13:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:13:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:13:30 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:13:30 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:13:30 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:13:30 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:13:30 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 05:13:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:13:30 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:13:30 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:13:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:13:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:13:30 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 05:13:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:13:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:13:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:13:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:13:31 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 05:13:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:13:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:13:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:13:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:13:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:13:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:13:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:13:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:13:31 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:13:31 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:13:31 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:13:31 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:13:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:13:31 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:13:31 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-27 05:13:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:13:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:13:31 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 05:13:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:13:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:13:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:13:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:13:32 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 05:13:32 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 05:13:32 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:13:32 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:13:32 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:13:32 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:13:33 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 05:13:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:13:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:13:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:13:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:13:33 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:13:33 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:13:33 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:13:33 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:13:33 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:13:33 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:13:33 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:13:33 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:13:33 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:13:33 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:13:33 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=991 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:13:33 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:13:33 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:13:33 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=991 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:13:33 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=991 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:13:33 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=991 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:13:33 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=991 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:13:33 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=991 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:13:33 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=992 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:13:33 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=992 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:13:33 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=992 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:13:33 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=992 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:13:33 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=992 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:13:33 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=992 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:13:33 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=992 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:13:33 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=992 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:13:38 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:13:38 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:13:38 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:13:38 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:13:38 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:13:38 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:13:38 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:13:38 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:13:38 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:13:38 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:13:38 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:13:38 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:13:38 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:13:38 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:13:38 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:13:38 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:13:38 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:13:38 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:13:38 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:13:38 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:13:38 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:13:38 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:13:38 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:13:38 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:13:38 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:13:38 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:13:38 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:13:38 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:13:38 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:13:38 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:13:38 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:13:38 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:13:38 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:13:38 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:13:38 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:13:38 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:13:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:13:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:13:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:13:38 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:13:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:13:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:13:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:13:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:13:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:13:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:13:38 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:13:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:13:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:13:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:13:38 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:13:38 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:13:38 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:13:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:13:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:13:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:13:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:13:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:13:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:13:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:13:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:13:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:13:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:13:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:13:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:13:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:13:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:13:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:13:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:13:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:13:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:13:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:13:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:13:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:13:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:13:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:13:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:13:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:13:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:13:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:13:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:13:38 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:13:39 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:13:39 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:13:39 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:13:39 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:13:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:13:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:13:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:13:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:13:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:13:39 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:13:39 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:13:39 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:13:39 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:13:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:13:39 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:13:39 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:13:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:13:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:13:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:13:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:13:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:13:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:13:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:13:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:13:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:13:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:13:39 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:13:39 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:13:39 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:13:39 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:13:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:13:39 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:13:39 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:13:39 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-27 05:13:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:13:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:13:39 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:13:39 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:13:39 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:13:39 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:13:40 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 05:13:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:13:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:13:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:13:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:13:40 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:13:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:13:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:13:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:13:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:13:40 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:13:40 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:13:40 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:13:40 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:13:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:13:40 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:13:40 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:13:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:13:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:13:40 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 05:13:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:13:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:13:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:13:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:13:41 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 05:13:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:13:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:13:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:13:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:13:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:13:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:13:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:13:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:13:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:13:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:13:41 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:13:41 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:13:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:13:41 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:13:41 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-27 05:13:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:13:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:13:41 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 05:13:41 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:13:41 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:13:41 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:13:41 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:13:41 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 05:13:42 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 05:13:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:13:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:13:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:13:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:13:42 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 05:13:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:13:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:13:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:13:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:13:43 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:13:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:13:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:13:43 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:13:43 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:13:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:13:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:13:43 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:13:43 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:13:43 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:13:43 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:13:43 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:13:43 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=991 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:13:43 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=991 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:13:43 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=991 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:13:43 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=991 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:13:43 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=991 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:13:43 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=991 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:13:48 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:13:48 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:13:48 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:13:48 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:13:48 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:13:48 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:13:48 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:13:48 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:13:48 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:13:48 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:13:48 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:13:48 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:13:48 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:13:48 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:13:48 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:13:48 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:13:48 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:13:48 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:13:48 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:13:48 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:13:48 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:13:48 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:13:48 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:13:48 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:13:48 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:13:48 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:13:48 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:13:48 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:13:48 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:13:48 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:13:48 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:13:48 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:13:48 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:13:48 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:13:48 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:13:48 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:13:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:13:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:13:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:13:48 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:13:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:13:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:13:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:13:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:13:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:13:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:13:48 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:13:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:13:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:13:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:13:48 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:13:48 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:13:48 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:13:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:13:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:13:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:13:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:13:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:13:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:13:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:13:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:13:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:13:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:13:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:13:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:13:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:13:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:13:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:13:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:13:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:13:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:13:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:13:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:13:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:13:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:13:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:13:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:13:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:13:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:13:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:13:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:13:48 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:13:48 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:13:48 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:13:48 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:13:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:13:48 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:13:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:13:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:13:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:13:48 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:13:48 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:13:48 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:13:48 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:13:48 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:13:48 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:13:48 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:13:48 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:13:48 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:13:48 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:13:48 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:13:48 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=122 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:13:48 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=122 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:13:48 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=122 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:13:48 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=122 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:13:48 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=122 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:13:48 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=122 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:13:48 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=122 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:13:53 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:13:53 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:13:53 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:13:53 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:13:53 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:13:53 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:13:53 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:13:53 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:13:53 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:13:53 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:13:53 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:13:53 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:13:53 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:13:53 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:13:53 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:13:53 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:13:53 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:13:53 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:13:53 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:13:53 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:13:53 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:13:53 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:13:53 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:13:53 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:13:53 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:13:53 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:13:53 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:13:53 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:13:53 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:13:53 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:13:53 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:13:53 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:13:53 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:13:53 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:13:53 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:13:53 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:13:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:13:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:13:53 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:13:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:13:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:13:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:13:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:13:53 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:13:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:13:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:13:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:13:53 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:13:53 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:13:53 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:13:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:13:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:13:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:13:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:13:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:13:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:13:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:13:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:13:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:13:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:13:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:13:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:13:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:13:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:13:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:13:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:13:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:13:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:13:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:13:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:13:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:13:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:13:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:13:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:13:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:13:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:13:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:13:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:13:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:13:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:13:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:13:53 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:13:54 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:13:54 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:13:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:13:54 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:13:54 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:13:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:13:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:13:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:13:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:13:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:13:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:13:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:13:54 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:13:54 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:13:54 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:13:54 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:13:54 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:13:54 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:13:54 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:13:54 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:13:54 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:13:54 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:13:54 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:13:59 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:13:59 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:13:59 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:13:59 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:13:59 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:13:59 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:13:59 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:13:59 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:13:59 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:13:59 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:13:59 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:13:59 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:13:59 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:13:59 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:13:59 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:13:59 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:13:59 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:13:59 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:13:59 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:13:59 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:13:59 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:13:59 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:13:59 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:13:59 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:13:59 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:13:59 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:13:59 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:13:59 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:13:59 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:13:59 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:13:59 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:13:59 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:13:59 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:13:59 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:13:59 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:13:59 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:13:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:13:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:13:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:13:59 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:13:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:13:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:13:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:13:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:13:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:13:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:13:59 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:13:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:13:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:13:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:13:59 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:13:59 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:13:59 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:13:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:13:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:13:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:13:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:13:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:13:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:13:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:13:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:13:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:13:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:13:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:13:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:13:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:13:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:13:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:13:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:13:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:13:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:13:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:13:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:13:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:13:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:13:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:13:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:13:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:13:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:13:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:13:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:13:59 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:14:00 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:14:00 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:14:00 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:14:00 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:14:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:14:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:14:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:14:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:14:00 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:14:00 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:14:00 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:14:00 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:14:00 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:14:00 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:14:00 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:14:00 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:14:00 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:14:00 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:14:00 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=121 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:14:00 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:14:00 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=121 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:14:00 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=121 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:14:00 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=121 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:14:00 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=121 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:14:00 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=121 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:14:00 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=121 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:14:00 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=122 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:14:00 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=122 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:14:00 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=122 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:14:00 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=122 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:14:00 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=122 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:14:00 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=122 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:14:00 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=122 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:14:00 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=122 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:14:05 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:14:05 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:14:05 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:14:05 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:14:05 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:14:05 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:14:05 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:14:05 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:14:05 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:14:05 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:14:05 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:14:05 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:14:05 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:14:05 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:14:05 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:14:05 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:14:05 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:14:05 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:14:05 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:14:05 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:14:05 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:14:05 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:14:05 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:14:05 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:14:05 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:14:05 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:14:05 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:14:05 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:14:05 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:14:05 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:14:05 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:14:05 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:14:05 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:14:05 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:14:05 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:14:05 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:14:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:14:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:14:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:14:05 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:14:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:14:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:14:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:14:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:14:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:14:05 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:14:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:14:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:14:05 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:14:05 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:14:05 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:14:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:14:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:14:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:14:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:14:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:14:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:14:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:14:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:14:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:14:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:14:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:14:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:14:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:14:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:14:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:14:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:14:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:14:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:14:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:14:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:14:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:14:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:14:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:14:05 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:14:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:14:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:14:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:14:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:14:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:14:05 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:14:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:14:05 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:14:05 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:14:05 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:14:05 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:14:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:14:10 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:14:10 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:14:10 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:14:10 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:14:10 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:14:10 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:14:10 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:14:10 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:14:10 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:14:10 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:14:10 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:14:10 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:14:10 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:14:10 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:14:10 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:14:10 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:14:10 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:14:10 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:14:10 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:14:10 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:14:10 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:14:10 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:14:10 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:14:10 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:14:10 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:14:10 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:14:10 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:14:10 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:14:10 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:14:10 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:14:10 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:14:10 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:14:10 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:14:10 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:14:10 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:14:10 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:14:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:14:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:14:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:14:10 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:14:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:14:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:14:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:14:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:14:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:14:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:14:10 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:14:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:14:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:14:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:14:10 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:14:10 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:14:10 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:14:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:14:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:14:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:14:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:14:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:14:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:14:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:14:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:14:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:14:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:14:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:14:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:14:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:14:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:14:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:14:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:14:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:14:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:14:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:14:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:14:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:14:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:14:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:14:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:14:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:14:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:14:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:14:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:14:10 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:14:10 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:14:10 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:14:10 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:14:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:14:10 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:14:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:14:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:14:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:14:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:14:10 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:14:10 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:14:10 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:14:10 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:14:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:14:10 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:14:10 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:14:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:14:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:14:11 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:14:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:14:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:14:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:14:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:14:11 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 05:14:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:14:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:14:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:14:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:14:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:14:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:14:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:14:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:14:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:14:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:14:11 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:14:11 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:14:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:14:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:14:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:14:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:14:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:14:12 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 05:14:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:14:12 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:14:12 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:14:12 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:14:12 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 05:14:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:14:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:14:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:14:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:14:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:14:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:14:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:14:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:14:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:14:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:14:12 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:14:12 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:14:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:14:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:14:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:14:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:14:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:14:13 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 05:14:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:14:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:14:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:14:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:14:13 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 05:14:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:14:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:14:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:14:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:14:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:14:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:14:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:14:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:14:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:14:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:14:13 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:14:13 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:14:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:14:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:14:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:14:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:14:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:14:14 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 05:14:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:14:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:14:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:14:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:14:14 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 05:14:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:14:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:14:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:14:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:14:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:14:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:14:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:14:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:14:14 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:14:14 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:14:14 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:14:14 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:14:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:14:14 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:14:14 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:14:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:14:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:14:14 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 05:14:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:14:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:14:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:14:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:14:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:14:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:14:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:14:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:14:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:14:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:14:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:14:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:14:15 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:14:15 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:14:15 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:14:15 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:14:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:14:15 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:14:15 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2025-04-27 05:14:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:14:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:14:15 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 05:14:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:14:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:14:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:14:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:14:15 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:14:15 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 05:14:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:14:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:14:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:14:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:14:15 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:14:15 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:14:15 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:14:15 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:14:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:14:16 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:14:16 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=3, maio=3, ma_len=4
2025-04-27 05:14:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:14:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:14:16 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 05:14:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:14:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:14:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:14:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:14:16 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:14:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:14:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:14:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:14:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:14:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:14:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:14:16 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:14:16 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:14:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:14:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:14:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:14:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:14:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:14:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:14:16 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 05:14:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:14:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:14:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:14:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:14:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:14:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:14:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:14:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:14:17 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:14:17 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:14:17 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:14:17 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:14:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:14:17 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:14:17 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:14:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:14:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:14:17 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 05:14:17 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 05:14:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:14:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:14:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:14:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:14:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:14:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:14:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:14:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:14:17 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:14:17 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:14:17 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:14:17 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:14:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:14:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:14:17 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:14:17 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:14:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:14:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:14:18 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 05:14:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:14:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:14:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:14:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:14:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:14:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:14:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:14:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:14:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:14:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:14:18 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:14:18 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:14:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:14:18 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:14:18 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-27 05:14:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:14:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:14:18 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 05:14:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:14:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:14:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:14:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:14:19 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:14:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:14:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:14:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:14:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:14:19 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:14:19 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:14:19 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:14:19 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:14:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:14:19 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:14:19 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-27 05:14:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:14:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:14:19 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 05:14:19 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 05:14:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:14:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:14:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:14:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:14:19 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:14:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:14:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:14:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:14:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:14:19 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:14:19 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:14:19 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:14:19 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:14:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:14:19 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:14:19 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-27 05:14:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:14:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:14:20 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 05:14:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:14:20 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 05:14:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:14:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:14:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:14:20 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:14:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:14:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:14:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:14:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:14:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:14:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:14:20 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:14:20 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:14:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:14:20 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:14:20 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-27 05:14:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:14:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:14:21 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-27 05:14:21 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-27 05:14:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:14:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:14:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:14:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:14:21 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:14:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:14:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:14:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:14:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:14:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:14:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:14:21 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:14:21 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:14:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:14:21 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:14:21 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-27 05:14:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:14:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:14:22 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-27 05:14:22 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-27 05:14:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:14:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:14:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:14:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:14:22 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:14:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:14:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:14:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:14:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:14:22 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:14:22 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:14:22 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:14:22 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:14:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:14:22 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:14:22 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-27 05:14:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:14:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:14:23 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-27 05:14:23 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-27 05:14:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:14:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:14:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:14:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:14:23 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:14:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:14:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:14:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:14:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:14:23 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:14:23 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:14:23 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:14:23 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:14:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:14:23 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:14:23 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-27 05:14:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:14:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:14:24 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-27 05:14:24 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-27 05:14:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:14:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:14:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:14:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:14:24 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:14:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:14:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:14:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:14:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:14:24 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:14:24 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:14:24 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:14:24 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:14:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:14:24 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:14:24 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-27 05:14:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:14:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:14:25 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-27 05:14:25 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-27 05:14:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:14:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:14:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:14:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:14:25 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:14:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:14:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:14:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:14:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:14:25 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:14:25 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:14:25 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:14:25 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:14:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:14:25 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:14:25 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-27 05:14:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:14:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:14:25 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-27 05:14:26 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-27 05:14:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:14:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:14:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:14:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:14:26 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:14:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:14:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:14:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:14:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:14:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:14:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:14:26 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:14:26 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:14:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:14:26 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:14:26 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-27 05:14:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:14:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:14:26 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-27 05:14:27 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-27 05:14:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:14:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:14:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:14:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:14:27 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:14:27 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:14:27 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:14:27 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:14:27 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:14:27 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:14:27 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:14:27 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:14:27 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:14:27 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:14:27 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:14:27 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:14:27 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3707 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:14:27 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3707 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:14:27 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3707 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:14:27 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3707 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:14:27 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3707 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:14:27 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3707 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:14:27 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3707 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:14:32 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:14:32 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:14:32 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:14:32 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:14:32 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:14:32 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:14:32 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:14:32 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:14:32 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:14:32 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:14:32 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:14:32 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:14:32 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:14:32 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:14:32 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:14:32 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:14:32 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:14:32 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:14:32 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:14:32 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:14:32 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:14:32 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:14:32 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:14:32 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:14:32 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:14:32 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:14:32 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:14:32 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:14:32 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:14:32 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:14:32 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:14:32 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:14:32 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:14:32 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:14:32 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:14:32 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:14:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:14:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:14:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:14:32 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:14:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:14:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:14:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:14:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:14:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:14:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:14:32 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:14:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:14:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:14:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:14:32 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:14:32 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:14:32 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:14:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:14:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:14:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:14:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:14:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:14:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:14:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:14:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:14:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:14:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:14:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:14:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:14:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:14:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:14:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:14:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:14:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:14:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:14:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:14:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:14:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:14:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:14:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:14:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:14:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:14:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:14:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:14:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:14:32 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:14:33 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:14:33 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:14:33 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:14:33 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:14:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:14:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:14:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:14:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:14:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:14:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:14:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:14:33 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:14:33 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:14:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:14:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:14:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:14:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:14:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:14:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:14:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:14:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:14:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:14:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:14:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:14:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:14:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:14:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:14:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:14:33 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:14:33 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:14:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:14:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:14:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:14:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:14:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:14:33 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:14:33 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:14:33 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:14:33 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:14:33 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:14:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:14:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:14:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:14:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:14:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:14:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:14:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:14:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:14:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:14:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:14:33 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:14:33 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:14:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:14:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:14:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:14:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:14:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:14:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:14:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:14:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:14:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:14:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:14:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:14:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:14:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:14:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:14:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:14:33 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:14:33 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:14:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:14:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:14:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:14:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:14:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:14:33 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 05:14:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:14:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:14:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:14:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:14:34 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:14:34 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:14:34 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:14:34 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:14:34 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:14:34 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:14:34 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:14:34 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:14:34 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:14:34 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:14:34 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:14:34 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=348 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:14:34 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=348 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:14:34 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=348 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:14:34 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=348 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:14:34 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=348 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:14:39 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:14:39 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:14:39 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:14:39 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:14:39 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:14:39 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:14:39 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:14:39 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:14:39 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:14:39 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:14:39 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:14:39 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:14:39 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:14:39 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:14:39 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:14:39 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:14:39 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:14:39 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:14:39 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:14:39 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:14:39 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:14:39 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:14:39 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:14:39 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:14:39 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:14:39 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:14:39 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:14:39 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:14:39 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:14:39 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:14:39 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:14:39 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:14:39 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:14:39 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:14:39 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:14:39 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:14:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:14:39 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:14:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:14:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:14:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:14:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:14:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:14:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:14:39 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:14:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:14:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:14:39 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:14:39 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:14:39 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:14:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:14:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:14:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:14:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:14:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:14:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:14:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:14:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:14:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:14:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:14:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:14:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:14:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:14:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:14:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:14:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:14:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:14:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:14:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:14:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:14:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:14:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:14:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:14:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:14:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:14:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:14:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:14:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:14:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:14:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:14:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:14:39 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:14:39 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:14:40 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:14:40 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 05:14:41 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 05:14:41 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 05:14:42 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 05:14:42 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 05:14:43 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 05:14:43 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 05:14:44 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 05:14:44 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 05:14:45 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 05:14:45 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 05:14:45 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 05:14:46 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 05:14:46 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 05:14:47 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 05:14:47 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 05:14:48 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 05:14:48 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 05:14:49 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 05:14:49 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 05:14:50 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-27 05:14:50 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-27 05:14:51 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-27 05:14:51 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-27 05:14:52 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-27 05:14:52 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-27 05:14:53 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-27 05:14:53 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-27 05:14:54 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-27 05:14:54 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-27 05:14:55 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-27 05:14:55 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-27 05:14:56 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-27 05:14:56 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-27 05:14:57 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-27 05:14:57 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-27 05:14:57 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2025-04-27 05:14:58 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2025-04-27 05:14:58 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2025-04-27 05:14:59 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2025-04-27 05:14:59 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2025-04-27 05:15:00 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2025-04-27 05:15:00 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2025-04-27 05:15:01 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2025-04-27 05:15:01 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2025-04-27 05:15:02 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2025-04-27 05:15:02 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2025-04-27 05:15:03 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2025-04-27 05:15:03 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:15:03 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:15:03 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:15:03 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:15:03 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:15:03 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:15:03 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:15:08 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:15:08 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:15:08 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:15:08 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:15:08 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:15:08 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:15:08 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:15:08 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:15:08 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:15:08 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:15:08 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:15:08 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:15:08 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:15:08 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:15:08 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:15:08 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:15:08 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:15:08 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:15:08 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:15:08 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:15:08 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:15:08 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:15:08 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:15:08 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:15:08 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:15:08 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:15:08 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:15:08 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:15:08 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:15:08 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:15:08 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:15:08 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:15:08 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:15:08 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:15:08 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:15:08 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:15:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:15:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:15:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:15:08 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:15:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:15:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:15:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:15:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:15:08 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:15:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:15:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:15:08 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:15:08 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:15:08 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:15:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:15:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:15:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:15:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:15:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:15:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:15:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:15:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:15:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:15:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:15:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:15:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:15:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:15:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:15:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:15:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:15:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:15:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:15:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:15:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:15:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:15:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:15:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:15:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:15:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:15:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:15:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:15:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:15:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:15:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:15:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:15:08 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:15:08 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:15:09 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:15:09 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 05:15:10 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 05:15:10 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 05:15:11 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 05:15:11 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 05:15:12 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 05:15:12 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 05:15:13 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 05:15:13 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 05:15:14 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 05:15:14 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 05:15:15 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 05:15:15 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 05:15:15 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 05:15:16 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 05:15:16 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 05:15:17 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 05:15:17 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 05:15:18 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 05:15:18 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 05:15:19 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-27 05:15:19 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-27 05:15:20 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-27 05:15:20 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-27 05:15:21 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-27 05:15:21 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-27 05:15:22 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-27 05:15:22 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-27 05:15:23 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-27 05:15:23 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-27 05:15:24 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-27 05:15:24 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-27 05:15:25 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-27 05:15:25 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-27 05:15:26 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-27 05:15:26 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-27 05:15:26 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2025-04-27 05:15:27 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2025-04-27 05:15:27 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2025-04-27 05:15:28 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2025-04-27 05:15:28 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2025-04-27 05:15:29 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2025-04-27 05:15:29 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2025-04-27 05:15:30 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2025-04-27 05:15:30 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2025-04-27 05:15:31 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2025-04-27 05:15:31 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2025-04-27 05:15:32 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2025-04-27 05:15:32 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2025-04-27 05:15:33 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2025-04-27 05:15:33 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2025-04-27 05:15:34 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2025-04-27 05:15:34 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2025-04-27 05:15:35 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2025-04-27 05:15:35 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2025-04-27 05:15:36 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2025-04-27 05:15:36 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2025-04-27 05:15:37 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2025-04-27 05:15:37 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2025-04-27 05:15:38 [DEBUG] clck_gen.py:102 IND CLOCK 6324
2025-04-27 05:15:38 [DEBUG] clck_gen.py:102 IND CLOCK 6426
2025-04-27 05:15:38 [DEBUG] clck_gen.py:102 IND CLOCK 6528
2025-04-27 05:15:39 [DEBUG] clck_gen.py:102 IND CLOCK 6630
2025-04-27 05:15:39 [DEBUG] clck_gen.py:102 IND CLOCK 6732
2025-04-27 05:15:40 [DEBUG] clck_gen.py:102 IND CLOCK 6834
2025-04-27 05:15:40 [DEBUG] clck_gen.py:102 IND CLOCK 6936
2025-04-27 05:15:41 [DEBUG] clck_gen.py:102 IND CLOCK 7038
2025-04-27 05:15:41 [DEBUG] clck_gen.py:102 IND CLOCK 7140
2025-04-27 05:15:42 [DEBUG] clck_gen.py:102 IND CLOCK 7242
2025-04-27 05:15:42 [DEBUG] clck_gen.py:102 IND CLOCK 7344
2025-04-27 05:15:43 [DEBUG] clck_gen.py:102 IND CLOCK 7446
2025-04-27 05:15:43 [DEBUG] clck_gen.py:102 IND CLOCK 7548
2025-04-27 05:15:44 [DEBUG] clck_gen.py:102 IND CLOCK 7650
2025-04-27 05:15:44 [DEBUG] clck_gen.py:102 IND CLOCK 7752
2025-04-27 05:15:45 [DEBUG] clck_gen.py:102 IND CLOCK 7854
2025-04-27 05:15:45 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:15:45 [DEBUG] clck_gen.py:102 IND CLOCK 7956
2025-04-27 05:15:46 [DEBUG] clck_gen.py:102 IND CLOCK 8058
2025-04-27 05:15:46 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:15:46 [DEBUG] clck_gen.py:102 IND CLOCK 8160
2025-04-27 05:15:47 [DEBUG] clck_gen.py:102 IND CLOCK 8262
2025-04-27 05:15:47 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:15:47 [DEBUG] clck_gen.py:102 IND CLOCK 8364
2025-04-27 05:15:48 [DEBUG] clck_gen.py:102 IND CLOCK 8466
2025-04-27 05:15:48 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:15:48 [DEBUG] clck_gen.py:102 IND CLOCK 8568
2025-04-27 05:15:48 [DEBUG] clck_gen.py:102 IND CLOCK 8670
2025-04-27 05:15:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:15:49 [DEBUG] clck_gen.py:102 IND CLOCK 8772
2025-04-27 05:15:49 [DEBUG] clck_gen.py:102 IND CLOCK 8874
2025-04-27 05:15:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:15:50 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:15:50 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:15:50 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:15:50 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:15:50 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:15:50 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:15:50 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:15:50 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=8961 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:15:50 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=8961 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:15:50 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=8961 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:15:55 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:15:55 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:15:55 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:15:55 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:15:55 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:15:55 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:15:55 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:15:55 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:15:55 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:15:55 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:15:55 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:15:55 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:15:55 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:15:55 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:15:55 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:15:55 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:15:55 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:15:55 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:15:55 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:15:55 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:15:55 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:15:55 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:15:55 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:15:55 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:15:55 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:15:55 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:15:55 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:15:55 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:15:55 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:15:55 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:15:55 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:15:55 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:15:55 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:15:55 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:15:55 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:15:55 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:15:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:15:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:15:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:15:55 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:15:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:15:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:15:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:15:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:15:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:15:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:15:55 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:15:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:15:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:15:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:15:55 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:15:55 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:15:55 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:15:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:15:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:15:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:15:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:15:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:15:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:15:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:15:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:15:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:15:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:15:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:15:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:15:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:15:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:15:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:15:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:15:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:15:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:15:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:15:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:15:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:15:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:15:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:15:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:15:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:15:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:15:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:15:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:15:55 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:15:55 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:15:55 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:15:55 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:15:55 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:15:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:15:55 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:15:55 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:15:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:15:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:15:55 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:15:55 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:15:55 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:15:55 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:15:55 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:15:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:15:55 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:15:55 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:15:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:15:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:15:56 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:15:56 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:15:56 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:15:56 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:15:56 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:15:56 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 05:15:57 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 05:15:57 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:15:57 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:15:57 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:15:57 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:15:57 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 05:15:58 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 05:15:58 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:15:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:15:58 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:15:58 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:15:58 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 05:15:59 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 05:15:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:15:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:15:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:15:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:15:59 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 05:16:00 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 05:16:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:16:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:16:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:16:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:16:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:16:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:16:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:16:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:16:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:16:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:16:00 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:16:00 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:16:00 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:16:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:16:00 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:16:00 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-27 05:16:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:16:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:16:00 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:16:00 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:16:00 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:16:00 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:16:00 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 05:16:01 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 05:16:01 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 05:16:02 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 05:16:02 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 05:16:03 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 05:16:03 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 05:16:03 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 05:16:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:16:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:16:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:16:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:16:04 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:16:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:16:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:16:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:16:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:16:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:16:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:16:04 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:16:04 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:16:04 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:16:04 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 05:16:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:16:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:16:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:16:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:16:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:16:04 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 05:16:05 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 05:16:05 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 05:16:06 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-27 05:16:06 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-27 05:16:07 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-27 05:16:07 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-27 05:16:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:16:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:16:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:16:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:16:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:16:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:16:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:16:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:16:08 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:16:08 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:16:08 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:16:08 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:16:08 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:16:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:16:08 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:16:08 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-27 05:16:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:16:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:16:08 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-27 05:16:08 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-27 05:16:09 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-27 05:16:09 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-27 05:16:10 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-27 05:16:10 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-27 05:16:11 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-27 05:16:11 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-27 05:16:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:16:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:16:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:16:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:16:11 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:16:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:16:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:16:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:16:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:16:11 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:16:11 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:16:11 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:16:11 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:16:11 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:16:11 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:16:11 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:16:11 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3558 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:16:11 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3558 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:16:11 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3558 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:16:11 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3558 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:16:11 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3558 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:16:11 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3558 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:16:16 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:16:16 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:16:16 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:16:16 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:16:16 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:16:16 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:16:16 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:16:16 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:16:16 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:16:16 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:16:16 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:16:17 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:16:17 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:16:17 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:16:17 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:16:17 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:16:17 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:16:17 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:16:17 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:16:17 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:16:17 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:16:17 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:16:17 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:16:17 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:16:17 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:16:17 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:16:17 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:16:17 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:16:17 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:16:17 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:16:17 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:16:17 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:16:17 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:16:17 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:16:17 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:16:17 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:16:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:16:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:16:17 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:16:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:16:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:16:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:16:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:16:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:16:17 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:16:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:16:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:16:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:16:17 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:16:17 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:16:17 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:16:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:16:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:16:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:16:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:16:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:16:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:16:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:16:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:16:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:16:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:16:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:16:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:16:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:16:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:16:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:16:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:16:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:16:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:16:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:16:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:16:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:16:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:16:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:16:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:16:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:16:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:16:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:16:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:16:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:16:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:16:17 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:16:17 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:16:17 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:16:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:16:17 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:16:17 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:16:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:16:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:16:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:16:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:16:17 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:16:17 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:16:17 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:16:17 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:16:17 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:16:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:16:17 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:16:17 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:16:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:16:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:16:17 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:16:18 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:16:18 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:16:18 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:16:18 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:16:18 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 05:16:18 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:16:18 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 05:16:18 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:16:19 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:16:19 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:16:19 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:16:19 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:16:19 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 05:16:19 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:16:19 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 05:16:19 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:16:20 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:16:20 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:16:20 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:16:20 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:16:20 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 05:16:20 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:16:20 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 05:16:20 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:16:21 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:16:21 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:16:21 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:16:21 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:16:21 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 05:16:21 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:16:21 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 05:16:21 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:16:22 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:16:22 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:16:22 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:16:22 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:16:22 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 05:16:22 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:16:22 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 05:16:22 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:16:23 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 05:16:23 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:16:23 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 05:16:23 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:16:24 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 05:16:24 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:16:24 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 05:16:24 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:16:25 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 05:16:25 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:16:25 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 05:16:25 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:16:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:16:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:16:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:16:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:16:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:16:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:16:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:16:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:16:25 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:16:25 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:16:25 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:16:25 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:16:25 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:16:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:16:25 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:16:25 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-27 05:16:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:16:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:16:26 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 05:16:26 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:16:26 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 05:16:26 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:16:27 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 05:16:27 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:16:27 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 05:16:27 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:16:27 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-27 05:16:28 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:16:28 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-27 05:16:28 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:16:28 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-27 05:16:29 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:16:29 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-27 05:16:29 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:16:29 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-27 05:16:30 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:16:30 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-27 05:16:30 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-27 05:16:30 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:16:31 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-27 05:16:31 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:16:31 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-27 05:16:31 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:16:32 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-27 05:16:32 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:16:32 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-27 05:16:32 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:16:33 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-27 05:16:33 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:16:33 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-27 05:16:33 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:16:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:16:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:16:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:16:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:16:33 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:16:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:16:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:16:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:16:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:16:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:16:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:16:33 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:16:33 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:16:33 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:16:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:16:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:16:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:16:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:16:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:16:34 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:16:34 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-27 05:16:34 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:16:34 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-27 05:16:35 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:16:35 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-27 05:16:35 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:16:35 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2025-04-27 05:16:36 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:16:36 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2025-04-27 05:16:36 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:16:36 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2025-04-27 05:16:37 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:16:37 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2025-04-27 05:16:37 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:16:37 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2025-04-27 05:16:37 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:16:38 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2025-04-27 05:16:38 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:16:38 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2025-04-27 05:16:38 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:16:38 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2025-04-27 05:16:39 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:16:39 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2025-04-27 05:16:39 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:16:39 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2025-04-27 05:16:40 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:16:40 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2025-04-27 05:16:40 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:16:40 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2025-04-27 05:16:41 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:16:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:16:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:16:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:16:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:16:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:16:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:16:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:16:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:16:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:16:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:16:41 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:16:41 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:16:41 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:16:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:16:41 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:16:41 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-27 05:16:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:16:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:16:41 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2025-04-27 05:16:41 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:16:41 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2025-04-27 05:16:42 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:16:42 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2025-04-27 05:16:42 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:16:42 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2025-04-27 05:16:43 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:16:43 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2025-04-27 05:16:43 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:16:43 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2025-04-27 05:16:44 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:16:44 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2025-04-27 05:16:44 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:16:44 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2025-04-27 05:16:45 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:16:45 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2025-04-27 05:16:45 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:16:45 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2025-04-27 05:16:46 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:16:46 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2025-04-27 05:16:46 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:16:46 [DEBUG] clck_gen.py:102 IND CLOCK 6324
2025-04-27 05:16:46 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:16:47 [DEBUG] clck_gen.py:102 IND CLOCK 6426
2025-04-27 05:16:47 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:16:47 [DEBUG] clck_gen.py:102 IND CLOCK 6528
2025-04-27 05:16:47 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:16:48 [DEBUG] clck_gen.py:102 IND CLOCK 6630
2025-04-27 05:16:48 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:16:48 [DEBUG] clck_gen.py:102 IND CLOCK 6732
2025-04-27 05:16:48 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:16:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:16:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:16:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:16:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:16:48 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:16:48 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:16:48 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:16:48 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:16:48 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:16:48 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:16:48 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:16:48 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:16:48 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:16:48 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:16:48 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:16:48 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=6821 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:16:48 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:16:48 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=6821 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:16:48 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=6821 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:16:48 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=6821 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:16:48 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=6821 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:16:48 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=6821 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:16:53 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:16:53 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:16:53 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:16:53 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:16:53 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:16:53 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:16:53 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:16:53 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:16:53 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:16:53 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:16:53 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:16:53 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:16:53 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:16:53 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:16:53 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:16:53 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:16:53 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:16:53 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:16:53 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:16:53 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:16:53 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:16:53 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:16:53 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:16:53 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:16:53 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:16:53 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:16:53 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:16:53 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:16:53 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:16:53 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:16:53 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:16:53 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:16:53 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:16:53 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:16:53 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:16:53 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:16:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:16:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:16:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:16:53 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:16:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:16:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:16:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:16:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:16:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:16:53 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:16:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:16:53 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:16:53 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:16:53 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:16:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:16:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:16:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:16:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:16:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:16:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:16:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:16:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:16:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:16:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:16:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:16:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:16:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:16:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:16:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:16:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:16:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:16:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:16:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:16:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:16:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:16:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:16:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:16:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:16:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:16:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:16:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:16:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:16:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:16:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:16:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:16:53 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:16:54 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:16:54 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:16:54 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:16:54 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:16:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:16:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:16:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:16:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:16:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:16:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:16:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:16:54 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:16:54 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:16:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:16:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:16:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:16:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:16:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:16:54 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:16:54 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:16:54 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:16:54 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:16:54 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:16:55 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 05:16:55 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 05:16:55 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:16:55 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:16:55 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:16:55 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:16:56 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 05:16:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:16:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:16:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:16:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:16:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:16:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:16:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:16:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:16:56 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:16:56 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:16:56 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:16:56 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:16:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:16:56 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:16:56 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:16:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:16:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:16:56 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 05:16:56 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:16:56 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:16:56 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:16:56 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:16:57 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 05:16:57 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 05:16:57 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:16:57 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:16:57 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:16:57 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:16:58 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 05:16:58 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 05:16:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:16:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:16:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:16:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:16:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:16:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:16:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:16:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:16:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:16:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:16:58 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:16:58 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:16:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:16:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:16:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:16:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:16:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:16:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:16:58 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:16:58 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:16:58 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:16:59 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 05:16:59 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 05:17:00 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 05:17:00 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 05:17:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:17:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:17:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:17:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:17:00 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:17:00 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:17:00 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:17:00 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:17:00 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:17:00 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:17:00 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:17:00 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:17:00 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:17:00 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:17:00 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:17:00 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1492 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:17:00 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1492 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:17:00 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1492 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:17:00 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1492 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:17:00 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1492 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:17:00 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1492 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:17:00 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1493 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:17:00 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1493 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:17:00 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1493 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:17:00 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1493 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:17:00 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1493 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:17:00 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1493 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:17:00 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1493 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:17:00 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1493 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:17:05 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:17:05 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:17:05 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:17:05 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:17:05 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:17:05 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:17:05 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:17:05 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:17:05 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:17:05 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:17:05 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:17:05 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:17:05 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:17:05 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:17:05 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:17:05 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:17:05 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:17:05 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:17:05 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:17:05 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:17:05 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:17:05 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:17:05 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:17:05 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:17:05 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:17:05 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:17:05 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:17:05 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:17:05 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:17:05 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:17:05 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:17:05 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:17:05 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:17:05 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:17:05 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:17:05 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:17:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:17:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:17:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:17:05 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:17:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:17:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:17:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:17:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:17:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:17:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:17:05 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:17:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:17:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:17:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:17:05 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:17:05 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:17:05 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:17:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:17:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:17:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:17:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:17:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:17:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:17:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:17:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:17:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:17:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:17:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:17:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:17:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:17:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:17:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:17:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:17:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:17:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:17:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:17:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:17:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:17:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:17:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:17:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:17:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:17:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:17:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:17:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:17:05 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:17:06 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:17:06 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:17:06 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:17:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:17:06 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:17:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:17:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:17:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:17:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:17:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:17:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:17:06 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:17:06 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:17:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:17:06 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:17:06 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-27 05:17:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:17:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:17:06 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:17:06 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:17:06 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:17:06 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:17:06 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:17:07 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 05:17:07 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 05:17:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:17:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:17:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:17:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:17:08 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 05:17:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:17:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:17:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:17:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:17:08 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:17:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:17:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:17:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:17:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:17:08 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:17:08 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:17:08 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:17:08 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:17:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:17:08 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:17:08 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-27 05:17:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:17:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:17:08 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 05:17:08 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:17:08 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:17:08 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:17:08 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:17:09 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 05:17:09 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 05:17:09 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:17:09 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:17:09 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:17:09 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:17:10 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 05:17:10 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 05:17:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:17:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:17:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:17:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:17:10 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:17:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:17:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:17:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:17:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:17:10 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:17:10 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:17:10 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:17:10 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:17:10 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:17:10 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:17:10 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:17:15 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:17:15 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:17:15 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:17:15 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:17:15 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:17:15 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:17:15 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:17:15 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:17:15 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:17:15 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:17:15 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:17:15 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:17:15 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:17:15 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:17:15 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:17:15 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:17:15 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:17:15 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:17:15 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:17:15 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:17:15 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:17:15 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:17:15 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:17:15 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:17:15 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:17:15 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:17:15 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:17:15 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:17:15 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:17:15 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:17:15 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:17:15 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:17:15 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:17:15 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:17:15 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:17:15 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:17:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:17:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:17:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:17:15 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:17:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:17:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:17:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:17:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:17:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:17:15 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:17:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:17:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:17:15 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:17:15 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:17:15 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:17:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:17:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:17:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:17:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:17:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:17:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:17:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:17:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:17:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:17:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:17:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:17:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:17:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:17:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:17:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:17:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:17:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:17:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:17:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:17:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:17:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:17:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:17:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:17:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:17:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:17:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:17:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:17:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:17:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:17:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:17:15 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:17:16 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:17:16 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:17:16 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:17:16 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:17:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:17:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:17:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:17:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:17:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:17:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:17:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:17:16 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:17:16 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:17:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:17:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:17:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:17:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:17:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:17:16 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:17:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:17:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:17:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:17:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:17:17 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 05:17:17 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 05:17:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:17:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:17:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:17:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:17:18 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 05:17:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:17:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:17:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:17:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:17:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:17:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:17:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:17:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:17:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:17:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:17:18 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:17:18 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:17:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:17:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:17:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:17:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:17:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:17:18 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 05:17:18 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:17:18 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:17:18 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:17:18 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:17:19 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 05:17:19 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 05:17:19 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:17:19 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:17:19 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:17:19 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:17:20 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 05:17:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:17:20 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 05:17:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:17:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:17:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:17:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:17:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:17:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:17:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:17:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:17:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:17:20 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:17:20 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:17:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:17:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:17:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:17:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:17:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:17:20 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:17:20 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:17:20 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:17:20 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:17:21 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 05:17:21 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 05:17:22 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 05:17:22 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 05:17:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:17:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:17:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:17:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:17:22 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:17:22 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:17:22 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:17:22 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:17:22 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:17:22 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:17:22 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:17:22 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:17:22 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1480 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:17:22 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:17:22 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:17:22 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:17:22 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1480 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:17:22 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1480 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:17:22 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1481 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:17:22 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1481 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:17:22 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1481 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:17:22 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1481 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:17:22 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1481 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:17:22 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1481 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:17:22 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1481 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:17:22 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1481 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:17:27 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:17:27 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:17:27 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:17:27 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:17:27 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:17:27 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:17:27 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:17:27 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:17:27 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:17:27 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:17:27 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:17:27 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:17:27 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:17:27 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:17:27 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:17:27 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:17:27 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:17:27 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:17:27 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:17:27 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:17:27 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:17:27 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:17:27 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:17:27 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:17:27 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:17:27 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:17:27 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:17:27 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:17:27 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:17:27 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:17:27 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:17:27 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:17:27 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:17:27 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:17:27 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:17:27 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:17:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:17:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:17:27 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:17:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:17:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:17:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:17:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:17:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:17:27 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:17:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:17:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:17:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:17:27 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:17:27 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:17:27 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:17:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:17:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:17:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:17:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:17:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:17:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:17:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:17:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:17:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:17:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:17:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:17:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:17:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:17:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:17:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:17:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:17:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:17:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:17:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:17:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:17:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:17:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:17:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:17:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:17:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:17:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:17:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:17:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:17:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:17:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:17:27 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:17:28 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:17:28 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:17:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:17:28 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:17:28 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:17:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:17:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:17:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:17:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:17:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:17:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:17:28 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:17:28 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:17:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:17:28 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:17:28 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-27 05:17:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:17:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:17:28 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:17:28 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:17:28 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:17:28 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:17:28 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:17:29 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 05:17:29 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 05:17:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:17:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:17:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:17:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:17:30 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 05:17:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:17:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:17:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:17:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:17:30 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:17:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:17:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:17:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:17:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:17:30 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:17:30 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:17:30 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:17:30 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:17:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:17:30 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:17:30 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-27 05:17:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:17:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:17:30 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 05:17:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:17:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:17:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:17:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:17:31 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 05:17:31 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 05:17:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:17:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:17:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:17:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:17:32 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 05:17:32 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 05:17:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:17:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:17:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:17:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:17:32 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:17:32 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:17:32 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:17:32 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:17:32 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:17:32 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:17:32 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:17:32 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:17:32 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:17:32 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:17:32 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:17:32 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:17:37 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:17:37 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:17:37 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:17:37 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:17:37 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:17:37 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:17:37 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:17:37 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:17:37 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:17:37 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:17:37 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:17:37 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:17:37 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:17:37 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:17:37 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:17:37 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:17:37 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:17:37 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:17:37 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:17:37 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:17:37 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:17:37 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:17:37 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:17:37 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:17:37 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:17:37 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:17:37 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:17:37 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:17:37 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:17:37 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:17:37 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:17:37 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:17:37 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:17:37 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:17:37 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:17:37 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:17:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:17:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:17:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:17:37 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:17:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:17:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:17:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:17:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:17:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:17:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:17:37 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:17:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:17:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:17:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:17:37 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:17:37 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:17:37 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:17:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:17:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:17:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:17:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:17:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:17:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:17:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:17:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:17:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:17:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:17:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:17:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:17:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:17:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:17:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:17:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:17:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:17:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:17:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:17:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:17:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:17:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:17:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:17:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:17:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:17:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:17:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:17:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:17:37 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:17:38 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:17:38 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:17:38 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:17:38 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:17:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:17:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:17:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:17:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:17:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:17:38 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:17:38 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:17:38 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:17:38 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:17:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:17:38 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:17:38 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:17:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:17:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:17:38 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:17:38 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:17:38 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:17:38 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:17:38 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:17:39 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 05:17:39 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 05:17:39 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:17:39 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:17:39 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:17:39 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:17:40 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 05:17:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:17:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:17:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:17:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:17:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:17:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:17:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:17:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:17:40 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:17:40 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:17:40 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:17:40 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:17:40 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:17:40 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:17:40 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:17:40 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=601 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:17:40 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=601 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:17:40 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=601 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:17:40 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=601 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:17:40 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=601 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:17:40 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=601 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:17:45 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:17:45 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:17:45 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:17:45 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:17:45 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:17:45 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:17:45 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:17:45 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:17:45 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:17:45 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:17:45 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:17:45 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:17:45 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:17:45 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:17:45 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:17:45 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:17:45 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:17:45 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:17:45 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:17:45 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:17:45 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:17:45 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:17:45 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:17:45 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:17:45 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:17:45 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:17:45 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:17:45 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:17:45 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:17:45 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:17:45 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:17:45 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:17:45 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:17:45 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:17:45 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:17:45 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:17:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:17:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:17:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:17:45 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:17:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:17:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:17:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:17:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:17:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:17:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:17:45 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:17:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:17:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:17:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:17:45 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:17:45 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:17:45 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:17:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:17:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:17:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:17:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:17:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:17:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:17:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:17:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:17:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:17:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:17:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:17:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:17:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:17:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:17:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:17:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:17:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:17:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:17:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:17:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:17:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:17:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:17:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:17:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:17:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:17:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:17:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:17:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:17:45 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:17:46 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:17:46 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:17:46 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:17:46 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:17:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:17:46 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:17:46 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:17:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:17:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:17:46 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:17:46 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:17:46 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:17:46 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:17:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:17:46 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:17:46 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-27 05:17:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:17:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:17:46 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:17:46 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:17:46 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:17:46 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:17:46 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:17:47 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 05:17:47 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 05:17:47 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:17:47 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:17:47 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:17:47 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:17:48 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 05:17:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:17:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:17:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:17:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:17:48 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:17:48 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:17:48 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:17:48 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:17:48 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:17:48 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:17:48 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:17:48 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:17:48 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:17:48 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=604 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:17:48 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:17:48 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:17:48 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:17:48 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=604 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:17:53 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:17:53 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:17:53 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:17:53 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:17:53 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:17:53 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:17:53 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:17:53 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:17:53 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:17:53 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:17:53 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:17:53 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:17:53 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:17:53 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:17:53 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:17:53 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:17:53 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:17:53 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:17:53 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:17:53 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:17:53 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:17:53 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:17:53 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:17:53 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:17:53 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:17:53 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:17:53 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:17:53 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:17:53 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:17:53 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:17:53 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:17:53 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:17:53 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:17:53 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:17:53 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:17:53 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:17:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:17:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:17:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:17:53 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:17:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:17:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:17:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:17:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:17:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:17:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:17:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:17:53 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:17:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:17:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:17:53 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:17:53 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:17:53 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:17:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:17:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:17:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:17:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:17:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:17:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:17:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:17:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:17:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:17:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:17:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:17:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:17:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:17:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:17:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:17:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:17:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:17:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:17:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:17:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:17:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:17:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:17:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:17:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:17:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:17:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:17:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:17:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:17:53 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:17:53 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:17:53 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:17:53 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:17:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:17:53 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:17:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:17:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:17:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:17:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:17:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:17:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:17:54 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:17:54 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:17:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:17:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:17:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:17:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:17:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:17:54 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:17:54 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:17:54 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:17:54 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:17:54 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:17:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:17:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:17:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:17:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:17:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:17:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:17:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:17:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:17:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:17:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:17:54 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:17:54 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:17:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:17:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:17:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:17:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:17:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:17:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:17:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:17:54 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 05:17:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:17:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:17:54 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:17:54 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:17:54 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:17:54 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:17:54 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:17:54 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:17:54 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:17:54 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:17:54 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:17:54 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:17:54 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:17:59 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:17:59 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:17:59 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:17:59 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:17:59 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:17:59 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:17:59 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:17:59 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:17:59 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:17:59 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:17:59 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:17:59 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:17:59 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:17:59 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:17:59 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:17:59 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:17:59 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:17:59 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:17:59 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:17:59 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:17:59 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:17:59 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:17:59 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:17:59 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:17:59 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:17:59 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:17:59 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:17:59 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:17:59 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:17:59 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:17:59 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:17:59 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:17:59 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:17:59 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:17:59 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:17:59 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:17:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:17:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:17:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:17:59 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:17:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:17:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:17:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:17:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:17:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:17:59 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:17:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:17:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:17:59 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:17:59 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:17:59 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:17:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:17:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:17:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:17:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:17:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:17:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:17:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:17:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:17:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:17:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:17:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:17:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:17:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:17:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:17:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:17:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:17:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:17:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:17:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:17:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:17:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:17:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:17:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:17:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:17:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:17:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:17:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:17:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:17:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:17:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:17:59 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:18:00 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:18:00 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:18:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:18:00 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:18:00 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:18:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:18:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:18:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:18:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:18:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:18:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:18:00 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:18:00 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:18:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:18:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:18:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:18:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:18:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:18:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:18:00 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:18:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:18:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:18:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:18:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:18:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:18:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:18:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:18:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:18:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:18:00 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:18:00 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:18:00 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:18:00 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:18:00 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:18:00 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:18:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:18:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:18:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:18:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:18:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:18:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:18:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:18:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:18:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:18:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:18:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:18:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:18:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:18:01 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:18:01 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:18:01 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:18:01 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:18:01 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:18:01 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=297 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:18:01 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:18:01 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:18:01 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=298 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:18:01 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=298 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:18:01 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=298 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:18:01 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=298 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:18:01 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=298 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:18:01 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=298 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:18:01 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=298 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:18:01 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=298 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:18:06 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:18:06 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:18:06 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:18:06 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:18:06 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:18:06 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:18:06 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:18:06 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:18:06 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:18:06 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:18:06 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:18:06 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:18:06 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:18:06 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:18:06 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:18:06 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:18:06 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:18:06 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:18:06 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:18:06 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:18:06 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:18:06 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:18:06 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:18:06 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:18:06 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:18:06 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:18:06 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:18:06 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:18:06 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:18:06 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:18:06 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:18:06 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:18:06 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:18:06 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:18:06 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:18:06 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:18:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:18:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:18:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:18:06 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:18:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:18:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:18:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:18:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:18:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:18:06 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:18:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:18:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:18:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:18:06 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:18:06 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:18:06 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:18:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:18:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:18:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:18:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:18:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:18:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:18:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:18:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:18:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:18:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:18:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:18:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:18:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:18:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:18:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:18:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:18:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:18:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:18:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:18:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:18:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:18:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:18:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:18:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:18:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:18:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:18:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:18:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:18:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:18:06 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:18:06 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:18:06 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:18:06 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:18:06 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:18:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:18:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:18:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:18:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:18:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:18:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:18:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:18:06 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:18:06 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:18:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:18:07 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:18:07 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:18:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:18:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:18:07 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:18:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:18:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:18:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:18:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:18:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:18:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:18:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:18:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:18:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:18:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:18:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:18:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:18:07 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:18:07 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:18:07 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:18:07 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:18:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:18:07 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:18:07 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:18:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:18:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:18:07 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 05:18:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:18:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:18:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:18:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:18:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:18:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:18:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:18:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:18:07 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:18:07 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:18:07 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:18:07 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:18:07 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:18:07 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=318 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:18:07 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:18:07 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:18:07 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=318 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:18:07 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=318 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:18:07 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=319 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:18:07 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=319 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:18:07 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=319 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:18:07 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=319 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:18:07 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=319 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:18:07 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=319 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:18:07 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=319 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:18:07 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=319 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:18:12 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:18:12 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:18:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:18:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:18:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:18:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:18:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:18:12 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:18:12 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:18:12 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:18:12 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:18:12 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:18:12 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:18:12 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:18:12 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:18:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:18:12 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:18:12 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:18:12 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:18:12 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:18:12 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:18:12 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:18:12 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:18:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:18:12 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:18:12 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:18:12 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:18:12 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:18:12 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:18:12 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:18:12 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:18:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:18:12 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:18:12 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:18:12 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:18:12 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:18:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:18:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:18:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:18:12 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:18:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:18:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:18:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:18:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:18:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:18:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:18:12 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:18:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:18:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:18:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:18:12 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:18:12 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:18:12 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:18:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:18:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:18:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:18:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:18:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:18:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:18:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:18:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:18:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:18:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:18:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:18:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:18:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:18:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:18:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:18:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:18:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:18:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:18:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:18:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:18:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:18:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:18:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:18:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:18:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:18:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:18:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:18:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:18:12 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:18:13 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:18:13 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:18:13 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:18:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:18:13 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:18:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:18:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:18:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:18:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:18:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:18:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:18:13 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:18:13 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:18:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:18:13 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:18:13 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-27 05:18:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:18:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:18:13 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:18:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:18:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:18:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:18:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:18:14 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 05:18:14 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 05:18:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:18:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:18:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:18:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:18:15 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 05:18:15 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 05:18:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:18:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:18:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:18:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:18:16 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 05:18:16 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 05:18:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:18:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:18:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:18:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:18:17 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 05:18:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:18:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:18:17 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:18:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:18:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:18:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:18:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:18:17 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:18:17 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:18:17 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:18:17 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:18:17 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:18:17 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:18:17 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:18:22 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:18:22 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:18:22 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:18:22 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:18:22 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:18:22 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:18:22 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:18:22 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:18:22 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:18:22 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:18:22 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:18:22 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:18:22 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:18:22 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:18:22 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:18:22 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:18:22 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:18:22 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:18:22 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:18:22 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:18:22 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:18:22 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:18:22 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:18:22 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:18:22 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:18:22 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:18:22 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:18:22 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:18:22 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:18:22 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:18:22 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:18:22 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:18:22 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:18:22 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:18:22 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:18:22 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:18:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:18:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:18:22 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:18:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:18:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:18:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:18:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:18:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:18:22 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:18:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:18:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:18:22 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:18:22 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:18:22 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:18:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:18:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:18:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:18:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:18:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:18:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:18:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:18:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:18:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:18:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:18:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:18:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:18:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:18:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:18:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:18:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:18:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:18:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:18:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:18:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:18:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:18:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:18:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:18:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:18:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:18:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:18:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:18:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:18:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:18:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:18:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:18:22 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:18:23 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:18:23 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:18:23 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:18:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:18:23 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:18:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:18:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:18:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:18:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:18:23 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:18:23 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:18:23 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:18:23 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:18:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:18:23 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:18:23 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:18:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:18:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:18:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:18:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:18:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:18:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:18:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:18:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:18:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:18:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:18:23 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:18:23 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:18:23 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:18:23 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:18:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:18:23 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:18:23 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:18:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:18:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:18:23 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:18:23 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:18:23 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:18:23 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:18:23 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:18:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:18:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:18:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:18:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:18:23 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:18:23 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:18:23 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:18:23 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:18:23 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:18:23 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:18:23 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:18:23 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:18:23 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:18:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=245 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:18:23 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:18:23 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:18:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=245 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:18:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=245 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:18:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=245 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:18:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=245 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:18:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=245 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:18:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=246 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:18:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=246 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:18:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=246 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:18:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=246 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:18:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=246 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:18:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=246 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:18:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=246 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:18:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=246 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:18:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=247 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:18:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=247 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:18:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=247 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:18:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=247 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:18:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=247 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:18:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=247 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:18:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=247 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:18:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=247 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:18:28 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:18:28 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:18:28 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:18:28 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:18:28 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:18:28 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:18:28 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:18:28 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:18:28 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:18:28 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:18:28 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:18:28 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:18:28 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:18:28 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:18:28 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:18:28 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:18:28 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:18:28 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:18:28 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:18:28 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:18:28 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:18:28 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:18:28 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:18:28 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:18:28 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:18:28 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:18:28 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:18:28 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:18:28 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:18:28 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:18:28 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:18:28 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:18:28 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:18:28 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:18:28 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:18:28 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:18:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:18:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:18:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:18:28 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:18:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:18:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:18:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:18:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:18:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:18:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:18:28 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:18:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:18:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:18:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:18:28 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:18:28 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:18:28 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:18:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:18:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:18:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:18:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:18:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:18:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:18:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:18:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:18:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:18:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:18:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:18:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:18:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:18:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:18:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:18:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:18:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:18:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:18:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:18:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:18:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:18:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:18:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:18:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:18:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:18:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:18:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:18:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:18:28 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:18:29 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:18:29 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:18:29 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:18:29 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:18:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:18:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:18:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:18:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:18:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:18:29 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:18:29 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:18:29 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:18:29 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:18:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:18:29 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:18:29 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-27 05:18:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:18:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:18:29 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:18:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:18:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:18:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:18:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:18:30 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 05:18:30 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 05:18:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:18:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:18:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:18:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:18:31 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 05:18:31 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 05:18:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:18:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:18:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:18:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:18:32 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 05:18:32 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 05:18:32 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:18:32 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:18:32 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:18:32 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:18:33 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 05:18:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:18:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:18:33 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:18:33 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:18:33 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:18:33 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:18:33 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:18:33 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:18:33 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:18:33 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:18:33 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:18:33 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:18:33 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:18:33 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:18:33 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=983 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:18:33 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=983 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:18:33 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=983 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:18:33 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=983 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:18:38 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:18:38 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:18:38 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:18:38 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:18:38 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:18:38 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:18:38 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:18:38 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:18:38 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:18:38 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:18:38 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:18:38 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:18:38 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:18:38 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:18:38 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:18:38 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:18:38 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:18:38 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:18:38 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:18:38 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:18:38 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:18:38 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:18:38 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:18:38 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:18:38 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:18:38 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:18:38 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:18:38 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:18:38 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:18:38 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:18:38 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:18:38 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:18:38 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:18:38 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:18:38 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:18:38 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:18:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:18:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:18:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:18:38 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:18:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:18:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:18:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:18:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:18:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:18:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:18:38 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:18:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:18:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:18:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:18:38 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:18:38 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:18:38 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:18:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:18:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:18:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:18:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:18:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:18:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:18:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:18:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:18:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:18:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:18:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:18:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:18:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:18:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:18:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:18:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:18:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:18:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:18:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:18:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:18:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:18:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:18:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:18:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:18:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:18:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:18:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:18:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:18:38 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:18:38 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:18:38 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:18:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:18:38 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:18:38 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:18:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:18:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:18:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:18:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:18:38 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:18:38 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:18:38 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:18:38 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:18:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:18:39 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:18:39 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:18:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:18:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:18:39 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:18:39 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:18:39 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:18:39 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:18:39 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:18:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:18:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:18:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:18:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:18:39 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:18:39 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:18:39 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:18:39 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:18:39 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:18:39 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:18:39 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:18:39 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:18:39 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=293 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:18:39 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:18:39 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:18:39 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:18:39 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=293 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:18:39 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=293 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:18:39 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=294 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:18:39 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=294 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:18:39 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=294 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:18:39 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=294 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:18:39 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=294 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:18:39 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=294 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:18:39 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=294 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:18:39 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=294 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:18:39 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=295 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:18:39 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=295 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:18:39 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=295 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:18:39 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=295 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:18:39 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=295 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:18:39 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=295 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:18:39 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=295 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:18:39 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=295 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:18:44 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:18:44 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:18:44 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:18:44 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:18:44 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:18:44 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:18:44 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:18:44 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:18:44 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:18:44 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:18:44 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:18:44 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:18:44 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:18:44 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:18:44 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:18:44 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:18:44 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:18:44 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:18:44 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:18:44 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:18:44 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:18:44 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:18:44 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:18:44 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:18:44 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:18:44 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:18:44 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:18:44 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:18:44 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:18:44 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:18:44 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:18:44 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:18:44 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:18:44 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:18:44 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:18:44 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:18:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:18:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:18:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:18:44 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:18:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:18:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:18:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:18:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:18:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:18:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:18:44 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:18:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:18:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:18:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:18:44 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:18:44 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:18:44 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:18:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:18:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:18:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:18:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:18:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:18:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:18:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:18:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:18:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:18:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:18:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:18:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:18:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:18:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:18:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:18:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:18:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:18:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:18:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:18:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:18:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:18:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:18:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:18:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:18:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:18:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:18:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:18:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:18:44 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:18:45 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:18:45 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:18:45 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:18:45 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:18:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:18:45 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:18:45 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:18:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:18:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:18:45 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:18:45 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:18:45 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:18:45 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:18:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:18:45 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:18:45 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:18:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:18:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:18:45 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:18:45 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:18:45 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:18:45 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:18:45 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:18:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:18:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:18:46 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:18:46 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:18:46 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:18:46 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:18:46 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:18:46 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:18:46 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:18:46 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:18:46 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:18:46 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:18:46 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:18:46 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:18:46 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=293 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:18:46 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:18:46 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=293 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:18:46 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=293 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:18:46 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=293 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:18:46 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=293 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:18:46 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=293 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:18:46 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=294 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:18:46 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=294 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:18:46 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=294 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:18:46 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=294 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:18:46 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=294 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:18:46 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=294 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:18:46 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=294 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:18:46 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=294 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:18:51 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:18:51 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:18:51 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:18:51 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:18:51 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:18:51 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:18:51 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:18:51 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:18:51 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:18:51 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:18:51 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:18:51 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:18:51 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:18:51 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:18:51 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:18:51 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:18:51 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:18:51 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:18:51 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:18:51 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:18:51 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:18:51 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:18:51 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:18:51 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:18:51 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:18:51 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:18:51 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:18:51 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:18:51 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:18:51 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:18:51 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:18:51 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:18:51 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:18:51 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:18:51 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:18:51 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:18:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:18:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:18:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:18:51 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:18:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:18:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:18:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:18:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:18:51 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:18:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:18:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:18:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:18:51 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:18:51 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:18:51 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:18:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:18:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:18:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:18:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:18:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:18:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:18:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:18:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:18:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:18:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:18:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:18:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:18:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:18:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:18:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:18:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:18:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:18:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:18:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:18:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:18:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:18:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:18:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:18:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:18:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:18:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:18:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:18:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:18:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:18:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:18:51 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:18:51 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:18:51 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:18:51 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:18:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:18:51 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:18:51 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:18:51 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:18:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:18:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:18:51 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:18:51 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:18:51 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:18:51 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:18:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:18:51 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:18:51 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:18:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:18:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:18:52 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:18:52 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:18:52 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:18:52 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:18:52 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:18:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:18:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:18:52 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:18:52 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:18:52 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:18:52 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:18:52 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:18:52 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:18:52 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:18:52 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:18:52 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:18:52 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:18:52 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:18:52 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:18:52 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:18:57 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:18:57 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:18:57 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:18:57 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:18:57 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:18:57 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:18:57 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:18:57 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:18:57 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:18:57 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:18:57 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:18:57 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:18:57 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:18:57 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:18:57 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:18:57 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:18:57 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:18:57 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:18:57 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:18:57 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:18:57 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:18:57 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:18:57 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:18:57 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:18:57 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:18:57 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:18:57 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:18:57 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:18:57 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:18:57 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:18:57 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:18:57 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:18:57 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:18:57 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:18:57 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:18:57 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:18:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:18:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:18:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:18:57 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:18:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:18:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:18:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:18:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:18:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:18:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:18:57 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:18:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:18:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:18:57 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:18:57 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:18:57 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:18:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:18:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:18:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:18:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:18:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:18:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:18:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:18:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:18:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:18:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:18:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:18:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:18:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:18:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:18:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:18:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:18:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:18:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:18:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:18:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:18:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:18:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:18:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:18:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:18:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:18:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:18:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:18:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:18:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:18:57 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:18:58 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:18:58 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:18:58 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:18:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:18:58 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:18:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:18:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:18:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:18:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:18:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:18:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:18:58 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:18:58 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:18:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:18:58 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:18:58 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-27 05:18:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:18:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:18:58 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:18:58 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:18:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:18:58 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:18:58 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:18:59 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 05:18:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:18:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:18:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:18:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:18:59 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:18:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:18:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:18:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:18:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:18:59 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:18:59 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:18:59 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:18:59 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:18:59 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:18:59 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:18:59 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:19:04 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:19:04 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:19:04 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:19:04 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:19:04 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:19:04 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:19:04 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:19:04 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:19:04 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:19:04 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:19:04 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:19:04 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:19:04 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:19:04 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:19:04 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:19:04 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:19:04 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:19:04 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:19:04 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:19:04 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:19:04 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:19:04 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:19:04 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:19:04 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:19:04 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:19:04 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:19:04 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:19:04 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:19:04 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:19:04 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:19:04 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:19:04 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:19:04 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:19:04 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:19:04 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:19:04 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:19:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:19:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:19:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:19:04 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:19:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:19:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:19:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:19:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:19:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:19:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:19:04 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:19:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:19:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:19:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:19:04 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:19:04 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:19:04 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:19:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:19:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:19:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:19:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:19:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:19:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:19:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:19:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:19:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:19:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:19:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:19:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:19:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:19:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:19:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:19:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:19:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:19:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:19:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:19:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:19:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:19:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:19:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:19:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:19:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:19:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:19:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:19:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:19:04 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:19:04 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:19:04 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:19:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:19:04 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:19:04 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:19:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:19:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:19:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:19:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:19:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:19:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:19:04 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:19:04 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:19:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:19:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:19:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:19:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:19:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:19:05 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:19:05 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:19:05 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:19:05 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:19:05 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:19:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:19:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:19:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:19:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:19:05 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:19:05 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:19:05 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:19:05 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:19:05 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:19:05 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:19:05 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:19:05 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:19:05 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:19:05 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=293 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:19:05 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:19:05 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:19:05 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=293 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:19:05 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=293 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:19:05 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=293 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:19:05 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=293 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:19:05 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=294 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:19:05 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=294 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:19:05 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=294 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:19:05 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=294 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:19:05 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=294 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:19:05 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=294 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:19:05 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=294 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:19:05 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=294 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:19:10 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:19:10 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:19:10 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:19:10 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:19:10 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:19:10 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:19:10 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:19:10 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:19:10 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:19:10 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:19:10 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:19:10 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:19:10 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:19:10 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:19:10 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:19:10 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:19:10 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:19:10 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:19:10 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:19:10 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:19:10 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:19:10 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:19:10 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:19:10 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:19:10 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:19:10 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:19:10 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:19:10 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:19:10 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:19:10 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:19:10 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:19:10 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:19:10 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:19:10 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:19:10 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:19:10 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:19:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:19:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:19:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:19:10 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:19:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:19:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:19:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:19:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:19:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:19:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:19:10 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:19:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:19:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:19:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:19:10 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:19:10 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:19:10 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:19:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:19:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:19:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:19:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:19:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:19:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:19:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:19:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:19:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:19:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:19:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:19:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:19:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:19:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:19:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:19:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:19:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:19:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:19:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:19:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:19:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:19:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:19:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:19:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:19:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:19:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:19:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:19:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:19:10 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:19:10 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:19:11 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:19:11 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:19:11 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:19:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:19:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:19:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:19:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:19:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:19:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:19:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:19:11 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:19:11 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:19:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:19:11 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:19:11 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-27 05:19:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:19:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:19:11 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:19:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:19:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:19:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:19:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:19:11 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 05:19:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:19:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:19:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:19:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:19:11 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:19:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:19:12 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:19:12 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:19:12 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:19:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:19:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:19:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:19:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:19:12 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:19:12 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:19:12 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:19:12 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=323 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:19:12 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=323 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:19:12 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=323 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:19:12 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=323 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:19:12 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=323 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:19:12 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=323 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:19:12 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=323 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:19:12 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=324 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:19:12 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=324 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:19:12 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=324 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:19:12 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=324 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:19:12 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=324 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:19:12 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=324 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:19:12 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=324 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:19:12 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=324 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:19:17 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:19:17 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:19:17 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:19:17 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:19:17 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:19:17 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:19:17 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:19:17 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:19:17 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:19:17 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:19:17 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:19:17 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:19:17 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:19:17 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:19:17 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:19:17 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:19:17 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:19:17 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:19:17 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:19:17 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:19:17 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:19:17 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:19:17 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:19:17 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:19:17 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:19:17 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:19:17 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:19:17 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:19:17 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:19:17 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:19:17 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:19:17 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:19:17 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:19:17 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:19:17 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:19:17 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:19:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:19:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:19:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:19:17 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:19:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:19:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:19:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:19:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:19:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:19:17 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:19:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:19:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:19:17 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:19:17 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:19:17 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:19:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:19:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:19:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:19:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:19:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:19:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:19:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:19:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:19:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:19:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:19:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:19:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:19:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:19:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:19:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:19:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:19:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:19:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:19:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:19:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:19:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:19:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:19:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:19:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:19:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:19:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:19:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:19:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:19:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:19:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:19:17 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:19:17 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:19:17 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:19:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:19:17 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:19:17 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:19:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:19:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:19:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:19:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:19:17 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:19:17 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:19:17 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:19:17 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:19:18 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:19:18 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:19:18 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:19:18 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:19:18 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:19:18 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 05:19:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:19:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:19:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:19:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:19:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:19:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:19:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:19:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:19:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:19:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:19:18 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:19:18 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:19:18 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 05:19:19 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:19:19 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:19:19 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:19:19 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:19:19 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 05:19:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD NOHANDOVER
2025-04-27 05:19:19 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 05:19:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD NOHANDOVER
2025-04-27 05:19:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:19:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:19:19 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:19:19 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:19:19 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:19:19 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:19:19 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:19:19 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:19:19 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:19:19 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:19:19 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:19:19 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:19:19 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:19:19 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=625 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:19:19 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=625 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:19:19 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=625 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:19:19 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=625 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:19:19 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=625 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:19:19 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=625 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:19:19 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=625 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:19:24 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:19:24 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:19:24 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:19:24 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:19:24 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:19:24 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:19:24 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:19:24 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:19:24 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:19:24 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:19:24 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:19:24 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:19:24 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:19:24 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:19:24 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:19:24 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:19:24 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:19:24 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:19:24 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:19:24 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:19:24 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:19:24 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:19:24 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:19:24 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:19:24 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:19:24 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:19:24 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:19:24 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:19:24 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:19:24 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:19:24 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:19:24 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:19:24 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:19:24 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:19:24 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:19:24 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:19:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:19:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:19:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:19:24 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:19:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:19:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:19:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:19:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:19:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:19:24 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:19:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:19:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:19:24 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:19:24 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:19:24 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:19:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:19:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:19:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:19:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:19:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:19:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:19:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:19:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:19:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:19:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:19:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:19:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:19:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:19:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:19:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:19:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:19:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:19:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:19:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:19:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:19:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:19:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:19:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:19:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:19:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:19:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:19:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:19:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:19:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:19:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:19:24 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:19:25 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:19:25 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:19:25 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:19:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:19:25 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:19:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:19:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:19:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:19:25 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:19:25 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:19:25 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:19:25 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:19:25 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:19:26 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 05:19:26 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 05:19:26 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:19:26 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:19:26 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:19:26 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:19:27 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 05:19:27 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 05:19:27 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:19:28 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:19:28 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:19:28 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:19:28 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 05:19:28 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 05:19:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:19:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:19:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:19:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:19:29 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 05:19:29 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 05:19:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:19:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:19:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:19:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:19:30 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 05:19:30 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 05:19:31 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 05:19:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:19:31 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:19:31 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:19:31 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:19:31 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:19:31 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 05:19:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD NOHANDOVER
2025-04-27 05:19:31 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:19:31 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:19:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:19:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:19:32 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 05:19:32 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 05:19:33 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 05:19:33 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 05:19:34 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 05:19:34 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 05:19:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:19:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:19:34 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:19:34 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:19:34 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:19:34 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:19:34 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:19:34 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:19:34 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:19:34 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:19:34 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:19:34 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:19:34 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:19:34 [WARNING] transceiver.py:250 (TRX1@172.18.127.20:5700/1) RX TRXD message (ver=1 fn=2067 tn=0 bl=148 pwr=8), but transceiver is not running => dropping...
2025-04-27 05:19:34 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2067 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:19:34 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2067 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:19:34 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2067 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:19:34 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2067 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:19:34 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2067 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:19:34 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2067 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:19:39 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:19:39 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:19:39 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:19:39 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:19:39 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:19:39 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:19:39 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:19:39 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:19:39 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:19:39 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:19:39 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:19:39 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:19:39 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:19:39 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:19:39 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:19:39 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:19:39 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:19:39 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:19:39 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:19:39 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:19:39 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:19:39 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:19:39 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:19:39 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:19:39 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:19:39 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:19:39 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:19:39 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:19:39 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:19:39 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:19:39 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:19:39 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:19:39 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:19:39 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:19:39 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:19:39 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:19:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:19:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:19:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:19:39 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:19:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:19:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:19:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:19:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:19:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:19:39 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:19:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:19:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:19:39 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:19:39 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:19:39 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:19:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:19:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:19:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:19:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:19:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:19:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:19:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:19:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:19:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:19:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:19:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:19:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:19:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:19:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:19:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:19:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:19:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:19:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:19:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:19:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:19:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:19:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:19:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:19:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:19:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:19:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:19:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:19:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:19:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:19:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:19:39 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:19:40 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:19:40 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:19:40 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:19:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:19:40 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:19:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:19:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:19:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:19:40 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:19:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:19:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:19:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:19:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:19:41 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 05:19:41 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 05:19:41 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:19:41 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:19:41 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:19:41 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:19:42 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 05:19:42 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 05:19:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:19:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:19:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:19:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:19:43 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 05:19:43 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 05:19:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:19:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:19:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:19:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:19:43 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 05:19:44 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 05:19:44 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:19:44 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:19:44 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:19:44 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:19:44 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 05:19:45 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 05:19:45 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 05:19:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:19:46 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:19:46 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:19:46 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:19:46 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:19:46 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 05:19:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD NOHANDOVER
2025-04-27 05:19:46 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:19:46 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:19:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:19:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:19:46 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 05:19:47 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 05:19:47 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 05:19:48 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 05:19:48 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 05:19:49 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 05:19:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:19:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:19:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:19:49 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:19:49 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:19:49 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:19:49 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:19:49 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:19:49 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:19:49 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:19:49 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:19:49 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:19:49 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:19:49 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2073 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:19:49 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2073 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:19:49 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2073 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:19:49 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2073 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:19:49 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2073 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:19:54 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:19:54 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:19:54 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:19:54 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:19:54 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:19:54 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:19:54 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:19:54 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:19:54 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:19:54 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:19:54 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:19:54 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:19:54 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:19:54 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:19:54 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:19:54 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:19:54 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:19:54 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:19:54 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:19:54 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:19:54 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:19:54 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:19:54 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:19:54 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:19:54 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:19:54 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:19:54 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:19:54 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:19:54 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:19:54 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:19:54 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:19:54 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:19:54 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:19:54 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:19:54 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:19:54 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:19:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:19:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:19:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:19:54 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:19:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:19:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:19:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:19:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:19:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:19:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:19:54 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:19:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:19:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:19:54 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:19:54 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:19:54 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:19:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:19:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:19:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:19:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:19:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:19:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:19:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:19:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:19:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:19:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:19:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:19:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:19:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:19:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:19:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:19:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:19:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:19:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:19:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:19:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:19:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:19:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:19:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:19:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:19:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:19:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:19:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:19:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:19:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:19:54 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:19:54 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:19:54 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:19:54 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:19:54 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:19:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:19:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:19:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:19:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:19:55 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:19:55 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:19:55 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:19:55 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:19:55 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:19:55 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 05:19:56 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 05:19:56 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:19:56 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:19:56 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:19:56 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:19:56 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 05:19:57 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 05:19:57 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:19:57 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:19:57 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:19:57 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:19:57 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 05:19:58 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 05:19:58 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:19:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:19:58 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:19:58 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:19:58 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 05:19:59 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 05:19:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:19:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:19:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:19:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:19:59 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 05:20:00 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 05:20:00 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 05:20:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:20:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:20:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:20:00 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:20:00 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:20:01 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 05:20:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD NOHANDOVER
2025-04-27 05:20:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:20:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:20:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:20:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:20:01 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 05:20:02 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 05:20:02 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 05:20:02 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 05:20:03 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 05:20:03 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 05:20:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:20:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:20:04 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:20:04 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:20:04 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:20:04 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:20:04 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:20:04 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:20:04 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:20:04 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:20:04 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:20:04 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:20:04 [WARNING] transceiver.py:250 (TRX3@172.18.127.20:5700/3) RX TRXD message (ver=1 fn=2075 tn=0 bl=148 pwr=4), but transceiver is not running => dropping...
2025-04-27 05:20:04 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:20:04 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2075 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:20:04 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2075 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:20:04 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2075 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:20:04 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2075 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:20:04 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2075 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:20:04 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2075 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:20:04 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2075 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:20:09 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:20:09 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:20:09 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:20:09 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:20:09 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:20:09 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:20:09 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:20:09 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:20:09 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:20:09 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:20:09 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:20:09 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:20:09 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:20:09 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:20:09 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:20:09 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:20:09 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:20:09 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:20:09 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:20:09 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:20:09 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:20:09 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:20:09 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:20:09 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:20:09 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:20:09 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:20:09 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:20:09 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:20:09 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:20:09 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:20:09 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:20:09 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:20:09 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:20:09 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:20:09 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:20:09 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:20:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:20:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:20:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:20:09 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:20:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:20:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:20:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:20:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:20:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:20:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:20:09 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:20:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:20:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:20:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:20:09 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:20:09 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:20:09 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:20:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:20:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:20:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:20:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:20:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:20:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:20:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:20:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:20:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:20:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:20:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:20:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:20:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:20:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:20:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:20:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:20:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:20:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:20:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:20:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:20:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:20:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:20:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:20:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:20:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:20:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:20:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:20:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:20:09 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:20:09 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:20:09 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:20:09 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:20:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:20:09 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:20:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:20:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:20:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:20:10 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:20:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:20:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:20:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:20:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:20:10 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 05:20:11 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 05:20:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:20:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:20:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:20:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:20:11 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 05:20:12 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 05:20:12 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:20:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:20:12 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:20:12 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:20:12 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 05:20:13 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 05:20:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:20:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:20:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:20:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:20:13 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 05:20:13 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 05:20:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:20:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:20:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:20:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:20:14 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 05:20:14 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 05:20:15 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 05:20:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:20:15 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:20:15 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:20:15 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:20:15 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:20:15 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 05:20:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD NOHANDOVER
2025-04-27 05:20:15 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:20:15 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:20:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:20:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:20:16 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 05:20:16 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 05:20:17 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 05:20:17 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 05:20:18 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 05:20:18 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 05:20:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:20:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:20:18 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:20:18 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:20:18 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:20:18 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:20:18 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:20:18 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:20:18 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:20:18 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:20:18 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:20:18 [WARNING] transceiver.py:250 (TRX1@172.18.127.20:5700/1) RX TRXD message (ver=1 fn=2070 tn=0 bl=148 pwr=8), but transceiver is not running => dropping...
2025-04-27 05:20:18 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:20:18 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:20:18 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2070 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:20:18 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2070 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:20:18 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2070 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:20:18 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2070 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:20:18 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2070 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:20:18 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2070 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:20:18 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2070 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:20:23 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:20:23 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:20:23 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:20:23 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:20:23 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:20:23 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:20:23 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:20:23 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:20:23 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:20:23 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:20:23 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:20:23 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:20:23 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:20:23 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:20:23 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:20:23 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:20:23 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:20:23 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:20:23 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:20:23 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:20:23 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:20:23 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:20:23 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:20:23 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:20:23 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:20:23 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:20:23 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:20:23 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:20:23 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:20:23 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:20:23 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:20:23 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:20:23 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:20:23 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:20:23 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:20:23 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:20:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:20:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:20:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:20:23 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:20:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:20:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:20:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:20:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:20:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:20:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:20:23 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:20:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:20:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:20:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:20:23 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:20:23 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:20:23 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:20:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:20:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:20:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:20:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:20:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:20:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:20:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:20:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:20:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:20:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:20:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:20:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:20:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:20:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:20:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:20:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:20:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:20:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:20:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:20:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:20:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:20:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:20:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:20:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:20:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:20:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:20:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:20:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:20:23 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:20:24 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:20:24 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:20:24 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:20:24 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:20:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:20:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:20:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:20:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:20:24 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:20:24 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:20:24 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:20:24 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:20:24 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:20:25 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 05:20:25 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 05:20:25 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:20:25 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:20:25 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:20:25 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:20:26 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 05:20:26 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 05:20:26 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:20:26 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:20:26 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:20:26 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:20:27 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 05:20:27 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 05:20:27 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:20:27 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:20:27 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:20:27 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:20:28 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 05:20:28 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 05:20:28 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:20:28 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:20:28 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:20:28 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:20:29 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 05:20:29 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 05:20:30 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 05:20:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:20:30 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:20:30 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:20:30 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:20:30 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:20:30 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 05:20:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD NOHANDOVER
2025-04-27 05:20:30 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:20:30 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:20:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:20:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:20:31 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 05:20:31 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 05:20:32 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 05:20:32 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 05:20:33 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 05:20:33 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 05:20:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:20:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:20:33 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:20:33 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:20:33 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:20:33 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:20:33 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:20:33 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:20:33 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:20:33 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:20:33 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:20:33 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:20:33 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2067 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:20:33 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:20:33 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2067 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:20:33 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2067 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:20:33 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2068 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:20:33 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2068 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:20:33 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2068 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:20:33 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2068 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:20:33 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2068 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:20:33 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2068 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:20:33 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2068 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:20:33 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2068 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:20:38 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:20:38 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:20:38 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:20:38 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:20:38 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:20:38 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:20:38 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:20:38 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:20:38 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:20:38 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:20:38 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:20:38 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:20:38 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:20:38 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:20:38 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:20:38 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:20:38 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:20:38 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:20:38 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:20:38 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:20:38 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:20:38 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:20:38 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:20:38 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:20:38 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:20:38 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:20:38 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:20:38 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:20:38 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:20:38 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:20:38 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:20:38 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:20:38 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:20:38 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:20:38 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:20:38 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:20:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:20:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:20:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:20:38 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:20:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:20:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:20:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:20:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:20:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:20:38 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:20:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:20:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:20:38 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:20:38 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:20:38 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:20:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:20:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:20:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:20:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:20:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:20:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:20:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:20:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:20:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:20:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:20:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:20:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:20:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:20:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:20:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:20:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:20:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:20:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:20:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:20:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:20:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:20:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:20:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:20:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:20:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:20:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:20:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:20:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:20:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:20:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:20:38 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:20:39 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:20:39 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:20:39 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:20:39 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:20:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:20:39 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:20:39 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:20:39 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:20:39 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:20:39 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:20:40 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 05:20:40 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 05:20:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:20:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:20:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:20:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:20:41 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 05:20:41 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 05:20:41 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:20:41 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:20:41 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:20:41 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:20:42 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 05:20:42 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 05:20:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:20:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:20:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:20:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:20:42 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 05:20:43 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 05:20:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:20:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:20:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:20:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:20:43 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 05:20:44 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 05:20:44 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 05:20:45 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 05:20:45 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 05:20:46 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 05:20:46 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 05:20:47 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 05:20:47 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 05:20:48 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 05:20:48 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 05:20:49 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 05:20:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:20:49 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:20:49 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:20:49 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:20:49 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:20:49 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:20:49 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:20:49 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:20:49 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:20:49 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2255 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:20:49 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:20:49 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:20:49 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2255 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:20:54 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:20:54 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:20:54 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:20:54 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:20:54 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:20:54 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:20:54 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:20:54 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:20:54 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:20:54 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:20:54 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:20:54 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:20:54 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:20:54 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:20:54 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:20:54 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:20:54 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:20:54 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:20:54 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:20:54 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:20:54 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:20:54 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:20:54 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:20:54 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:20:54 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:20:54 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:20:54 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:20:54 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:20:54 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:20:54 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:20:54 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:20:54 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:20:54 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:20:54 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:20:54 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:20:54 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:20:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:20:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:20:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:20:54 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:20:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:20:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:20:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:20:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:20:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:20:54 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:20:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:20:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:20:54 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:20:54 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:20:54 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:20:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:20:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:20:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:20:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:20:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:20:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:20:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:20:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:20:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:20:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:20:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:20:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:20:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:20:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:20:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:20:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:20:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:20:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:20:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:20:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:20:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:20:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:20:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:20:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:20:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:20:54 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:20:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:20:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:20:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:20:54 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:20:54 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:20:54 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:20:54 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:20:54 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:20:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:20:59 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:20:59 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:20:59 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:20:59 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:20:59 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:20:59 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:20:59 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:20:59 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:20:59 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:20:59 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:20:59 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:20:59 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:20:59 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:20:59 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:20:59 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:20:59 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:20:59 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:20:59 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:20:59 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:20:59 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:20:59 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:20:59 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:20:59 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:20:59 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:20:59 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:20:59 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:20:59 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:20:59 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:20:59 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:20:59 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:20:59 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:20:59 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:20:59 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:20:59 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:20:59 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:20:59 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:20:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:20:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:20:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:20:59 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:20:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:20:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:20:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:20:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:20:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:20:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:20:59 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:20:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:20:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:20:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:20:59 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:20:59 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:20:59 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:20:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:20:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:20:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:20:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:20:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:20:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:20:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:20:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:20:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:20:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:20:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:20:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:20:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:20:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:20:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:20:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:20:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:20:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:20:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:20:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:20:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:20:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:20:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:20:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:20:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:20:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:20:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:20:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:20:59 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:20:59 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:20:59 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:20:59 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:20:59 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:20:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:20:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:20:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:20:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:20:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:20:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:20:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:20:59 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:20:59 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:21:00 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:21:00 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:21:00 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:21:00 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:21:00 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:21:00 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 05:21:01 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 05:21:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:21:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:21:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:21:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:21:01 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 05:21:02 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 05:21:02 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:21:02 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:21:02 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:21:02 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:21:02 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 05:21:03 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 05:21:03 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:21:03 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:21:03 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:21:03 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:21:03 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 05:21:04 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 05:21:04 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:21:04 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:21:04 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:21:04 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:21:04 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 05:21:05 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 05:21:05 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 05:21:05 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 05:21:06 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 05:21:06 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 05:21:07 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 05:21:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:21:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:21:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:21:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:21:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:21:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:21:07 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:21:07 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:21:07 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:21:07 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:21:07 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:21:07 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:21:07 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:21:07 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1823 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:21:07 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1823 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:21:07 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1823 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:21:07 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1823 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:21:07 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1823 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:21:07 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1823 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:21:07 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1823 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:21:07 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1824 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:21:07 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1824 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:21:07 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1824 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:21:07 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1824 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:21:07 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1824 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:21:07 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1824 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:21:07 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1824 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:21:07 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1824 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:21:12 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:21:12 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:21:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:21:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:21:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:21:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:21:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:21:12 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:21:12 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:21:12 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:21:12 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:21:12 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:21:12 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:21:12 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:21:12 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:21:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:21:12 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:21:12 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:21:12 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:21:12 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:21:12 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:21:12 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:21:12 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:21:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:21:12 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:21:12 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:21:12 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:21:12 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:21:12 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:21:12 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:21:12 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:21:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:21:12 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:21:12 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:21:12 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:21:12 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:21:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:21:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:21:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:21:12 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:21:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:21:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:21:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:21:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:21:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:21:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:21:12 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:21:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:21:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:21:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:21:12 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:21:12 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:21:12 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:21:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:21:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:21:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:21:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:21:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:21:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:21:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:21:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:21:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:21:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:21:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:21:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:21:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:21:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:21:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:21:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:21:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:21:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:21:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:21:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:21:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:21:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:21:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:21:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:21:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:21:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:21:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:21:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:21:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:21:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:21:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:21:12 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:21:12 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:21:12 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:21:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:21:17 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:21:17 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:21:17 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:21:17 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:21:17 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:21:17 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:21:17 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:21:17 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:21:17 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:21:17 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:21:17 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:21:17 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:21:17 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:21:17 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:21:17 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:21:17 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:21:17 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:21:17 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:21:17 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:21:17 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:21:17 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:21:17 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:21:17 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:21:17 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:21:17 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:21:17 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:21:17 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:21:17 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:21:17 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:21:17 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:21:17 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:21:17 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:21:17 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:21:17 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:21:17 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:21:17 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:21:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:21:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:21:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:21:17 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:21:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:21:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:21:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:21:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:21:17 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:21:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:21:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:21:17 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:21:17 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:21:17 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:21:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:21:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:21:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:21:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:21:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:21:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:21:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:21:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:21:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:21:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:21:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:21:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:21:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:21:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:21:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:21:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:21:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:21:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:21:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:21:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:21:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:21:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:21:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:21:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:21:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:21:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:21:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:21:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:21:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:21:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:21:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:21:17 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:21:18 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:21:18 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:21:18 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:21:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:21:18 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:21:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:21:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:21:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:21:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:21:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:21:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:21:18 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:21:18 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:21:18 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:21:18 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:21:18 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:21:18 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:21:18 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:21:19 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 05:21:19 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 05:21:19 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:21:19 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:21:19 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:21:19 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:21:20 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 05:21:20 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 05:21:20 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:21:20 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:21:20 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:21:20 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:21:21 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 05:21:21 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 05:21:21 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:21:21 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:21:21 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:21:21 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:21:22 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 05:21:22 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 05:21:22 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:21:22 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:21:22 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:21:22 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:21:23 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 05:21:23 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 05:21:24 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 05:21:24 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 05:21:25 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 05:21:25 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 05:21:26 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 05:21:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:21:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:21:26 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:21:26 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:21:26 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:21:26 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:21:26 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:21:26 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:21:26 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:21:26 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:21:26 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:21:26 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:21:26 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:21:26 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1838 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:21:31 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:21:31 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:21:31 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:21:31 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:21:31 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:21:31 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:21:31 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:21:31 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:21:31 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:21:31 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:21:31 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:21:31 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:21:31 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:21:31 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:21:31 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:21:31 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:21:31 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:21:31 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:21:31 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:21:31 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:21:31 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:21:31 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:21:31 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:21:31 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:21:31 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:21:31 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:21:31 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:21:31 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:21:31 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:21:31 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:21:31 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:21:31 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:21:31 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:21:31 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:21:31 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:21:31 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:21:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:21:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:21:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:21:31 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:21:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:21:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:21:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:21:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:21:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:21:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:21:31 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:21:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:21:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:21:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:21:31 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:21:31 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:21:31 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:21:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:21:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:21:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:21:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:21:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:21:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:21:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:21:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:21:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:21:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:21:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:21:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:21:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:21:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:21:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:21:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:21:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:21:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:21:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:21:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:21:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:21:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:21:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:21:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:21:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:21:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:21:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:21:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:21:31 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:21:31 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:21:31 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:21:31 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:21:31 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:21:31 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:21:31 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:21:36 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:21:36 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:21:36 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:21:36 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:21:36 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:21:36 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:21:36 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:21:36 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:21:36 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:21:36 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:21:36 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:21:36 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:21:36 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:21:36 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:21:36 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:21:36 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:21:36 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:21:36 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:21:36 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:21:36 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:21:36 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:21:36 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:21:36 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:21:36 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:21:36 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:21:36 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:21:36 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:21:36 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:21:36 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:21:36 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:21:36 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:21:36 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:21:36 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:21:36 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:21:36 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:21:36 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:21:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:21:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:21:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:21:36 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:21:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:21:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:21:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:21:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:21:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:21:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:21:36 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:21:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:21:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:21:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:21:36 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:21:36 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:21:36 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:21:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:21:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:21:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:21:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:21:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:21:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:21:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:21:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:21:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:21:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:21:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:21:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:21:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:21:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:21:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:21:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:21:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:21:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:21:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:21:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:21:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:21:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:21:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:21:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:21:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:21:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:21:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:21:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:21:36 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:21:37 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:21:37 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:21:37 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:21:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:21:37 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:21:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:21:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:21:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:21:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:21:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:21:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:21:37 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:21:37 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:21:37 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:21:37 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:21:37 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:21:37 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:21:37 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:21:37 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 05:21:38 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 05:21:38 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:21:38 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:21:38 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:21:38 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:21:38 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 05:21:39 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 05:21:39 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:21:39 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:21:39 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:21:39 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:21:39 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 05:21:40 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 05:21:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:21:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:21:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:21:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:21:40 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 05:21:41 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 05:21:41 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:21:41 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:21:41 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:21:41 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:21:41 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 05:21:42 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 05:21:42 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 05:21:43 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 05:21:43 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 05:21:44 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 05:21:44 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 05:21:45 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:21:45 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:21:45 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:21:45 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:21:45 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:21:45 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:21:45 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:21:45 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:21:45 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:21:45 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:21:45 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:21:45 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:21:45 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:21:50 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:21:50 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:21:50 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:21:50 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:21:50 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:21:50 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:21:50 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:21:50 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:21:50 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:21:50 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:21:50 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:21:50 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:21:50 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:21:50 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:21:50 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:21:50 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:21:50 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:21:50 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:21:50 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:21:50 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:21:50 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:21:50 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:21:50 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:21:50 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:21:50 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:21:50 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:21:50 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:21:50 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:21:50 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:21:50 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:21:50 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:21:50 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:21:50 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:21:50 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:21:50 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:21:50 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:21:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:21:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:21:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:21:50 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:21:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:21:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:21:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:21:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:21:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:21:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:21:50 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:21:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:21:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:21:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:21:50 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:21:50 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:21:50 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:21:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:21:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:21:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:21:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:21:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:21:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:21:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:21:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:21:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:21:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:21:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:21:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:21:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:21:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:21:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:21:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:21:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:21:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:21:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:21:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:21:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:21:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:21:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:21:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:21:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:21:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:21:50 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:21:50 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:21:50 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:21:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:21:50 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:21:50 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:21:50 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:21:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:21:55 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:21:55 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:21:55 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:21:55 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:21:55 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:21:55 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:21:55 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:21:55 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:21:55 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:21:55 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:21:55 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:21:55 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:21:55 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:21:55 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:21:55 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:21:55 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:21:55 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:21:55 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:21:55 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:21:55 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:21:55 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:21:55 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:21:55 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:21:55 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:21:55 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:21:55 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:21:55 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:21:55 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:21:55 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:21:55 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:21:55 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:21:55 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:21:55 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:21:55 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:21:55 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:21:55 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:21:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:21:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:21:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:21:55 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:21:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:21:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:21:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:21:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:21:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:21:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:21:55 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:21:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:21:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:21:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:21:55 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:21:55 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:21:55 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:21:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:21:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:21:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:21:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:21:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:21:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:21:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:21:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:21:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:21:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:21:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:21:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:21:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:21:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:21:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:21:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:21:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:21:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:21:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:21:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:21:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:21:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:21:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:21:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:21:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:21:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:21:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:21:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:21:55 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:21:55 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:21:55 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:21:55 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:21:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:21:55 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:21:55 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:21:55 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:21:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:21:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:21:55 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:21:55 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:21:55 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:21:55 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:21:56 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:21:56 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:21:56 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:21:56 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:21:56 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:21:56 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 05:21:57 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 05:21:57 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:21:57 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:21:57 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:21:57 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:21:57 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 05:21:58 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 05:21:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:21:58 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:21:58 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:21:58 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:21:58 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 05:21:59 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 05:21:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:21:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:21:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:21:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:21:59 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 05:21:59 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 05:22:00 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:22:00 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:22:00 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:22:00 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:22:00 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 05:22:00 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 05:22:01 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 05:22:01 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 05:22:02 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 05:22:02 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 05:22:03 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 05:22:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:22:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:22:03 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 05:22:03 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:22:03 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:22:03 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:22:03 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:22:03 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:22:03 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:22:03 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:22:03 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:22:03 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:22:03 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:22:03 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:22:08 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:22:08 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:22:08 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:22:08 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:22:08 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:22:08 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:22:08 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:22:08 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:22:08 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:22:08 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:22:08 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:22:08 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:22:08 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:22:08 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:22:08 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:22:08 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:22:08 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:22:08 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:22:08 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:22:08 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:22:08 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:22:08 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:22:08 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:22:08 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:22:08 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:22:08 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:22:08 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:22:08 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:22:08 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:22:08 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:22:08 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:22:08 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:22:08 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:22:08 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:22:08 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:22:08 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:22:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:22:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:22:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:22:08 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:22:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:22:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:22:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:22:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:22:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:22:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:22:08 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:22:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:22:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:22:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:22:08 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:22:08 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:22:08 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:22:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:22:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:22:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:22:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:22:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:22:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:22:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:22:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:22:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:22:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:22:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:22:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:22:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:22:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:22:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:22:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:22:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:22:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:22:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:22:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:22:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:22:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:22:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:22:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:22:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:22:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:22:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:22:08 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:22:08 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:22:08 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:22:08 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:22:08 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:22:08 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:22:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:22:13 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:22:13 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:22:13 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:22:13 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:22:13 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:22:13 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:22:13 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:22:13 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:22:13 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:22:13 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:22:13 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:22:13 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:22:13 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:22:13 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:22:13 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:22:13 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:22:13 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:22:13 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:22:13 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:22:13 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:22:13 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:22:13 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:22:13 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:22:13 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:22:13 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:22:13 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:22:13 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:22:13 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:22:13 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:22:13 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:22:13 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:22:13 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:22:13 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:22:13 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:22:13 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:22:13 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:22:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:22:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:22:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:22:13 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:22:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:22:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:22:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:22:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:22:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:22:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:22:13 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:22:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:22:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:22:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:22:13 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:22:13 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:22:13 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:22:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:22:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:22:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:22:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:22:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:22:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:22:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:22:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:22:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:22:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:22:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:22:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:22:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:22:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:22:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:22:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:22:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:22:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:22:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:22:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:22:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:22:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:22:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:22:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:22:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:22:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:22:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:22:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:22:13 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:22:14 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:22:14 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:22:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:22:14 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:22:14 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:22:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:22:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:22:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:22:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:22:14 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:22:14 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:22:14 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:22:14 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:22:14 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:22:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:22:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:22:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:22:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:22:15 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 05:22:15 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 05:22:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:22:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:22:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:22:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:22:16 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 05:22:16 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 05:22:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:22:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:22:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:22:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:22:17 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 05:22:17 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 05:22:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:22:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:22:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:22:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:22:18 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 05:22:18 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 05:22:18 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:22:18 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:22:18 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:22:18 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:22:19 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 05:22:19 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 05:22:20 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 05:22:20 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 05:22:21 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 05:22:21 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 05:22:21 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 05:22:22 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 05:22:22 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 05:22:23 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 05:22:23 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 05:22:24 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 05:22:24 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-27 05:22:25 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-27 05:22:25 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-27 05:22:26 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-27 05:22:26 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-27 05:22:27 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-27 05:22:27 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-27 05:22:28 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-27 05:22:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:22:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:22:28 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:22:28 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:22:28 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:22:28 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:22:28 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:22:28 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:22:28 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:22:28 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:22:28 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:22:28 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:22:28 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:22:28 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3119 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:22:28 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3119 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:22:28 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3119 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:22:28 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3119 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:22:28 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3119 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:22:28 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3119 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:22:28 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3119 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:22:33 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:22:33 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:22:33 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:22:33 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:22:33 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:22:33 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:22:33 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:22:33 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:22:33 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:22:33 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:22:33 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:22:33 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:22:33 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:22:33 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:22:33 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:22:33 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:22:33 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:22:33 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:22:33 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:22:33 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:22:33 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:22:33 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:22:33 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:22:33 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:22:33 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:22:33 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:22:33 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:22:33 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:22:33 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:22:33 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:22:33 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:22:33 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:22:33 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:22:33 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:22:33 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:22:33 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:22:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:22:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:22:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:22:33 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:22:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:22:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:22:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:22:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:22:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:22:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:22:33 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:22:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:22:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:22:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:22:33 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:22:33 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:22:33 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:22:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:22:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:22:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:22:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:22:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:22:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:22:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:22:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:22:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:22:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:22:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:22:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:22:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:22:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:22:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:22:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:22:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:22:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:22:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:22:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:22:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:22:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:22:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:22:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:22:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:22:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:22:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:22:33 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:22:33 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:22:33 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:22:33 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:22:33 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:22:33 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:22:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:22:38 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:22:38 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:22:38 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:22:38 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:22:38 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:22:38 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:22:38 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:22:38 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:22:38 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:22:38 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:22:38 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:22:38 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:22:38 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:22:38 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:22:38 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:22:38 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:22:38 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:22:38 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:22:38 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:22:38 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:22:38 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:22:38 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:22:38 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:22:38 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:22:38 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:22:38 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:22:38 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:22:38 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:22:38 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:22:38 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:22:38 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:22:38 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:22:38 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:22:38 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:22:38 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:22:38 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:22:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:22:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:22:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:22:38 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:22:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:22:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:22:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:22:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:22:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:22:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:22:38 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:22:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:22:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:22:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:22:38 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:22:38 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:22:38 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:22:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:22:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:22:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:22:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:22:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:22:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:22:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:22:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:22:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:22:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:22:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:22:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:22:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:22:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:22:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:22:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:22:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:22:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:22:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:22:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:22:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:22:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:22:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:22:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:22:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:22:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:22:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:22:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:22:38 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:22:39 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:22:39 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:22:39 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:22:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:22:39 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:22:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:22:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:22:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:22:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:22:39 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:22:39 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:22:39 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:22:39 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:22:39 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:22:39 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:22:39 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:22:39 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:22:39 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:22:39 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 05:22:40 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 05:22:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:22:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:22:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:22:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:22:40 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 05:22:41 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 05:22:41 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:22:41 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:22:41 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:22:41 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:22:41 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 05:22:42 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 05:22:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:22:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:22:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:22:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:22:42 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 05:22:43 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 05:22:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:22:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:22:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:22:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:22:43 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 05:22:44 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 05:22:44 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 05:22:45 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 05:22:45 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 05:22:46 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 05:22:46 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 05:22:47 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:22:47 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:22:47 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:22:47 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:22:47 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:22:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:22:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:22:47 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:22:47 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:22:47 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:22:47 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:22:47 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:22:47 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:22:47 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1833 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:22:47 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1833 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:22:47 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1833 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:22:47 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1833 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:22:47 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1833 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:22:47 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1833 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:22:47 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1833 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:22:52 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:22:52 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:22:52 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:22:52 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:22:52 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:22:52 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:22:52 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:22:52 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:22:52 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:22:52 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:22:52 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:22:52 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:22:52 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:22:52 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:22:52 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:22:52 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:22:52 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:22:52 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:22:52 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:22:52 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:22:52 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:22:52 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:22:52 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:22:52 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:22:52 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:22:52 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:22:52 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:22:52 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:22:52 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:22:52 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:22:52 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:22:52 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:22:52 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:22:52 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:22:52 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:22:52 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:22:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:22:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:22:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:22:52 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:22:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:22:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:22:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:22:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:22:52 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:22:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:22:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:22:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:22:52 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:22:52 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:22:52 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:22:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:22:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:22:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:22:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:22:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:22:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:22:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:22:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:22:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:22:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:22:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:22:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:22:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:22:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:22:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:22:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:22:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:22:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:22:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:22:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:22:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:22:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:22:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:22:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:22:52 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:22:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:22:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:22:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:22:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:22:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:22:52 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:22:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:22:52 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:22:52 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:22:52 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:22:52 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:22:52 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:22:57 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:22:57 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:22:57 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:22:57 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:22:57 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:22:57 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:22:57 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:22:57 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:22:57 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:22:57 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:22:57 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:22:57 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:22:57 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:22:57 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:22:57 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:22:57 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:22:57 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:22:57 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:22:57 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:22:57 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:22:57 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:22:57 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:22:57 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:22:57 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:22:57 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:22:57 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:22:57 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:22:57 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:22:57 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:22:57 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:22:57 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:22:57 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:22:57 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:22:57 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:22:57 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:22:57 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:22:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:22:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:22:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:22:57 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:22:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:22:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:22:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:22:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:22:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:22:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:22:57 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:22:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:22:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:22:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:22:57 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:22:57 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:22:57 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:22:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:22:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:22:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:22:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:22:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:22:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:22:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:22:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:22:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:22:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:22:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:22:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:22:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:22:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:22:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:22:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:22:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:22:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:22:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:22:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:22:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:22:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:22:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:22:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:22:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:22:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:22:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:22:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:22:57 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:22:57 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:22:57 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:22:57 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:22:57 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:22:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:22:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:22:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:22:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:22:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:22:57 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:22:57 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:22:57 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:22:57 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:22:58 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:22:58 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:22:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:22:58 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:22:58 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:22:58 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 05:22:59 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 05:22:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:22:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:22:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:22:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:22:59 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 05:23:00 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 05:23:00 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:23:00 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:23:00 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:23:00 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:23:00 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 05:23:00 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 05:23:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:23:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:23:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:23:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:23:01 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 05:23:01 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 05:23:02 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:23:02 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:23:02 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:23:02 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:23:02 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 05:23:02 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 05:23:03 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 05:23:03 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 05:23:04 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 05:23:04 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 05:23:05 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 05:23:05 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 05:23:06 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 05:23:06 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 05:23:07 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 05:23:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:23:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:23:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:23:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:23:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:23:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:23:07 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:23:07 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:23:07 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:23:07 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:23:07 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:23:07 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:23:07 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:23:07 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2245 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:23:07 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2245 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:23:07 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2245 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:23:07 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2245 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:23:07 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2245 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:23:07 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2245 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:23:07 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2245 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:23:12 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:23:12 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:23:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:23:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:23:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:23:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:23:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:23:12 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:23:12 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:23:12 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:23:12 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:23:12 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:23:12 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:23:12 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:23:12 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:23:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:23:12 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:23:12 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:23:12 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:23:12 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:23:12 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:23:12 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:23:12 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:23:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:23:12 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:23:12 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:23:12 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:23:12 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:23:12 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:23:12 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:23:12 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:23:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:23:12 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:23:12 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:23:12 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:23:12 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:23:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:23:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:23:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:23:12 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:23:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:23:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:23:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:23:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:23:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:23:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:23:12 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:23:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:23:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:23:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:23:12 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:23:12 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:23:12 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:23:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:23:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:23:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:23:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:23:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:23:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:23:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:23:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:23:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:23:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:23:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:23:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:23:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:23:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:23:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:23:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:23:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:23:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:23:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:23:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:23:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:23:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:23:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:23:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:23:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:23:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:23:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:23:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:23:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:23:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:23:12 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:23:12 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:23:12 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:23:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:23:17 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:23:17 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:23:17 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:23:17 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:23:17 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:23:17 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:23:17 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:23:17 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:23:17 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:23:17 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:23:17 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:23:17 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:23:17 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:23:17 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:23:17 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:23:17 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:23:17 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:23:17 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:23:17 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:23:17 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:23:17 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:23:17 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:23:17 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:23:17 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:23:17 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:23:17 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:23:17 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:23:17 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:23:17 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:23:17 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:23:17 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:23:17 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:23:17 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:23:17 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:23:17 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:23:17 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:23:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:23:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:23:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:23:17 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:23:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:23:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:23:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:23:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:23:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:23:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:23:17 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:23:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:23:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:23:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:23:17 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:23:17 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:23:17 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:23:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:23:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:23:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:23:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:23:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:23:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:23:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:23:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:23:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:23:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:23:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:23:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:23:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:23:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:23:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:23:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:23:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:23:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:23:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:23:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:23:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:23:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:23:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:23:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:23:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:23:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:23:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:23:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:23:17 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:23:18 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:23:18 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:23:18 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:23:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:23:18 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:23:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:23:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:23:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:23:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:23:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:23:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:23:18 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:23:18 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:23:18 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:23:18 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:23:18 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:23:18 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:23:18 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:23:19 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 05:23:19 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 05:23:19 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:23:19 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:23:19 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:23:19 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:23:20 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 05:23:20 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 05:23:20 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:23:20 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:23:20 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:23:20 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:23:21 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 05:23:21 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 05:23:21 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:23:21 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:23:21 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:23:21 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:23:22 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 05:23:22 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 05:23:22 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:23:22 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:23:22 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:23:22 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:23:23 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 05:23:23 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 05:23:24 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 05:23:24 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 05:23:24 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 05:23:25 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 05:23:25 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 05:23:26 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 05:23:26 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 05:23:27 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 05:23:27 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 05:23:28 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 05:23:28 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-27 05:23:29 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-27 05:23:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:23:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:23:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:23:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:23:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:23:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:23:29 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:23:29 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:23:29 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:23:29 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:23:29 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:23:29 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2460 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:23:29 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:23:29 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:23:29 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2460 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:23:29 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2460 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:23:29 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2460 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:23:29 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2460 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:23:29 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2460 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:23:34 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:23:34 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:23:34 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:23:34 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:23:34 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:23:34 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:23:34 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:23:34 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:23:34 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:23:34 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:23:34 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:23:34 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:23:34 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:23:34 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:23:34 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:23:34 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:23:34 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:23:34 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:23:34 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:23:34 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:23:34 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:23:34 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:23:34 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:23:34 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:23:34 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:23:34 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:23:34 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:23:34 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:23:34 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:23:34 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:23:34 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:23:34 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:23:34 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:23:34 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:23:34 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:23:34 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:23:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:23:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:23:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:23:34 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:23:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:23:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:23:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:23:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:23:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:23:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:23:34 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:23:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:23:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:23:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:23:34 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:23:34 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:23:34 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:23:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:23:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:23:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:23:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:23:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:23:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:23:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:23:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:23:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:23:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:23:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:23:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:23:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:23:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:23:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:23:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:23:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:23:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:23:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:23:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:23:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:23:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:23:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:23:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:23:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:23:34 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:23:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:23:34 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:23:34 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:23:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:23:34 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:23:34 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:23:34 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:23:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:23:39 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:23:39 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:23:39 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:23:39 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:23:39 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:23:39 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:23:39 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:23:39 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:23:39 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:23:39 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:23:39 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:23:39 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:23:39 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:23:39 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:23:39 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:23:39 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:23:39 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:23:39 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:23:39 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:23:39 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:23:39 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:23:39 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:23:39 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:23:39 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:23:39 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:23:39 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:23:39 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:23:39 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:23:39 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:23:39 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:23:39 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:23:39 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:23:39 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:23:39 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:23:39 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:23:39 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:23:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:23:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:23:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:23:39 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:23:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:23:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:23:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:23:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:23:39 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:23:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:23:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:23:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:23:39 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:23:39 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:23:39 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:23:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:23:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:23:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:23:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:23:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:23:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:23:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:23:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:23:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:23:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:23:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:23:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:23:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:23:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:23:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:23:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:23:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:23:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:23:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:23:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:23:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:23:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:23:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:23:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:23:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:23:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:23:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:23:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:23:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:23:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:23:39 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:23:39 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:23:39 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:23:39 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:23:39 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:23:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:23:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:23:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:23:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:23:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:23:39 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:23:39 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:23:39 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:23:39 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:23:40 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:23:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:23:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:23:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:23:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:23:40 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 05:23:41 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 05:23:41 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:23:41 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:23:41 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:23:41 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:23:41 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 05:23:42 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 05:23:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:23:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:23:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:23:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:23:42 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 05:23:43 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 05:23:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:23:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:23:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:23:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:23:43 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 05:23:44 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 05:23:44 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:23:44 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:23:44 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:23:44 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:23:44 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 05:23:45 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 05:23:45 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 05:23:46 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 05:23:46 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 05:23:47 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 05:23:47 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 05:23:47 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 05:23:48 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 05:23:48 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 05:23:49 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 05:23:49 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 05:23:50 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-27 05:23:50 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-27 05:23:51 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-27 05:23:51 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-27 05:23:52 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-27 05:23:52 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-27 05:23:53 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-27 05:23:53 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-27 05:23:54 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-27 05:23:54 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-27 05:23:55 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-27 05:23:55 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-27 05:23:56 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-27 05:23:56 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-27 05:23:57 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-27 05:23:57 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-27 05:23:58 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2025-04-27 05:23:58 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2025-04-27 05:23:58 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2025-04-27 05:23:59 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2025-04-27 05:23:59 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2025-04-27 05:23:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:23:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:23:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:23:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:23:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:23:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:23:59 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:23:59 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:23:59 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:23:59 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:23:59 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:23:59 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:23:59 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:23:59 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4389 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:23:59 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4389 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:23:59 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4389 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:23:59 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4389 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:23:59 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4389 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:23:59 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4389 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:23:59 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4389 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:24:04 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:24:04 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:24:04 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:24:04 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:24:04 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:24:04 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:24:04 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:24:04 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:24:04 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:24:04 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:24:04 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:24:04 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:24:04 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:24:04 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:24:04 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:24:04 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:24:04 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:24:04 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:24:04 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:24:04 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:24:04 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:24:04 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:24:04 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:24:04 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:24:04 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:24:04 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:24:04 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:24:04 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:24:04 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:24:04 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:24:04 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:24:04 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:24:04 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:24:04 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:24:04 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:24:04 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:24:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:24:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:24:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:24:04 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:24:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:24:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:24:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:24:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:24:04 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:24:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:24:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:24:04 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:24:04 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:24:04 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:24:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:24:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:24:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:24:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:24:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:24:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:24:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:24:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:24:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:24:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:24:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:24:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:24:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:24:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:24:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:24:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:24:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:24:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:24:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:24:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:24:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:24:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:24:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:24:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:24:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:24:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:24:04 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:24:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:24:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:24:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:24:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:24:04 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:24:04 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:24:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:24:04 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:24:04 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:24:04 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:24:04 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:24:10 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:24:10 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:24:10 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:24:10 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:24:10 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:24:10 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:24:10 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:24:10 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:24:10 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:24:10 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:24:10 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:24:10 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:24:10 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:24:10 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:24:10 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:24:10 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:24:10 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:24:10 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:24:10 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:24:10 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:24:10 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:24:10 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:24:10 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:24:10 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:24:10 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:24:10 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:24:10 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:24:10 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:24:10 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:24:10 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:24:10 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:24:10 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:24:10 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:24:10 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:24:10 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:24:10 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:24:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:24:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:24:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:24:10 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:24:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:24:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:24:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:24:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:24:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:24:10 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:24:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:24:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:24:10 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:24:10 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:24:10 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:24:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:24:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:24:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:24:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:24:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:24:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:24:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:24:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:24:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:24:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:24:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:24:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:24:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:24:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:24:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:24:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:24:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:24:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:24:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:24:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:24:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:24:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:24:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:24:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:24:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:24:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:24:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:24:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:24:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:24:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:24:10 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:24:10 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:24:10 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:24:10 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:24:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:24:10 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:24:11 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:24:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:24:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:24:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:24:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:24:11 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 05:24:11 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 05:24:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:24:12 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:24:12 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:24:12 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:24:12 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 05:24:12 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 05:24:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:24:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:24:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:24:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:24:13 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 05:24:13 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 05:24:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:24:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:24:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:24:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:24:14 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 05:24:14 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 05:24:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:24:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:24:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:24:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:24:15 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 05:24:15 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 05:24:16 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 05:24:16 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 05:24:17 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 05:24:17 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 05:24:18 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 05:24:18 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 05:24:19 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 05:24:19 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 05:24:20 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 05:24:20 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:24:20 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:24:20 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:24:20 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:24:20 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:24:20 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:24:20 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:24:20 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:24:20 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:24:20 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:24:20 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2244 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:24:20 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:24:20 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2244 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:24:20 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2244 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:24:20 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2244 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:24:20 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2244 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:24:20 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2244 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:24:20 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2244 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:24:25 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:24:25 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:24:25 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:24:25 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:24:25 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:24:25 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:24:25 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:24:25 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:24:25 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:24:25 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:24:25 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:24:25 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:24:25 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:24:25 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:24:25 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:24:25 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:24:25 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:24:25 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:24:25 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:24:25 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:24:25 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:24:25 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:24:25 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:24:25 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:24:25 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:24:25 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:24:25 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:24:25 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:24:25 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:24:25 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:24:25 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:24:25 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:24:25 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:24:25 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:24:25 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:24:25 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:24:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:24:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:24:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:24:25 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:24:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:24:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:24:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:24:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:24:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:24:25 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:24:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:24:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:24:25 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:24:25 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:24:25 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:24:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:24:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:24:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:24:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:24:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:24:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:24:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:24:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:24:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:24:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:24:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:24:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:24:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:24:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:24:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:24:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:24:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:24:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:24:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:24:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:24:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:24:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:24:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:24:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:24:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:24:25 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:24:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:24:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:24:25 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:24:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:24:25 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:24:25 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:24:25 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:24:25 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:24:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:24:30 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:24:30 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:24:30 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:24:30 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:24:30 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:24:30 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:24:30 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:24:30 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:24:30 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:24:30 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:24:30 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:24:30 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:24:30 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:24:30 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:24:30 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:24:30 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:24:30 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:24:30 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:24:30 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:24:30 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:24:30 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:24:30 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:24:30 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:24:30 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:24:30 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:24:30 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:24:30 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:24:30 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:24:30 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:24:30 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:24:30 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:24:30 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:24:30 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:24:30 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:24:30 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:24:30 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:24:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:24:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:24:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:24:30 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:24:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:24:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:24:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:24:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:24:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:24:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:24:30 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:24:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:24:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:24:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:24:30 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:24:30 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:24:30 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:24:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:24:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:24:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:24:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:24:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:24:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:24:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:24:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:24:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:24:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:24:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:24:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:24:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:24:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:24:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:24:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:24:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:24:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:24:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:24:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:24:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:24:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:24:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:24:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:24:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:24:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:24:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:24:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:24:30 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:24:31 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:24:31 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:24:31 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:24:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:24:31 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:24:31 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:24:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:24:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:24:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:24:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:24:32 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 05:24:32 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 05:24:32 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:24:32 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:24:32 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:24:32 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:24:33 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 05:24:33 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 05:24:33 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:24:33 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:24:33 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:24:33 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:24:34 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 05:24:34 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 05:24:34 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:24:34 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:24:34 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:24:34 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:24:35 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 05:24:35 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 05:24:35 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:24:35 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:24:35 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:24:35 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:24:35 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 05:24:36 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 05:24:36 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 05:24:37 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 05:24:37 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 05:24:38 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 05:24:38 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 05:24:39 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 05:24:39 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 05:24:40 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 05:24:40 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 05:24:41 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 05:24:41 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-27 05:24:42 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-27 05:24:42 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-27 05:24:43 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-27 05:24:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:24:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:24:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:24:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:24:43 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:24:43 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:24:43 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:24:43 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:24:43 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:24:43 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:24:43 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:24:43 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2671 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:24:43 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2671 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:24:43 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2671 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:24:43 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2671 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:24:43 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2671 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:24:43 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2671 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:24:43 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2671 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:24:48 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:24:48 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:24:48 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:24:48 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:24:48 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:24:48 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:24:48 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:24:48 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:24:48 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:24:48 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:24:48 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:24:48 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:24:48 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:24:48 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:24:48 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:24:48 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:24:48 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:24:48 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:24:48 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:24:48 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:24:48 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:24:48 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:24:48 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:24:48 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:24:48 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:24:48 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:24:48 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:24:48 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:24:48 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:24:48 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:24:48 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:24:48 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:24:48 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:24:48 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:24:48 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:24:48 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:24:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:24:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:24:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:24:48 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:24:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:24:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:24:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:24:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:24:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:24:48 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:24:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:24:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:24:48 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:24:48 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:24:48 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:24:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:24:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:24:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:24:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:24:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:24:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:24:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:24:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:24:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:24:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:24:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:24:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:24:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:24:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:24:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:24:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:24:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:24:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:24:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:24:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:24:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:24:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:24:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:24:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:24:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:24:48 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:24:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:24:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:24:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:24:48 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:24:48 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:24:48 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:24:48 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:24:48 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:24:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:24:53 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:24:53 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:24:53 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:24:53 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:24:53 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:24:53 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:24:53 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:24:53 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:24:53 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:24:53 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:24:53 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:24:53 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:24:53 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:24:53 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:24:53 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:24:53 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:24:53 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:24:53 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:24:53 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:24:53 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:24:53 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:24:53 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:24:53 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:24:53 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:24:53 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:24:53 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:24:53 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:24:53 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:24:53 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:24:53 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:24:53 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:24:53 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:24:53 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:24:53 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:24:53 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:24:53 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:24:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:24:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:24:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:24:53 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:24:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:24:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:24:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:24:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:24:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:24:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:24:53 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:24:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:24:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:24:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:24:53 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:24:53 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:24:53 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:24:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:24:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:24:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:24:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:24:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:24:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:24:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:24:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:24:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:24:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:24:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:24:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:24:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:24:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:24:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:24:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:24:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:24:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:24:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:24:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:24:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:24:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:24:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:24:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:24:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:24:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:24:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:24:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:24:53 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:24:53 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:24:53 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:24:53 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:24:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:24:53 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:24:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:24:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:24:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:24:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:24:53 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:24:53 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:24:53 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:24:53 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:24:53 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:24:53 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2025-04-27 05:24:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:24:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:24:54 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:24:54 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:24:54 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:24:54 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:24:54 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:24:54 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 05:24:55 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 05:24:55 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:24:55 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:24:55 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:24:55 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:24:55 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 05:24:56 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 05:24:56 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:24:56 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:24:56 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:24:56 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:24:56 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 05:24:57 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 05:24:57 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:24:57 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:24:57 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:24:57 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:24:57 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 05:24:58 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 05:24:58 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:24:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:24:58 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:24:58 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:24:58 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 05:24:59 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 05:24:59 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 05:25:00 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 05:25:00 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 05:25:00 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 05:25:01 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 05:25:01 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 05:25:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:25:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:25:01 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:25:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:25:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:25:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:25:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:25:01 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:25:01 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:25:01 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:25:01 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:25:01 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:25:01 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:25:01 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:25:01 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1845 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:25:01 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1845 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:25:01 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1845 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:25:01 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1845 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:25:01 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1845 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:25:01 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1845 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:25:01 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1845 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:25:01 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1845 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:25:06 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:25:06 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:25:06 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:25:06 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:25:06 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:25:06 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:25:06 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:25:06 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:25:06 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:25:06 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:25:06 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:25:06 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:25:06 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:25:06 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:25:06 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:25:06 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:25:06 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:25:06 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:25:06 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:25:06 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:25:06 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:25:06 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:25:06 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:25:06 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:25:06 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:25:06 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:25:06 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:25:06 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:25:06 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:25:06 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:25:06 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:25:06 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:25:06 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:25:06 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:25:06 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:25:06 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:25:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:25:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:25:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:25:06 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:25:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:25:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:25:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:25:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:25:06 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:25:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:25:06 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:25:06 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:25:06 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:25:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:25:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:25:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:25:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:25:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:25:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:25:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:25:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:25:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:25:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:25:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:25:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:25:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:25:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:25:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:25:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:25:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:25:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:25:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:25:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:25:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:25:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:25:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:25:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:25:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:25:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:25:06 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:25:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:25:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:25:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:25:06 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:25:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:25:06 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:25:06 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:25:06 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:25:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:25:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:25:11 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:25:11 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:25:11 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:25:11 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:25:11 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:25:11 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:25:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:25:12 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:25:12 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:25:12 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:25:12 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:25:12 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:25:12 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:25:12 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:25:12 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:25:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:25:12 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:25:12 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:25:12 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:25:12 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:25:12 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:25:12 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:25:12 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:25:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:25:12 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:25:12 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:25:12 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:25:12 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:25:12 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:25:12 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:25:12 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:25:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:25:12 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:25:12 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:25:12 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:25:12 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:25:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:25:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:25:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:25:12 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:25:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:25:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:25:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:25:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:25:12 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:25:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:25:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:25:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:25:12 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:25:12 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:25:12 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:25:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:25:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:25:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:25:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:25:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:25:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:25:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:25:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:25:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:25:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:25:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:25:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:25:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:25:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:25:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:25:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:25:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:25:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:25:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:25:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:25:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:25:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:25:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:25:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:25:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:25:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:25:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:25:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:25:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:25:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:25:12 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:25:12 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:25:12 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:25:12 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:25:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:25:12 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:25:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:25:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:25:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:25:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:25:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:25:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:25:12 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:25:12 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:25:12 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:25:12 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2025-04-27 05:25:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:25:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:25:12 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:25:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:25:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:25:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:25:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:25:13 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 05:25:13 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 05:25:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:25:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:25:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:25:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:25:14 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 05:25:14 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 05:25:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:25:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:25:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:25:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:25:15 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 05:25:15 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 05:25:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:25:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:25:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:25:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:25:16 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 05:25:16 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 05:25:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:25:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:25:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:25:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:25:17 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 05:25:17 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 05:25:18 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 05:25:18 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 05:25:19 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 05:25:19 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 05:25:20 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 05:25:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:25:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:25:20 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:25:20 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:25:20 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:25:20 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:25:20 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:25:20 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:25:20 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:25:20 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:25:20 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:25:20 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:25:20 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:25:20 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:25:20 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1821 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:25:20 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1821 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:25:20 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1821 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:25:20 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1821 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:25:20 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1821 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:25:20 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1821 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:25:20 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1822 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:25:20 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1822 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:25:20 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1822 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:25:20 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1822 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:25:20 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1822 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:25:20 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1822 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:25:20 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1822 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:25:20 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1822 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:25:25 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:25:25 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:25:25 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:25:25 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:25:25 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:25:25 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:25:25 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:25:25 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:25:25 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:25:25 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:25:25 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:25:25 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:25:25 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:25:25 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:25:25 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:25:25 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:25:25 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:25:25 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:25:25 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:25:25 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:25:25 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:25:25 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:25:25 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:25:25 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:25:25 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:25:25 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:25:25 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:25:25 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:25:25 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:25:25 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:25:25 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:25:25 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:25:25 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:25:25 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:25:25 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:25:25 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:25:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:25:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:25:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:25:25 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:25:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:25:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:25:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:25:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:25:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:25:25 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:25:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:25:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:25:25 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:25:25 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:25:25 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:25:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:25:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:25:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:25:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:25:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:25:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:25:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:25:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:25:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:25:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:25:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:25:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:25:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:25:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:25:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:25:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:25:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:25:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:25:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:25:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:25:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:25:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:25:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:25:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:25:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:25:25 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:25:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:25:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:25:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:25:25 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:25:25 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:25:25 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:25:25 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:25:25 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:25:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:25:30 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:25:30 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:25:30 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:25:30 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:25:30 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:25:30 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:25:30 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:25:30 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:25:30 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:25:30 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:25:30 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:25:30 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:25:30 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:25:30 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:25:30 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:25:30 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:25:30 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:25:30 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:25:30 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:25:30 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:25:30 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:25:30 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:25:30 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:25:30 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:25:30 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:25:30 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:25:30 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:25:30 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:25:30 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:25:30 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:25:30 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:25:30 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:25:30 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:25:30 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:25:30 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:25:30 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:25:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:25:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:25:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:25:30 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:25:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:25:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:25:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:25:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:25:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:25:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:25:30 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:25:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:25:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:25:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:25:30 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:25:30 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:25:30 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:25:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:25:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:25:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:25:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:25:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:25:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:25:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:25:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:25:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:25:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:25:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:25:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:25:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:25:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:25:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:25:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:25:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:25:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:25:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:25:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:25:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:25:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:25:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:25:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:25:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:25:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:25:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:25:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:25:30 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:25:31 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:25:31 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:25:31 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:25:31 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:25:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:25:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:25:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:25:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:25:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:25:31 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:25:31 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:25:31 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:25:31 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:25:31 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:25:31 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2025-04-27 05:25:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:25:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:25:31 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:25:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:25:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:25:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:25:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:25:32 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 05:25:32 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 05:25:32 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:25:32 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:25:32 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:25:32 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:25:33 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 05:25:33 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 05:25:33 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:25:33 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:25:33 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:25:33 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:25:33 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 05:25:34 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 05:25:34 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:25:34 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:25:34 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:25:34 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:25:34 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 05:25:35 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 05:25:35 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:25:35 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:25:35 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:25:35 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:25:35 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 05:25:36 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 05:25:36 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 05:25:37 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 05:25:37 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 05:25:38 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 05:25:38 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 05:25:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:25:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:25:39 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:25:39 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:25:39 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:25:39 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:25:39 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:25:39 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:25:39 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:25:39 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:25:39 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:25:39 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:25:39 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:25:39 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:25:39 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1824 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:25:39 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1824 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:25:39 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1824 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:25:39 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1824 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:25:39 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1824 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:25:39 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1824 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:25:39 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1825 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:25:39 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1825 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:25:39 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1825 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:25:39 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1825 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:25:39 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1825 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:25:39 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1825 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:25:39 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1825 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:25:39 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1825 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:25:44 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:25:44 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:25:44 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:25:44 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:25:44 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:25:44 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:25:44 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:25:44 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:25:44 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:25:44 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:25:44 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:25:44 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:25:44 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:25:44 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:25:44 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:25:44 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:25:44 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:25:44 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:25:44 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:25:44 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:25:44 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:25:44 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:25:44 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:25:44 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:25:44 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:25:44 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:25:44 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:25:44 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:25:44 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:25:44 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:25:44 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:25:44 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:25:44 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:25:44 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:25:44 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:25:44 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:25:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:25:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:25:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:25:44 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:25:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:25:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:25:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:25:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:25:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:25:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:25:44 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:25:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:25:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:25:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:25:44 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:25:44 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:25:44 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:25:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:25:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:25:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:25:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:25:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:25:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:25:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:25:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:25:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:25:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:25:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:25:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:25:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:25:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:25:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:25:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:25:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:25:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:25:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:25:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:25:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:25:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:25:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:25:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:25:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:25:44 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:25:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:25:44 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:25:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:25:44 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:25:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:25:44 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:25:44 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:25:44 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:25:44 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:25:49 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:25:49 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:25:49 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:25:49 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:25:49 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:25:49 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:25:49 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:25:49 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:25:49 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:25:49 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:25:49 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:25:49 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:25:49 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:25:49 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:25:49 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:25:49 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:25:49 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:25:49 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:25:49 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:25:49 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:25:49 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:25:49 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:25:49 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:25:49 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:25:49 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:25:49 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:25:49 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:25:49 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:25:49 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:25:49 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:25:49 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:25:49 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:25:49 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:25:49 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:25:49 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:25:49 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:25:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:25:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:25:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:25:49 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:25:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:25:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:25:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:25:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:25:49 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:25:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:25:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:25:49 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:25:49 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:25:49 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:25:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:25:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:25:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:25:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:25:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:25:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:25:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:25:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:25:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:25:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:25:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:25:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:25:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:25:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:25:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:25:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:25:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:25:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:25:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:25:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:25:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:25:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:25:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:25:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:25:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:25:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:25:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:25:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:25:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:25:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:25:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:25:49 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:25:49 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:25:49 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:25:49 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:25:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:25:49 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:25:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:25:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:25:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:25:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:25:49 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:25:49 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:25:49 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:25:49 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:25:49 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:25:49 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2025-04-27 05:25:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:25:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:25:50 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:25:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:25:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:25:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:25:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:25:50 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 05:25:51 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 05:25:51 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:25:51 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:25:51 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:25:51 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:25:51 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 05:25:52 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 05:25:52 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:25:52 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:25:52 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:25:52 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:25:52 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 05:25:53 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 05:25:53 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:25:53 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:25:53 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:25:53 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:25:53 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 05:25:54 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 05:25:54 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:25:54 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:25:54 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:25:54 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:25:54 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 05:25:55 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 05:25:55 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 05:25:55 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 05:25:56 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 05:25:56 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 05:25:57 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 05:25:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:25:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:25:57 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:25:57 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:25:57 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:25:57 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:25:57 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:25:57 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:25:57 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:25:57 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:25:57 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:25:57 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:25:57 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:25:57 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:25:57 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1830 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:25:57 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1830 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:25:57 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1830 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:25:57 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1830 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:25:57 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1830 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:25:57 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1830 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:25:57 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1830 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:26:02 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:26:02 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:26:02 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:26:02 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:26:02 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:26:02 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:26:02 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:26:02 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:26:02 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:26:02 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:26:02 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:26:02 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:26:02 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:26:02 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:26:02 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:26:02 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:26:02 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:26:02 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:26:02 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:26:02 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:26:02 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:26:02 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:26:02 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:26:02 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:26:02 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:26:02 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:26:02 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:26:02 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:26:02 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:26:02 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:26:02 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:26:02 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:26:02 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:26:02 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:26:02 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:26:02 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:26:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:26:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:26:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:26:02 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:26:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:26:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:26:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:26:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:26:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:26:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:26:02 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:26:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:26:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:26:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:26:02 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:26:02 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:26:02 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:26:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:26:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:26:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:26:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:26:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:26:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:26:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:26:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:26:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:26:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:26:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:26:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:26:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:26:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:26:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:26:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:26:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:26:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:26:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:26:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:26:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:26:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:26:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:26:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:26:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:26:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:26:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:26:02 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:26:02 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:26:02 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:26:02 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:26:02 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:26:02 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:26:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:26:07 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:26:07 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:26:07 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:26:07 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:26:07 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:26:07 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:26:07 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:26:07 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:26:07 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:26:07 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:26:07 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:26:07 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:26:07 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:26:07 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:26:07 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:26:07 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:26:07 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:26:07 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:26:07 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:26:07 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:26:07 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:26:07 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:26:07 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:26:07 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:26:07 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:26:07 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:26:07 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:26:07 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:26:07 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:26:07 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:26:07 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:26:07 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:26:07 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:26:07 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:26:07 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:26:07 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:26:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:26:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:26:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:26:07 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:26:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:26:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:26:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:26:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:26:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:26:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:26:07 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:26:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:26:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:26:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:26:07 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:26:07 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:26:07 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:26:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:26:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:26:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:26:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:26:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:26:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:26:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:26:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:26:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:26:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:26:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:26:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:26:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:26:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:26:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:26:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:26:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:26:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:26:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:26:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:26:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:26:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:26:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:26:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:26:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:26:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:26:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:26:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:26:07 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:26:08 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:26:08 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:26:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:26:08 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:26:08 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:26:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:26:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:26:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:26:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:26:08 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:26:08 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:26:08 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:26:08 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:26:08 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:26:08 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2025-04-27 05:26:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:26:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:26:08 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:26:08 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:26:08 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:26:08 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:26:08 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:26:09 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 05:26:09 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 05:26:09 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:26:09 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:26:09 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:26:09 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:26:10 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 05:26:10 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 05:26:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:26:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:26:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:26:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:26:11 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 05:26:11 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 05:26:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:26:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:26:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:26:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:26:12 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 05:26:12 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 05:26:12 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:26:12 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:26:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:26:12 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:26:13 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 05:26:13 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 05:26:14 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 05:26:14 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 05:26:15 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 05:26:15 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 05:26:16 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 05:26:16 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 05:26:17 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 05:26:17 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 05:26:17 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 05:26:18 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 05:26:18 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-27 05:26:19 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-27 05:26:19 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-27 05:26:20 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-27 05:26:20 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-27 05:26:21 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-27 05:26:21 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-27 05:26:22 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-27 05:26:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:26:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:26:22 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:26:22 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:26:22 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:26:22 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:26:22 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:26:22 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:26:22 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:26:22 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:26:22 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:26:22 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:26:22 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:26:22 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:26:22 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3095 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:26:22 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3095 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:26:22 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3095 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:26:22 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3095 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:26:22 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3095 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:26:22 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3095 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:26:22 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3095 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:26:27 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:26:27 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:26:27 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:26:27 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:26:27 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:26:27 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:26:27 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:26:27 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:26:27 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:26:27 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:26:27 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:26:27 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:26:27 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:26:27 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:26:27 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:26:27 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:26:27 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:26:27 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:26:27 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:26:27 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:26:27 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:26:27 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:26:27 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:26:27 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:26:27 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:26:27 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:26:27 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:26:27 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:26:27 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:26:27 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:26:27 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:26:27 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:26:27 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:26:27 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:26:27 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:26:27 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:26:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:26:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:26:27 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:26:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:26:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:26:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:26:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:26:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:26:27 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:26:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:26:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:26:27 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:26:27 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:26:27 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:26:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:26:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:26:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:26:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:26:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:26:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:26:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:26:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:26:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:26:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:26:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:26:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:26:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:26:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:26:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:26:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:26:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:26:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:26:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:26:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:26:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:26:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:26:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:26:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:26:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:26:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:26:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:26:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:26:27 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:26:27 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:26:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:26:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:26:27 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:26:27 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:26:27 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:26:27 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:26:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:26:32 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:26:32 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:26:32 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:26:32 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:26:32 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:26:32 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:26:32 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:26:32 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:26:32 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:26:32 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:26:32 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:26:32 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:26:32 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:26:32 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:26:32 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:26:32 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:26:32 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:26:32 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:26:32 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:26:32 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:26:32 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:26:32 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:26:32 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:26:32 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:26:32 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:26:32 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:26:32 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:26:32 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:26:32 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:26:32 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:26:32 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:26:32 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:26:32 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:26:32 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:26:32 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:26:32 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:26:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:26:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:26:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:26:32 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:26:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:26:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:26:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:26:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:26:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:26:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:26:32 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:26:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:26:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:26:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:26:32 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:26:32 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:26:32 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:26:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:26:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:26:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:26:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:26:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:26:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:26:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:26:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:26:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:26:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:26:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:26:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:26:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:26:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:26:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:26:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:26:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:26:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:26:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:26:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:26:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:26:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:26:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:26:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:26:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:26:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:26:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:26:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:26:32 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:26:33 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:26:33 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:26:33 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:26:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:26:33 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:26:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:26:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:26:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:26:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:26:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:26:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:26:33 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:26:33 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:26:33 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:26:33 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2025-04-27 05:26:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:26:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:26:33 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:26:33 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:26:33 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:26:33 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:26:33 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:26:33 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 05:26:34 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 05:26:34 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:26:34 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:26:34 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:26:34 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:26:34 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 05:26:35 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 05:26:35 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:26:35 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:26:35 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:26:35 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:26:35 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 05:26:36 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 05:26:36 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:26:36 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:26:36 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:26:36 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:26:36 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 05:26:37 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 05:26:37 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:26:37 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:26:37 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:26:37 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:26:37 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 05:26:38 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 05:26:38 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 05:26:39 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 05:26:39 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 05:26:40 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 05:26:40 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 05:26:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:26:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:26:41 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:26:41 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:26:41 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:26:41 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:26:41 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:26:41 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:26:41 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:26:41 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:26:41 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:26:41 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:26:41 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:26:41 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:26:46 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:26:46 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:26:46 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:26:46 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:26:46 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:26:46 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:26:46 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:26:46 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:26:46 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:26:46 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:26:46 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:26:46 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:26:46 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:26:46 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:26:46 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:26:46 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:26:46 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:26:46 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:26:46 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:26:46 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:26:46 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:26:46 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:26:46 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:26:46 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:26:46 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:26:46 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:26:46 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:26:46 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:26:46 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:26:46 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:26:46 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:26:46 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:26:46 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:26:46 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:26:46 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:26:46 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:26:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:26:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:26:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:26:46 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:26:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:26:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:26:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:26:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:26:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:26:46 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:26:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:26:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:26:46 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:26:46 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:26:46 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:26:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:26:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:26:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:26:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:26:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:26:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:26:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:26:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:26:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:26:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:26:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:26:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:26:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:26:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:26:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:26:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:26:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:26:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:26:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:26:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:26:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:26:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:26:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:26:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:26:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:26:46 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:26:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:26:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:26:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:26:46 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:26:46 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:26:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:26:46 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:26:46 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:26:46 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:26:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:26:51 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:26:51 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:26:51 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:26:51 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:26:51 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:26:51 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:26:51 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:26:51 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:26:51 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:26:51 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:26:51 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:26:51 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:26:51 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:26:51 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:26:51 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:26:51 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:26:51 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:26:51 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:26:51 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:26:51 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:26:51 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:26:51 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:26:51 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:26:51 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:26:51 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:26:51 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:26:51 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:26:51 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:26:51 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:26:51 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:26:51 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:26:51 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:26:51 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:26:51 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:26:51 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:26:51 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:26:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:26:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:26:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:26:51 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:26:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:26:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:26:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:26:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:26:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:26:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:26:51 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:26:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:26:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:26:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:26:51 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:26:51 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:26:51 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:26:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:26:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:26:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:26:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:26:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:26:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:26:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:26:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:26:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:26:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:26:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:26:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:26:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:26:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:26:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:26:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:26:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:26:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:26:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:26:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:26:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:26:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:26:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:26:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:26:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:26:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:26:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:26:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:26:51 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:26:51 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:26:51 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:26:51 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:26:51 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:26:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:26:51 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:26:51 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:26:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:26:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:26:51 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:26:51 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:26:51 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:26:51 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:26:52 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:26:52 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:26:52 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:26:52 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:26:52 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:26:52 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 05:26:53 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 05:26:53 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:26:53 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:26:53 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:26:53 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:26:53 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 05:26:54 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 05:26:54 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:26:54 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:26:54 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:26:54 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:26:54 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 05:26:54 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 05:26:55 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:26:55 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:26:55 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:26:55 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:26:55 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 05:26:55 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 05:26:56 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:26:56 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:26:56 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:26:56 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:26:56 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 05:26:56 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 05:26:57 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 05:26:57 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 05:26:58 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 05:26:58 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 05:26:59 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 05:26:59 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 05:27:00 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 05:27:00 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 05:27:01 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 05:27:01 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 05:27:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:27:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:27:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:27:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:27:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:27:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:27:01 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:27:01 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:27:01 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:27:01 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:27:01 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:27:01 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:27:01 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:27:01 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2262 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:27:01 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2262 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:27:01 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2262 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:27:01 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2262 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:27:01 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2262 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:27:01 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2262 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:27:01 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2262 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:27:06 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:27:06 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:27:06 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:27:06 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:27:06 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:27:06 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:27:06 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:27:06 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:27:06 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:27:06 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:27:06 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:27:06 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:27:06 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:27:06 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:27:06 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:27:06 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:27:06 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:27:06 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:27:06 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:27:06 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:27:06 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:27:06 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:27:06 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:27:06 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:27:06 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:27:06 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:27:06 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:27:06 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:27:06 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:27:06 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:27:06 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:27:06 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:27:06 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:27:06 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:27:06 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:27:06 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:27:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:27:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:27:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:27:06 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:27:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:27:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:27:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:27:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:27:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:27:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:27:06 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:27:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:27:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:27:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:27:06 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:27:06 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:27:06 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:27:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:27:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:27:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:27:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:27:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:27:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:27:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:27:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:27:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:27:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:27:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:27:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:27:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:27:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:27:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:27:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:27:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:27:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:27:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:27:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:27:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:27:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:27:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:27:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:27:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:27:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:27:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:27:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:27:06 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:27:06 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:27:06 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:27:06 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:27:06 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:27:06 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:27:06 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:27:11 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:27:11 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:27:11 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:27:11 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:27:11 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:27:11 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:27:11 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:27:11 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:27:11 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:27:11 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:27:11 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:27:11 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:27:11 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:27:11 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:27:11 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:27:11 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:27:11 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:27:11 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:27:11 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:27:11 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:27:11 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:27:11 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:27:11 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:27:11 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:27:11 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:27:11 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:27:11 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:27:11 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:27:11 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:27:11 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:27:11 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:27:11 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:27:11 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:27:11 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:27:11 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:27:11 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:27:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:27:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:27:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:27:11 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:27:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:27:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:27:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:27:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:27:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:27:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:27:11 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:27:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:27:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:27:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:27:11 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:27:11 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:27:11 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:27:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:27:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:27:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:27:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:27:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:27:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:27:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:27:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:27:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:27:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:27:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:27:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:27:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:27:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:27:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:27:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:27:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:27:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:27:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:27:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:27:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:27:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:27:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:27:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:27:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:27:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:27:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:27:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:27:11 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:27:12 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:27:12 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:27:12 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:27:12 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:27:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:27:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:27:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:27:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:27:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:27:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:27:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:27:12 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:27:12 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:27:12 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:27:12 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2025-04-27 05:27:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:27:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:27:12 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:27:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:27:12 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:27:12 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:27:12 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:27:13 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 05:27:13 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 05:27:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:27:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:27:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:27:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:27:14 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 05:27:14 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 05:27:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:27:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:27:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:27:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:27:15 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 05:27:15 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 05:27:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:27:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:27:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:27:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:27:16 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 05:27:16 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 05:27:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:27:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:27:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:27:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:27:17 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 05:27:17 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 05:27:18 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 05:27:18 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 05:27:18 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 05:27:19 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 05:27:19 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 05:27:20 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 05:27:20 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 05:27:21 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 05:27:21 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 05:27:22 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 05:27:22 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-27 05:27:23 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-27 05:27:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:27:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:27:23 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:27:23 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:27:23 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:27:23 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:27:23 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:27:23 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:27:23 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:27:23 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:27:23 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:27:23 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:27:23 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:27:23 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:27:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2463 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:27:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2463 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:27:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2463 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:27:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2463 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:27:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2463 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:27:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2463 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:27:28 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:27:28 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:27:28 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:27:28 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:27:28 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:27:28 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:27:28 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:27:28 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:27:28 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:27:28 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:27:28 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:27:28 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:27:28 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:27:28 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:27:28 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:27:28 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:27:28 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:27:28 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:27:28 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:27:28 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:27:28 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:27:28 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:27:28 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:27:28 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:27:28 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:27:28 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:27:28 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:27:28 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:27:28 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:27:28 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:27:28 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:27:28 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:27:28 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:27:28 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:27:28 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:27:28 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:27:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:27:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:27:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:27:28 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:27:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:27:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:27:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:27:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:27:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:27:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:27:28 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:27:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:27:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:27:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:27:28 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:27:28 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:27:28 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:27:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:27:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:27:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:27:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:27:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:27:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:27:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:27:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:27:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:27:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:27:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:27:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:27:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:27:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:27:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:27:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:27:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:27:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:27:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:27:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:27:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:27:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:27:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:27:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:27:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:27:28 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:27:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:27:28 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:27:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:27:28 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:27:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:27:28 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:27:28 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:27:28 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:27:28 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:27:33 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:27:33 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:27:33 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:27:33 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:27:33 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:27:33 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:27:33 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:27:33 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:27:33 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:27:33 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:27:33 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:27:33 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:27:33 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:27:33 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:27:33 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:27:33 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:27:33 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:27:33 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:27:33 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:27:33 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:27:33 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:27:33 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:27:33 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:27:33 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:27:33 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:27:33 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:27:33 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:27:33 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:27:33 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:27:33 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:27:33 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:27:33 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:27:33 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:27:33 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:27:33 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:27:33 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:27:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:27:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:27:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:27:33 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:27:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:27:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:27:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:27:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:27:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:27:33 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:27:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:27:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:27:33 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:27:33 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:27:33 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:27:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:27:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:27:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:27:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:27:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:27:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:27:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:27:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:27:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:27:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:27:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:27:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:27:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:27:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:27:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:27:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:27:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:27:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:27:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:27:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:27:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:27:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:27:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:27:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:27:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:27:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:27:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:27:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:27:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:27:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:27:33 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:27:33 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:27:33 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:27:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:27:33 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:27:33 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:27:34 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:27:34 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:27:34 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:27:34 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:27:34 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:27:34 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 05:27:35 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 05:27:35 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:27:35 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:27:35 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:27:35 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:27:35 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 05:27:36 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 05:27:36 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:27:36 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:27:36 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:27:36 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:27:36 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 05:27:37 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 05:27:37 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:27:37 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:27:37 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:27:37 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:27:37 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 05:27:38 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 05:27:38 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:27:38 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:27:38 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:27:38 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:27:38 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 05:27:39 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 05:27:39 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 05:27:40 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 05:27:40 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 05:27:41 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 05:27:41 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 05:27:41 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 05:27:42 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 05:27:42 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 05:27:43 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 05:27:43 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 05:27:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:27:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:27:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:27:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:27:43 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:27:43 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:27:43 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:27:43 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:27:43 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2259 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:27:43 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:27:43 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:27:43 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:27:43 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2259 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:27:43 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2259 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:27:43 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2259 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:27:43 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2259 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:27:43 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2259 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:27:48 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:27:48 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:27:48 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:27:48 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:27:48 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:27:48 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:27:49 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:27:49 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:27:49 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:27:49 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:27:49 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:27:49 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:27:49 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:27:49 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:27:49 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:27:49 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:27:49 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:27:49 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:27:49 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:27:49 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:27:49 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:27:49 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:27:49 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:27:49 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:27:49 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:27:49 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:27:49 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:27:49 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:27:49 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:27:49 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:27:49 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:27:49 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:27:49 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:27:49 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:27:49 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:27:49 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:27:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:27:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:27:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:27:49 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:27:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:27:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:27:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:27:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:27:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:27:49 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:27:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:27:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:27:49 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:27:49 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:27:49 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:27:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:27:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:27:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:27:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:27:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:27:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:27:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:27:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:27:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:27:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:27:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:27:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:27:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:27:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:27:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:27:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:27:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:27:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:27:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:27:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:27:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:27:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:27:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:27:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:27:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:27:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:27:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:27:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:27:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:27:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:27:49 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:27:49 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:27:49 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:27:49 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:27:49 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:27:49 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:27:49 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:27:54 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:27:54 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:27:54 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:27:54 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:27:54 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:27:54 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:27:54 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:27:54 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:27:54 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:27:54 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:27:54 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:27:54 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:27:54 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:27:54 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:27:54 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:27:54 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:27:54 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:27:54 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:27:54 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:27:54 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:27:54 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:27:54 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:27:54 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:27:54 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:27:54 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:27:54 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:27:54 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:27:54 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:27:54 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:27:54 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:27:54 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:27:54 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:27:54 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:27:54 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:27:54 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:27:54 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:27:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:27:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:27:54 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:27:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:27:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:27:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:27:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:27:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:27:54 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:27:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:27:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:27:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:27:54 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:27:54 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:27:54 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:27:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:27:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:27:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:27:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:27:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:27:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:27:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:27:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:27:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:27:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:27:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:27:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:27:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:27:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:27:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:27:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:27:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:27:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:27:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:27:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:27:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:27:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:27:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:27:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:27:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:27:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:27:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:27:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:27:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:27:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:27:54 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:27:54 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:27:54 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:27:54 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:27:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:27:54 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:27:55 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:27:55 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:27:55 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:27:55 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:27:55 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:27:55 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 05:27:56 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 05:27:56 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:27:56 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:27:56 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:27:56 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:27:56 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 05:27:56 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 05:27:57 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:27:57 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:27:57 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:27:57 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:27:57 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 05:27:57 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 05:27:58 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:27:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:27:58 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:27:58 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:27:58 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 05:27:58 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 05:27:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:27:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:27:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:27:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:27:59 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 05:27:59 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 05:28:00 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 05:28:00 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 05:28:01 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 05:28:01 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 05:28:02 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 05:28:02 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 05:28:03 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 05:28:03 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 05:28:04 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 05:28:04 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 05:28:05 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-27 05:28:05 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-27 05:28:06 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-27 05:28:06 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-27 05:28:06 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:28:06 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:28:06 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:28:06 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:28:06 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:28:06 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:28:06 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:28:06 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:28:06 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:28:06 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:28:06 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:28:11 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:28:11 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:28:11 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:28:11 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:28:11 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:28:11 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:28:11 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:28:11 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:28:11 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:28:11 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:28:11 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:28:11 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:28:11 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:28:11 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:28:11 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:28:11 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:28:11 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:28:11 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:28:11 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:28:11 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:28:11 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:28:11 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:28:11 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:28:11 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:28:11 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:28:11 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:28:11 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:28:11 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:28:11 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:28:11 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:28:11 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:28:11 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:28:11 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:28:11 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:28:11 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:28:11 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:28:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:28:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:28:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:28:11 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:28:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:28:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:28:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:28:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:28:11 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:28:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:28:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:28:11 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:28:11 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:28:11 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:28:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:28:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:28:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:28:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:28:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:28:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:28:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:28:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:28:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:28:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:28:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:28:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:28:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:28:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:28:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:28:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:28:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:28:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:28:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:28:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:28:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:28:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:28:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:28:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:28:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:28:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:28:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:28:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:28:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:28:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:28:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:28:11 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:28:12 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:28:12 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:28:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:28:12 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:28:12 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:28:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:28:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:28:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:28:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:28:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:28:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:28:12 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:28:12 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:28:12 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:28:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:28:12 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:28:12 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:28:12 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:28:13 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 05:28:13 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 05:28:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:28:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:28:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:28:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:28:14 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 05:28:14 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 05:28:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:28:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:28:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:28:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:28:15 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 05:28:15 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 05:28:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:28:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:28:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:28:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:28:15 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 05:28:16 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 05:28:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:28:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:28:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:28:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:28:16 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 05:28:17 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 05:28:17 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 05:28:18 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 05:28:18 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 05:28:19 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 05:28:19 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 05:28:20 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 05:28:20 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 05:28:21 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 05:28:21 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 05:28:22 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 05:28:22 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-27 05:28:23 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-27 05:28:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:28:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:28:23 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:28:23 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:28:23 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:28:23 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:28:23 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:28:23 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:28:23 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:28:23 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:28:23 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:28:23 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:28:23 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:28:28 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:28:28 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:28:28 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:28:28 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:28:28 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:28:28 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:28:28 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:28:28 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:28:28 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:28:28 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:28:28 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:28:28 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:28:28 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:28:28 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:28:28 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:28:28 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:28:28 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:28:28 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:28:28 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:28:28 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:28:28 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:28:28 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:28:28 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:28:28 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:28:28 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:28:28 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:28:28 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:28:28 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:28:28 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:28:28 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:28:28 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:28:28 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:28:28 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:28:28 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:28:28 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:28:28 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:28:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:28:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:28:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:28:28 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:28:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:28:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:28:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:28:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:28:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:28:28 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:28:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:28:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:28:28 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:28:28 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:28:28 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:28:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:28:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:28:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:28:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:28:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:28:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:28:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:28:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:28:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:28:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:28:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:28:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:28:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:28:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:28:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:28:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:28:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:28:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:28:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:28:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:28:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:28:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:28:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:28:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:28:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:28:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:28:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:28:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:28:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:28:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:28:28 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:28:28 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:28:28 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:28:28 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:28:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:28:28 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:28:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:28:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:28:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:28:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:28:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:28:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:28:28 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:28:28 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:28:29 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:28:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:28:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:28:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:28:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:28:29 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 05:28:30 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 05:28:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:28:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:28:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:28:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:28:30 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 05:28:31 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 05:28:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:28:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:28:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:28:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:28:31 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 05:28:32 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 05:28:32 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:28:32 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:28:32 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:28:32 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:28:32 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 05:28:33 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 05:28:33 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:28:33 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:28:33 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:28:33 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:28:33 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 05:28:33 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 05:28:34 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 05:28:34 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 05:28:35 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 05:28:35 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 05:28:36 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 05:28:36 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 05:28:37 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 05:28:37 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 05:28:38 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 05:28:38 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 05:28:39 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-27 05:28:39 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-27 05:28:40 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-27 05:28:40 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-27 05:28:41 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-27 05:28:41 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-27 05:28:42 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-27 05:28:42 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-27 05:28:43 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-27 05:28:43 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-27 05:28:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:28:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:28:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:28:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:28:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:28:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:28:43 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:28:43 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:28:43 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:28:43 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:28:43 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:28:43 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:28:43 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:28:48 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:28:48 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:28:48 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:28:48 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:28:48 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:28:48 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:28:48 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:28:48 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:28:48 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:28:48 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:28:48 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:28:48 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:28:48 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:28:48 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:28:48 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:28:48 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:28:48 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:28:48 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:28:48 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:28:48 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:28:48 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:28:48 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:28:48 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:28:48 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:28:48 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:28:48 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:28:48 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:28:48 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:28:48 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:28:48 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:28:48 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:28:48 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:28:48 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:28:48 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:28:48 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:28:48 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:28:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:28:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:28:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:28:48 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:28:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:28:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:28:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:28:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:28:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:28:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:28:48 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:28:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:28:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:28:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:28:48 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:28:48 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:28:48 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:28:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:28:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:28:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:28:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:28:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:28:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:28:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:28:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:28:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:28:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:28:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:28:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:28:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:28:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:28:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:28:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:28:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:28:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:28:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:28:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:28:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:28:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:28:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:28:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:28:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:28:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:28:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:28:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:28:48 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:28:49 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:28:49 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:28:49 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:28:49 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:28:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:28:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:28:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:28:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:28:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:28:49 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:28:49 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:28:49 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:28:49 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:28:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:28:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:28:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:28:49 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:28:49 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:28:49 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:28:49 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:28:49 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:28:49 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:28:49 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:28:49 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:28:49 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:28:49 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:28:54 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:28:54 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:28:54 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:28:54 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:28:54 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:28:54 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:28:54 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:28:54 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:28:54 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:28:54 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:28:54 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:28:54 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:28:54 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:28:54 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:28:54 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:28:54 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:28:54 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:28:54 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:28:54 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:28:54 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:28:54 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:28:54 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:28:54 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:28:54 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:28:54 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:28:54 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:28:54 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:28:54 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:28:54 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:28:54 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:28:54 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:28:54 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:28:54 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:28:54 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:28:54 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:28:54 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:28:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:28:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:28:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:28:54 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:28:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:28:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:28:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:28:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:28:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:28:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:28:54 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:28:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:28:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:28:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:28:54 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:28:54 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:28:54 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:28:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:28:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:28:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:28:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:28:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:28:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:28:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:28:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:28:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:28:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:28:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:28:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:28:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:28:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:28:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:28:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:28:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:28:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:28:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:28:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:28:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:28:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:28:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:28:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:28:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:28:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:28:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:28:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:28:54 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:28:54 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:28:54 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:28:54 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:28:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:28:54 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:28:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:28:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:28:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:28:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:28:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:28:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:28:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:28:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:28:55 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:28:55 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:28:55 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:28:55 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:28:55 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:28:55 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:28:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:28:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:28:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:28:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:28:55 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:28:55 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:28:55 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:28:55 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:28:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:28:55 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:28:55 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:28:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:28:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:28:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:28:55 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:28:55 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:28:55 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:28:55 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:28:55 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:28:55 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-27 05:28:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:28:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:28:55 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:28:55 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:28:55 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:28:55 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:28:55 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:28:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:28:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:28:55 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:28:55 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:28:55 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:28:55 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:28:55 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:28:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:28:55 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:28:55 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:28:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:28:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:28:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:28:55 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:28:55 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:28:55 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:28:55 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:28:55 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:28:55 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:28:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:28:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:28:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:28:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:28:55 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:28:55 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:28:55 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:28:55 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:28:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:28:55 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:28:55 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:28:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:28:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:28:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:28:55 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:28:55 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:28:55 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:28:55 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:28:55 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:28:55 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-27 05:28:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:28:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:28:55 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 05:28:56 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 05:28:56 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:28:56 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:28:56 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:28:56 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:28:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:28:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:28:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:28:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:28:56 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:28:56 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:28:56 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:28:56 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:28:56 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:28:56 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:28:56 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:28:56 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:28:56 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:28:56 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:28:56 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:28:56 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:28:56 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=483 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:28:56 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=483 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:28:56 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=483 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:28:56 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=483 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:28:56 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=483 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:28:56 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=483 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:28:56 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=483 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:28:56 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=483 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:29:01 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:29:01 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:29:01 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:29:01 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:29:01 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:29:01 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:29:01 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:29:01 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:29:01 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:29:01 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:29:01 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:29:01 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:29:01 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:29:01 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:29:01 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:29:01 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:29:01 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:29:01 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:29:01 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:29:01 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:29:01 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:29:01 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:29:01 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:29:01 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:29:01 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:29:01 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:29:01 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:29:01 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:29:01 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:29:01 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:29:01 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:29:01 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:29:01 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:29:01 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:29:01 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:29:01 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:29:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:29:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:29:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:29:01 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:29:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:29:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:29:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:29:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:29:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:29:01 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:29:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:29:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:29:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:29:01 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:29:01 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:29:01 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:29:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:29:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:29:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:29:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:29:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:29:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:29:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:29:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:29:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:29:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:29:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:29:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:29:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:29:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:29:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:29:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:29:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:29:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:29:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:29:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:29:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:29:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:29:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:29:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:29:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:29:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:29:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:29:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:29:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:29:01 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:29:02 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:29:02 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:29:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:29:02 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:29:02 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:29:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:29:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:29:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:29:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:29:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:29:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:29:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:29:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:29:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:29:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:29:02 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:29:02 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:29:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:29:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:29:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:29:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:29:02 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:29:02 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:29:02 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:29:02 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:29:02 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:29:03 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 05:29:03 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 05:29:03 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:29:03 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:29:03 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:29:03 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:29:04 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 05:29:04 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 05:29:04 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:29:04 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:29:04 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:29:04 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:29:05 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 05:29:05 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 05:29:05 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:29:05 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:29:05 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:29:05 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:29:06 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 05:29:06 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 05:29:06 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:29:06 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:29:06 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:29:06 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:29:06 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 05:29:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:29:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:29:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:29:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:29:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:29:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:29:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:29:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:29:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:29:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:29:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:29:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:29:07 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:29:07 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:29:07 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:29:07 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:29:07 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:29:07 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-27 05:29:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:29:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:29:07 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 05:29:07 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 05:29:08 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 05:29:08 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 05:29:09 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 05:29:09 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 05:29:10 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 05:29:10 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 05:29:11 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 05:29:11 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 05:29:12 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 05:29:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:29:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:29:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:29:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:29:12 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:29:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:29:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:29:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:29:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:29:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:29:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:29:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:29:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:29:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:29:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:29:12 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:29:12 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:29:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:29:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:29:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:29:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:29:12 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-27 05:29:13 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-27 05:29:13 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-27 05:29:14 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-27 05:29:14 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-27 05:29:15 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-27 05:29:15 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-27 05:29:16 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-27 05:29:16 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-27 05:29:16 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-27 05:29:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:29:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:29:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:29:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:29:17 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-27 05:29:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:29:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:29:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:29:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:29:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:29:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:29:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:29:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:29:17 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:29:17 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:29:17 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:29:17 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:29:17 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:29:17 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-27 05:29:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:29:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:29:17 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-27 05:29:18 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-27 05:29:18 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-27 05:29:19 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-27 05:29:19 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-27 05:29:20 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2025-04-27 05:29:20 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2025-04-27 05:29:21 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2025-04-27 05:29:21 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2025-04-27 05:29:22 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2025-04-27 05:29:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:29:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:29:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:29:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:29:22 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:29:22 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:29:22 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:29:22 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:29:22 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:29:22 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:29:22 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:29:22 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:29:22 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:29:22 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4451 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:29:22 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:29:22 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:29:22 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:29:22 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4451 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:29:22 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4451 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:29:27 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:29:27 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:29:27 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:29:27 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:29:27 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:29:27 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:29:27 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:29:27 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:29:27 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:29:27 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:29:27 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:29:27 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:29:27 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:29:27 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:29:27 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:29:27 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:29:27 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:29:27 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:29:27 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:29:27 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:29:27 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:29:27 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:29:27 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:29:27 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:29:27 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:29:27 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:29:27 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:29:27 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:29:27 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:29:27 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:29:27 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:29:27 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:29:27 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:29:27 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:29:27 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:29:27 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:29:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:29:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:29:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:29:27 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:29:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:29:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:29:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:29:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:29:27 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:29:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:29:27 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:29:27 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:29:27 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:29:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:29:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:29:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:29:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:29:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:29:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:29:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:29:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:29:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:29:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:29:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:29:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:29:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:29:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:29:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:29:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:29:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:29:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:29:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:29:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:29:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:29:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:29:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:29:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:29:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:29:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:29:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:29:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:29:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:29:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:29:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:29:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:29:27 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:29:28 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:29:28 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:29:28 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:29:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:29:28 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:29:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:29:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:29:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:29:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:29:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:29:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:29:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:29:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:29:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:29:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:29:28 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:29:28 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:29:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:29:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:29:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:29:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:29:28 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:29:28 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:29:28 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:29:28 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:29:28 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:29:29 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 05:29:29 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 05:29:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:29:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:29:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:29:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:29:29 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 05:29:30 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 05:29:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:29:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:29:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:29:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:29:30 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 05:29:31 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 05:29:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:29:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:29:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:29:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:29:31 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 05:29:32 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 05:29:32 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:29:32 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:29:32 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:29:32 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:29:32 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 05:29:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:29:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:29:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:29:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:29:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:29:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:29:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:29:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:29:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:29:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:29:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:29:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:29:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:29:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:29:33 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:29:33 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:29:33 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:29:33 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-27 05:29:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:29:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:29:33 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 05:29:33 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 05:29:34 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 05:29:34 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 05:29:35 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 05:29:35 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 05:29:36 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 05:29:36 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 05:29:37 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 05:29:37 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 05:29:38 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 05:29:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:29:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:29:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:29:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:29:38 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:29:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:29:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:29:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:29:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:29:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:29:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:29:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:29:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:29:38 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:29:38 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:29:38 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:29:38 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:29:38 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:29:38 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:29:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:29:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:29:38 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-27 05:29:39 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-27 05:29:39 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-27 05:29:39 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-27 05:29:40 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-27 05:29:40 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-27 05:29:41 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-27 05:29:41 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-27 05:29:42 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-27 05:29:42 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-27 05:29:43 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-27 05:29:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:29:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:29:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:29:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:29:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:29:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:29:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:29:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:29:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:29:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:29:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:29:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:29:43 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:29:43 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:29:43 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:29:43 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:29:43 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:29:43 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-27 05:29:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:29:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:29:43 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-27 05:29:44 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-27 05:29:44 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-27 05:29:45 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-27 05:29:45 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-27 05:29:46 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2025-04-27 05:29:46 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2025-04-27 05:29:47 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2025-04-27 05:29:47 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2025-04-27 05:29:48 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2025-04-27 05:29:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:29:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:29:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:29:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:29:48 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:29:48 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:29:48 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:29:48 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:29:48 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:29:48 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:29:48 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:29:48 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:29:48 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:29:48 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:29:48 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:29:48 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:29:48 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4449 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:29:48 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4449 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:29:48 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4449 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:29:48 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4449 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:29:48 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4449 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:29:48 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4449 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:29:48 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4449 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:29:48 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4449 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:29:53 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:29:53 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:29:53 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:29:53 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:29:53 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:29:53 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:29:53 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:29:53 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:29:53 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:29:53 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:29:53 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:29:53 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:29:53 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:29:53 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:29:53 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:29:53 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:29:53 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:29:53 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:29:53 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:29:53 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:29:53 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:29:53 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:29:53 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:29:53 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:29:53 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:29:53 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:29:53 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:29:53 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:29:53 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:29:53 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:29:53 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:29:53 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:29:53 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:29:53 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:29:53 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:29:53 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:29:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:29:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:29:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:29:53 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:29:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:29:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:29:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:29:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:29:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:29:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:29:53 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:29:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:29:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:29:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:29:53 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:29:53 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:29:53 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:29:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:29:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:29:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:29:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:29:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:29:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:29:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:29:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:29:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:29:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:29:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:29:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:29:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:29:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:29:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:29:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:29:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:29:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:29:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:29:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:29:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:29:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:29:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:29:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:29:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:29:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:29:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:29:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:29:53 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:29:53 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:29:53 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:29:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:29:53 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:29:53 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:29:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:29:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:29:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:29:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:29:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:29:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:29:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:29:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:29:53 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:29:53 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:29:53 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:29:53 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:29:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:29:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:29:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:29:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:29:54 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:29:54 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:29:54 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:29:54 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:29:54 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:29:54 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 05:29:55 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 05:29:55 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:29:55 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:29:55 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:29:55 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:29:55 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 05:29:56 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 05:29:56 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:29:56 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:29:56 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:29:56 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:29:56 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 05:29:57 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 05:29:57 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:29:57 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:29:57 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:29:57 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:29:57 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 05:29:58 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 05:29:58 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:29:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:29:58 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:29:58 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:29:58 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 05:29:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:29:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:29:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:29:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:29:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:29:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:29:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:29:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:29:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:29:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:29:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:29:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:29:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:29:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:29:59 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:29:59 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:29:59 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:29:59 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-27 05:29:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:29:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:29:59 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 05:29:59 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 05:30:00 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 05:30:00 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 05:30:00 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 05:30:01 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 05:30:01 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 05:30:02 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 05:30:02 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 05:30:03 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 05:30:03 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 05:30:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:30:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:30:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:30:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:30:04 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:30:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:30:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:30:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:30:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:30:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:30:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:30:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:30:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:30:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:30:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:30:04 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:30:04 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:30:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:30:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:30:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:30:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:30:04 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-27 05:30:04 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-27 05:30:05 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-27 05:30:05 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-27 05:30:06 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-27 05:30:06 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-27 05:30:07 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-27 05:30:07 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-27 05:30:08 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-27 05:30:08 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-27 05:30:09 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-27 05:30:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:30:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:30:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:30:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:30:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:30:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:30:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:30:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:30:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:30:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:30:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:30:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:30:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:30:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:30:09 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:30:09 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:30:09 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:30:09 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-27 05:30:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:30:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:30:09 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-27 05:30:10 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-27 05:30:10 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-27 05:30:11 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-27 05:30:11 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-27 05:30:11 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2025-04-27 05:30:12 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2025-04-27 05:30:12 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2025-04-27 05:30:13 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2025-04-27 05:30:13 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2025-04-27 05:30:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:30:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:30:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:30:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:30:14 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:30:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:30:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:30:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:30:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:30:14 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:30:14 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:30:14 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:30:14 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:30:14 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4472 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:30:14 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:30:14 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:30:14 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:30:14 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4472 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:30:14 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4472 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:30:14 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4472 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:30:14 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4472 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:30:19 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:30:19 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:30:19 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:30:19 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:30:19 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:30:19 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:30:19 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:30:19 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:30:19 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:30:19 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:30:19 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:30:19 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:30:19 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:30:19 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:30:19 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:30:19 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:30:19 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:30:19 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:30:19 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:30:19 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:30:19 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:30:19 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:30:19 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:30:19 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:30:19 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:30:19 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:30:19 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:30:19 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:30:19 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:30:19 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:30:19 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:30:19 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:30:19 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:30:19 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:30:19 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:30:19 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:30:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:30:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:30:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:30:19 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:30:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:30:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:30:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:30:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:30:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:30:19 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:30:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:30:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:30:19 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:30:19 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:30:19 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:30:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:30:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:30:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:30:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:30:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:30:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:30:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:30:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:30:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:30:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:30:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:30:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:30:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:30:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:30:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:30:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:30:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:30:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:30:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:30:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:30:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:30:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:30:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:30:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:30:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:30:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:30:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:30:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:30:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:30:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:30:19 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:30:19 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:30:19 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:30:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:30:19 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:30:19 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:30:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:30:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:30:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:30:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:30:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:30:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:30:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:30:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:30:19 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:30:19 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:30:19 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:30:19 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:30:19 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:30:19 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:30:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:30:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:30:20 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:30:20 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:30:20 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:30:20 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:30:20 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:30:20 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 05:30:21 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 05:30:21 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:30:21 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:30:21 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:30:21 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:30:21 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 05:30:22 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 05:30:22 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:30:22 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:30:22 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:30:22 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:30:22 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 05:30:23 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 05:30:23 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:30:23 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:30:23 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:30:23 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:30:23 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 05:30:24 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 05:30:24 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:30:24 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:30:24 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:30:24 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:30:24 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 05:30:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:30:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:30:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:30:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:30:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:30:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:30:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:30:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:30:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:30:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:30:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:30:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:30:24 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:30:24 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:30:24 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:30:24 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:30:24 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:30:24 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-27 05:30:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:30:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:30:25 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 05:30:25 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 05:30:26 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 05:30:26 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 05:30:26 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 05:30:27 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 05:30:27 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 05:30:28 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 05:30:28 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 05:30:29 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 05:30:29 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 05:30:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:30:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:30:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:30:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:30:29 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:30:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:30:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:30:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:30:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:30:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:30:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:30:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:30:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:30:29 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:30:29 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:30:29 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:30:29 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:30:29 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:30:29 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:30:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:30:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:30:30 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-27 05:30:30 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-27 05:30:31 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-27 05:30:31 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-27 05:30:32 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-27 05:30:32 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-27 05:30:33 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-27 05:30:33 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-27 05:30:34 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-27 05:30:34 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-27 05:30:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:30:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:30:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:30:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:30:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:30:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:30:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:30:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:30:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:30:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:30:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:30:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:30:35 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:30:35 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:30:35 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:30:35 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:30:35 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:30:35 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-27 05:30:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:30:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:30:35 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-27 05:30:35 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-27 05:30:36 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-27 05:30:36 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-27 05:30:36 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-27 05:30:37 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-27 05:30:37 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2025-04-27 05:30:38 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2025-04-27 05:30:38 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2025-04-27 05:30:39 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2025-04-27 05:30:39 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2025-04-27 05:30:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:30:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:30:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:30:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:30:40 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:30:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:30:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:30:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:30:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:30:40 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:30:40 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:30:40 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:30:40 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:30:40 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:30:40 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:30:40 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:30:40 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4430 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:30:40 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4430 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:30:40 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4430 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:30:40 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4430 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:30:40 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4430 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:30:40 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4430 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:30:45 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:30:45 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:30:45 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:30:45 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:30:45 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:30:45 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:30:45 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:30:45 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:30:45 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:30:45 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:30:45 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:30:45 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:30:45 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:30:45 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:30:45 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:30:45 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:30:45 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:30:45 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:30:45 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:30:45 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:30:45 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:30:45 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:30:45 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:30:45 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:30:45 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:30:45 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:30:45 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:30:45 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:30:45 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:30:45 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:30:45 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:30:45 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:30:45 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:30:45 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:30:45 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:30:45 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:30:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:30:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:30:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:30:45 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:30:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:30:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:30:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:30:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:30:45 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:30:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:30:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:30:45 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:30:45 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:30:45 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:30:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:30:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:30:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:30:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:30:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:30:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:30:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:30:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:30:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:30:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:30:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:30:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:30:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:30:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:30:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:30:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:30:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:30:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:30:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:30:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:30:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:30:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:30:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:30:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:30:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:30:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:30:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:30:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:30:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:30:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:30:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:30:45 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:30:45 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:30:45 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:30:45 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:30:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:30:45 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:30:45 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:30:45 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:30:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:30:45 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:30:45 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:30:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:30:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:30:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:30:45 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:30:45 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:30:45 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:30:45 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:30:45 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:30:45 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:30:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:30:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:30:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:30:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:30:45 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:30:45 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:30:45 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:30:45 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:30:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:30:45 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:30:45 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:30:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:30:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:30:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:30:45 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:30:45 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:30:45 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:30:45 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:30:45 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:30:45 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-27 05:30:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:30:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:30:46 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:30:46 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:30:46 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:30:46 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:30:46 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:30:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:30:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:30:46 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:30:46 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:30:46 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:30:46 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:30:46 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:30:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:30:46 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:30:46 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:30:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:30:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:30:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:30:46 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:30:46 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:30:46 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:30:46 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:30:46 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:30:46 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:30:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:30:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:30:46 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 05:30:46 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 05:30:47 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:30:47 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:30:47 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:30:47 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:30:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:30:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:30:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:30:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:30:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:30:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:30:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:30:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:30:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:30:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:30:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:30:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:30:47 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:30:47 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:30:47 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:30:47 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:30:47 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:30:47 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-27 05:30:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:30:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:30:47 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 05:30:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:30:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:30:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:30:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:30:47 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:30:47 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:30:47 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:30:47 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:30:47 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:30:47 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:30:47 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:30:47 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:30:47 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:30:47 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:30:47 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:30:47 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:30:47 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=584 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:30:47 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=584 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:30:47 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=584 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:30:47 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=584 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:30:47 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=584 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:30:47 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=584 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:30:47 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=584 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:30:52 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:30:52 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:30:52 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:30:52 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:30:52 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:30:52 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:30:52 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:30:52 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:30:52 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:30:52 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:30:52 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:30:52 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:30:52 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:30:52 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:30:52 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:30:52 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:30:52 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:30:52 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:30:52 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:30:52 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:30:52 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:30:52 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:30:52 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:30:52 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:30:52 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:30:52 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:30:52 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:30:52 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:30:52 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:30:52 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:30:52 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:30:52 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:30:52 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:30:52 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:30:52 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:30:52 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:30:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:30:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:30:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:30:52 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:30:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:30:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:30:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:30:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:30:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:30:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:30:52 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:30:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:30:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:30:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:30:52 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:30:52 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:30:52 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:30:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:30:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:30:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:30:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:30:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:30:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:30:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:30:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:30:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:30:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:30:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:30:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:30:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:30:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:30:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:30:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:30:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:30:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:30:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:30:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:30:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:30:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:30:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:30:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:30:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:30:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:30:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:30:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:30:52 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:30:53 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:30:53 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:30:53 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:30:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:30:53 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:30:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:30:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:30:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:30:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:30:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:30:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:30:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:30:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:30:53 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:30:53 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:30:53 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:30:53 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:30:53 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:30:53 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:30:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:30:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:30:53 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:30:53 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:30:53 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:30:53 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:30:53 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:30:54 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 05:30:54 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 05:30:54 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:30:54 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:30:54 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:30:54 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:30:55 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 05:30:55 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 05:30:55 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:30:55 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:30:55 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:30:55 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:30:56 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 05:30:56 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 05:30:56 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:30:56 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:30:56 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:30:56 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:30:57 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 05:30:57 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 05:30:57 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:30:57 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:30:57 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:30:57 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:30:58 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 05:30:58 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 05:30:59 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 05:30:59 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 05:30:59 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 05:31:00 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 05:31:00 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 05:31:01 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 05:31:01 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 05:31:02 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 05:31:02 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 05:31:03 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 05:31:03 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-27 05:31:04 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-27 05:31:04 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-27 05:31:05 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-27 05:31:05 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-27 05:31:06 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-27 05:31:06 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-27 05:31:07 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-27 05:31:07 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-27 05:31:08 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-27 05:31:08 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-27 05:31:09 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-27 05:31:09 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-27 05:31:09 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-27 05:31:10 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-27 05:31:10 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-27 05:31:11 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2025-04-27 05:31:11 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2025-04-27 05:31:12 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2025-04-27 05:31:12 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2025-04-27 05:31:13 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2025-04-27 05:31:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:31:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:31:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:31:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:31:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:31:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:31:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:31:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:31:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:31:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:31:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:31:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:31:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:31:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:31:13 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:31:13 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:31:13 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:31:13 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-27 05:31:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:31:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:31:13 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2025-04-27 05:31:14 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2025-04-27 05:31:14 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2025-04-27 05:31:15 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2025-04-27 05:31:15 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2025-04-27 05:31:16 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2025-04-27 05:31:16 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2025-04-27 05:31:17 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2025-04-27 05:31:17 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2025-04-27 05:31:18 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2025-04-27 05:31:18 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2025-04-27 05:31:19 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2025-04-27 05:31:19 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2025-04-27 05:31:19 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2025-04-27 05:31:20 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2025-04-27 05:31:20 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2025-04-27 05:31:21 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2025-04-27 05:31:21 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2025-04-27 05:31:22 [DEBUG] clck_gen.py:102 IND CLOCK 6324
2025-04-27 05:31:22 [DEBUG] clck_gen.py:102 IND CLOCK 6426
2025-04-27 05:31:23 [DEBUG] clck_gen.py:102 IND CLOCK 6528
2025-04-27 05:31:23 [DEBUG] clck_gen.py:102 IND CLOCK 6630
2025-04-27 05:31:24 [DEBUG] clck_gen.py:102 IND CLOCK 6732
2025-04-27 05:31:24 [DEBUG] clck_gen.py:102 IND CLOCK 6834
2025-04-27 05:31:25 [DEBUG] clck_gen.py:102 IND CLOCK 6936
2025-04-27 05:31:25 [DEBUG] clck_gen.py:102 IND CLOCK 7038
2025-04-27 05:31:26 [DEBUG] clck_gen.py:102 IND CLOCK 7140
2025-04-27 05:31:26 [DEBUG] clck_gen.py:102 IND CLOCK 7242
2025-04-27 05:31:27 [DEBUG] clck_gen.py:102 IND CLOCK 7344
2025-04-27 05:31:27 [DEBUG] clck_gen.py:102 IND CLOCK 7446
2025-04-27 05:31:28 [DEBUG] clck_gen.py:102 IND CLOCK 7548
2025-04-27 05:31:28 [DEBUG] clck_gen.py:102 IND CLOCK 7650
2025-04-27 05:31:29 [DEBUG] clck_gen.py:102 IND CLOCK 7752
2025-04-27 05:31:29 [DEBUG] clck_gen.py:102 IND CLOCK 7854
2025-04-27 05:31:29 [DEBUG] clck_gen.py:102 IND CLOCK 7956
2025-04-27 05:31:30 [DEBUG] clck_gen.py:102 IND CLOCK 8058
2025-04-27 05:31:30 [DEBUG] clck_gen.py:102 IND CLOCK 8160
2025-04-27 05:31:31 [DEBUG] clck_gen.py:102 IND CLOCK 8262
2025-04-27 05:31:31 [DEBUG] clck_gen.py:102 IND CLOCK 8364
2025-04-27 05:31:32 [DEBUG] clck_gen.py:102 IND CLOCK 8466
2025-04-27 05:31:32 [DEBUG] clck_gen.py:102 IND CLOCK 8568
2025-04-27 05:31:33 [DEBUG] clck_gen.py:102 IND CLOCK 8670
2025-04-27 05:31:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:31:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:31:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:31:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:31:33 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:31:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:31:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:31:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:31:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:31:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:31:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:31:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:31:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:31:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:31:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:31:33 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:31:33 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:31:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:31:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:31:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:31:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:31:33 [DEBUG] clck_gen.py:102 IND CLOCK 8772
2025-04-27 05:31:34 [DEBUG] clck_gen.py:102 IND CLOCK 8874
2025-04-27 05:31:34 [DEBUG] clck_gen.py:102 IND CLOCK 8976
2025-04-27 05:31:35 [DEBUG] clck_gen.py:102 IND CLOCK 9078
2025-04-27 05:31:35 [DEBUG] clck_gen.py:102 IND CLOCK 9180
2025-04-27 05:31:36 [DEBUG] clck_gen.py:102 IND CLOCK 9282
2025-04-27 05:31:36 [DEBUG] clck_gen.py:102 IND CLOCK 9384
2025-04-27 05:31:37 [DEBUG] clck_gen.py:102 IND CLOCK 9486
2025-04-27 05:31:37 [DEBUG] clck_gen.py:102 IND CLOCK 9588
2025-04-27 05:31:38 [DEBUG] clck_gen.py:102 IND CLOCK 9690
2025-04-27 05:31:38 [DEBUG] clck_gen.py:102 IND CLOCK 9792
2025-04-27 05:31:39 [DEBUG] clck_gen.py:102 IND CLOCK 9894
2025-04-27 05:31:39 [DEBUG] clck_gen.py:102 IND CLOCK 9996
2025-04-27 05:31:40 [DEBUG] clck_gen.py:102 IND CLOCK 10098
2025-04-27 05:31:40 [DEBUG] clck_gen.py:102 IND CLOCK 10200
2025-04-27 05:31:40 [DEBUG] clck_gen.py:102 IND CLOCK 10302
2025-04-27 05:31:41 [DEBUG] clck_gen.py:102 IND CLOCK 10404
2025-04-27 05:31:41 [DEBUG] clck_gen.py:102 IND CLOCK 10506
2025-04-27 05:31:42 [DEBUG] clck_gen.py:102 IND CLOCK 10608
2025-04-27 05:31:42 [DEBUG] clck_gen.py:102 IND CLOCK 10710
2025-04-27 05:31:43 [DEBUG] clck_gen.py:102 IND CLOCK 10812
2025-04-27 05:31:43 [DEBUG] clck_gen.py:102 IND CLOCK 10914
2025-04-27 05:31:44 [DEBUG] clck_gen.py:102 IND CLOCK 11016
2025-04-27 05:31:44 [DEBUG] clck_gen.py:102 IND CLOCK 11118
2025-04-27 05:31:45 [DEBUG] clck_gen.py:102 IND CLOCK 11220
2025-04-27 05:31:45 [DEBUG] clck_gen.py:102 IND CLOCK 11322
2025-04-27 05:31:46 [DEBUG] clck_gen.py:102 IND CLOCK 11424
2025-04-27 05:31:46 [DEBUG] clck_gen.py:102 IND CLOCK 11526
2025-04-27 05:31:47 [DEBUG] clck_gen.py:102 IND CLOCK 11628
2025-04-27 05:31:47 [DEBUG] clck_gen.py:102 IND CLOCK 11730
2025-04-27 05:31:48 [DEBUG] clck_gen.py:102 IND CLOCK 11832
2025-04-27 05:31:48 [DEBUG] clck_gen.py:102 IND CLOCK 11934
2025-04-27 05:31:48 [DEBUG] clck_gen.py:102 IND CLOCK 12036
2025-04-27 05:31:49 [DEBUG] clck_gen.py:102 IND CLOCK 12138
2025-04-27 05:31:49 [DEBUG] clck_gen.py:102 IND CLOCK 12240
2025-04-27 05:31:50 [DEBUG] clck_gen.py:102 IND CLOCK 12342
2025-04-27 05:31:50 [DEBUG] clck_gen.py:102 IND CLOCK 12444
2025-04-27 05:31:51 [DEBUG] clck_gen.py:102 IND CLOCK 12546
2025-04-27 05:31:51 [DEBUG] clck_gen.py:102 IND CLOCK 12648
2025-04-27 05:31:52 [DEBUG] clck_gen.py:102 IND CLOCK 12750
2025-04-27 05:31:52 [DEBUG] clck_gen.py:102 IND CLOCK 12852
2025-04-27 05:31:53 [DEBUG] clck_gen.py:102 IND CLOCK 12954
2025-04-27 05:31:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:31:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:31:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:31:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:31:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:31:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:31:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:31:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:31:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:31:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:31:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:31:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:31:53 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:31:53 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:31:53 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:31:53 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:31:53 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:31:53 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-27 05:31:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:31:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:31:53 [DEBUG] clck_gen.py:102 IND CLOCK 13056
2025-04-27 05:31:54 [DEBUG] clck_gen.py:102 IND CLOCK 13158
2025-04-27 05:31:54 [DEBUG] clck_gen.py:102 IND CLOCK 13260
2025-04-27 05:31:55 [DEBUG] clck_gen.py:102 IND CLOCK 13362
2025-04-27 05:31:55 [DEBUG] clck_gen.py:102 IND CLOCK 13464
2025-04-27 05:31:56 [DEBUG] clck_gen.py:102 IND CLOCK 13566
2025-04-27 05:31:56 [DEBUG] clck_gen.py:102 IND CLOCK 13668
2025-04-27 05:31:57 [DEBUG] clck_gen.py:102 IND CLOCK 13770
2025-04-27 05:31:57 [DEBUG] clck_gen.py:102 IND CLOCK 13872
2025-04-27 05:31:58 [DEBUG] clck_gen.py:102 IND CLOCK 13974
2025-04-27 05:31:58 [DEBUG] clck_gen.py:102 IND CLOCK 14076
2025-04-27 05:31:59 [DEBUG] clck_gen.py:102 IND CLOCK 14178
2025-04-27 05:31:59 [DEBUG] clck_gen.py:102 IND CLOCK 14280
2025-04-27 05:31:59 [DEBUG] clck_gen.py:102 IND CLOCK 14382
2025-04-27 05:32:00 [DEBUG] clck_gen.py:102 IND CLOCK 14484
2025-04-27 05:32:00 [DEBUG] clck_gen.py:102 IND CLOCK 14586
2025-04-27 05:32:01 [DEBUG] clck_gen.py:102 IND CLOCK 14688
2025-04-27 05:32:01 [DEBUG] clck_gen.py:102 IND CLOCK 14790
2025-04-27 05:32:02 [DEBUG] clck_gen.py:102 IND CLOCK 14892
2025-04-27 05:32:02 [DEBUG] clck_gen.py:102 IND CLOCK 14994
2025-04-27 05:32:03 [DEBUG] clck_gen.py:102 IND CLOCK 15096
2025-04-27 05:32:03 [DEBUG] clck_gen.py:102 IND CLOCK 15198
2025-04-27 05:32:04 [DEBUG] clck_gen.py:102 IND CLOCK 15300
2025-04-27 05:32:04 [DEBUG] clck_gen.py:102 IND CLOCK 15402
2025-04-27 05:32:05 [DEBUG] clck_gen.py:102 IND CLOCK 15504
2025-04-27 05:32:05 [DEBUG] clck_gen.py:102 IND CLOCK 15606
2025-04-27 05:32:06 [DEBUG] clck_gen.py:102 IND CLOCK 15708
2025-04-27 05:32:06 [DEBUG] clck_gen.py:102 IND CLOCK 15810
2025-04-27 05:32:07 [DEBUG] clck_gen.py:102 IND CLOCK 15912
2025-04-27 05:32:07 [DEBUG] clck_gen.py:102 IND CLOCK 16014
2025-04-27 05:32:08 [DEBUG] clck_gen.py:102 IND CLOCK 16116
2025-04-27 05:32:08 [DEBUG] clck_gen.py:102 IND CLOCK 16218
2025-04-27 05:32:08 [DEBUG] clck_gen.py:102 IND CLOCK 16320
2025-04-27 05:32:09 [DEBUG] clck_gen.py:102 IND CLOCK 16422
2025-04-27 05:32:09 [DEBUG] clck_gen.py:102 IND CLOCK 16524
2025-04-27 05:32:10 [DEBUG] clck_gen.py:102 IND CLOCK 16626
2025-04-27 05:32:10 [DEBUG] clck_gen.py:102 IND CLOCK 16728
2025-04-27 05:32:11 [DEBUG] clck_gen.py:102 IND CLOCK 16830
2025-04-27 05:32:11 [DEBUG] clck_gen.py:102 IND CLOCK 16932
2025-04-27 05:32:12 [DEBUG] clck_gen.py:102 IND CLOCK 17034
2025-04-27 05:32:12 [DEBUG] clck_gen.py:102 IND CLOCK 17136
2025-04-27 05:32:13 [DEBUG] clck_gen.py:102 IND CLOCK 17238
2025-04-27 05:32:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:32:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:32:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:32:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:32:13 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:32:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:32:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:32:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:32:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:32:13 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:32:13 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:32:13 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:32:13 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:32:13 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=17325 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:32:13 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:32:13 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:32:13 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:32:13 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=17325 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:32:13 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=17325 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:32:13 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=17325 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:32:13 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=17325 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:32:18 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:32:18 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:32:18 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:32:18 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:32:18 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:32:18 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:32:18 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:32:18 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:32:18 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:32:18 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:32:18 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:32:18 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:32:18 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:32:18 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:32:18 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:32:18 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:32:18 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:32:18 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:32:18 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:32:18 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:32:18 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:32:18 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:32:18 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:32:18 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:32:18 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:32:18 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:32:18 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:32:18 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:32:18 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:32:18 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:32:18 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:32:18 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:32:18 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:32:18 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:32:18 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:32:18 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:32:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:32:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:32:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:32:18 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:32:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:32:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:32:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:32:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:32:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:32:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:32:18 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:32:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:32:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:32:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:32:18 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:32:18 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:32:18 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:32:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:32:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:32:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:32:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:32:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:32:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:32:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:32:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:32:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:32:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:32:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:32:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:32:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:32:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:32:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:32:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:32:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:32:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:32:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:32:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:32:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:32:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:32:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:32:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:32:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:32:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:32:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:32:18 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:32:18 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:32:18 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:32:18 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:32:18 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:32:18 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:32:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:32:23 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:32:23 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:32:23 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:32:23 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:32:23 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:32:23 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:32:23 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:32:23 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:32:23 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:32:23 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:32:23 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:32:23 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:32:23 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:32:23 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:32:23 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:32:23 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:32:23 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:32:23 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:32:23 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:32:23 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:32:23 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:32:23 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:32:23 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:32:23 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:32:23 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:32:23 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:32:23 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:32:23 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:32:23 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:32:23 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:32:23 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:32:23 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:32:23 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:32:23 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:32:23 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:32:23 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:32:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:32:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:32:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:32:23 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:32:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:32:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:32:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:32:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:32:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:32:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:32:23 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:32:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:32:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:32:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:32:23 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:32:23 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:32:23 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:32:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:32:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:32:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:32:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:32:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:32:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:32:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:32:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:32:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:32:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:32:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:32:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:32:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:32:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:32:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:32:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:32:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:32:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:32:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:32:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:32:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:32:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:32:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:32:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:32:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:32:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:32:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:32:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:32:23 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:32:24 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:32:24 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:32:24 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:32:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:32:24 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:32:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:32:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:32:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:32:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:32:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:32:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:32:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:32:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:32:24 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:32:24 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:32:24 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:32:24 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:32:24 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:32:24 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:32:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:32:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:32:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:32:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:32:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:32:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:32:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:32:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:32:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:32:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:32:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:32:24 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:32:24 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:32:24 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:32:24 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:32:24 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:32:24 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:32:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:32:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:32:24 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:32:24 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:32:24 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:32:24 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:32:24 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:32:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:32:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:32:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:32:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:32:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:32:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:32:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:32:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:32:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:32:24 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:32:24 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:32:24 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:32:24 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:32:24 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:32:24 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:32:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:32:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:32:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:32:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:32:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:32:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:32:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:32:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:32:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:32:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:32:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:32:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:32:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:32:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:32:25 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:32:25 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:32:25 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:32:25 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:32:25 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:32:25 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-27 05:32:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:32:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:32:25 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 05:32:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:32:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:32:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:32:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:32:25 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:32:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:32:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:32:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:32:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:32:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:32:25 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:32:25 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:32:25 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:32:25 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:32:25 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:32:25 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-27 05:32:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:32:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:32:25 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 05:32:25 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:32:25 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:32:25 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:32:25 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:32:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:32:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:32:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:32:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:32:25 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:32:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:32:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:32:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:32:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:32:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:32:25 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:32:25 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:32:25 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:32:25 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:32:25 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:32:25 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-27 05:32:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:32:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:32:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:32:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:32:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:32:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:32:26 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:32:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:32:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:32:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:32:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:32:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:32:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:32:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:32:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:32:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:32:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:32:26 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:32:26 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:32:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:32:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:32:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:32:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:32:26 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 05:32:26 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 05:32:26 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:32:26 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:32:26 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:32:26 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:32:27 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 05:32:27 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 05:32:27 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:32:27 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:32:27 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:32:27 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:32:28 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 05:32:28 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 05:32:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:32:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:32:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:32:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:32:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:32:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:32:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:32:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:32:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:32:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:32:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:32:28 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:32:28 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:32:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:32:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:32:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:32:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:32:28 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:32:28 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:32:28 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:32:28 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:32:29 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 05:32:29 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 05:32:29 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 05:32:30 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 05:32:30 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 05:32:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:32:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:32:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:32:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:32:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:32:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:32:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:32:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:32:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:32:31 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:32:31 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:32:31 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:32:31 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:32:31 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:32:31 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:32:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:32:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:32:31 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 05:32:31 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 05:32:32 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 05:32:32 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 05:32:33 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 05:32:33 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 05:32:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:32:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:32:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:32:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:32:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:32:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:32:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:32:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:32:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:32:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:32:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:32:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:32:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:32:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:32:33 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:32:33 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:32:34 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:32:34 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-27 05:32:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:32:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:32:34 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 05:32:34 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-27 05:32:35 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-27 05:32:35 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-27 05:32:36 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-27 05:32:36 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-27 05:32:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:32:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:32:36 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:32:36 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:32:36 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:32:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:32:36 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:32:36 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:32:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:32:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:32:36 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:32:36 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:32:36 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:32:36 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:32:36 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:32:36 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-27 05:32:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:32:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:32:37 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-27 05:32:37 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-27 05:32:38 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-27 05:32:38 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-27 05:32:39 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-27 05:32:39 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-27 05:32:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:32:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:32:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:32:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:32:39 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:32:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:32:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:32:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:32:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:32:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:32:39 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:32:39 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:32:39 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:32:39 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:32:39 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:32:39 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-27 05:32:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:32:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:32:40 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-27 05:32:40 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-27 05:32:40 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-27 05:32:41 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-27 05:32:41 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-27 05:32:42 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2025-04-27 05:32:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:32:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:32:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:32:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:32:42 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:32:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:32:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:32:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:32:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:32:42 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:32:42 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:32:42 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:32:42 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:32:42 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:32:42 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:32:42 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4000 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:32:42 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:32:42 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4000 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:32:42 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4000 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:32:42 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4000 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:32:42 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4001 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:32:42 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4001 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:32:42 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4001 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:32:42 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4001 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:32:42 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4001 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:32:42 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4001 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:32:42 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4001 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:32:42 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4001 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:32:47 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:32:47 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:32:47 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:32:47 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:32:47 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:32:47 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:32:47 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:32:47 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:32:47 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:32:47 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:32:47 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:32:47 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:32:47 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:32:47 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:32:47 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:32:47 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:32:47 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:32:47 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:32:47 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:32:47 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:32:47 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:32:47 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:32:47 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:32:47 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:32:47 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:32:47 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:32:47 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:32:47 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:32:47 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:32:47 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:32:47 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:32:47 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:32:47 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:32:47 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:32:47 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:32:47 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:32:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:32:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:32:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:32:47 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:32:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:32:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:32:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:32:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:32:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:32:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:32:47 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:32:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:32:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:32:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:32:47 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:32:47 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:32:47 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:32:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:32:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:32:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:32:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:32:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:32:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:32:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:32:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:32:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:32:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:32:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:32:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:32:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:32:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:32:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:32:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:32:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:32:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:32:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:32:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:32:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:32:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:32:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:32:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:32:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:32:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:32:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:32:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:32:47 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:32:48 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:32:48 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:32:48 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:32:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:32:48 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:32:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:32:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:32:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:32:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:32:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:32:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:32:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:32:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:32:48 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:32:48 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:32:48 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:32:48 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:32:48 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:32:48 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:32:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:32:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:32:48 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:32:48 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:32:48 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:32:48 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:32:48 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:32:48 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 05:32:49 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 05:32:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:32:49 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:32:49 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:32:49 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:32:49 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 05:32:50 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 05:32:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:32:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:32:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:32:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:32:50 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 05:32:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:32:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:32:51 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:32:51 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:32:51 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:32:51 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:32:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:32:51 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:32:51 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:32:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:32:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:32:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:32:51 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:32:51 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:32:51 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:32:51 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:32:51 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:32:51 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-27 05:32:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:32:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:32:51 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 05:32:51 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:32:51 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:32:51 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:32:51 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:32:51 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 05:32:52 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 05:32:52 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:32:52 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:32:52 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:32:52 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:32:52 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 05:32:53 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 05:32:53 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 05:32:54 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 05:32:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:32:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:32:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:32:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:32:54 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:32:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:32:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:32:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:32:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:32:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:32:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:32:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:32:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:32:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:32:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:32:54 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:32:54 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:32:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:32:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:32:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:32:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:32:54 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 05:32:55 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 05:32:55 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 05:32:56 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 05:32:56 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 05:32:57 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 05:32:57 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 05:32:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:32:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:32:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:32:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:32:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:32:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:32:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:32:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:32:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:32:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:32:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:32:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:32:57 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:32:57 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:32:57 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:32:57 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:32:57 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:32:57 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-27 05:32:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:32:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:32:58 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 05:32:58 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-27 05:32:58 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-27 05:32:59 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-27 05:32:59 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-27 05:33:00 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-27 05:33:00 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-27 05:33:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:33:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:33:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:33:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:33:00 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:33:00 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:33:00 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:33:00 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:33:00 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:33:00 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:33:00 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:33:00 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:33:00 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:33:00 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:33:00 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:33:00 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:33:00 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2874 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:33:00 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2874 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:33:00 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2874 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:33:00 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2874 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:33:00 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2874 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:33:00 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2874 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:33:00 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2875 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:33:00 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2875 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:33:00 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2875 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:33:00 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2875 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:33:00 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2875 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:33:00 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2875 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:33:00 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2875 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:33:00 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2875 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:33:00 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2876 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:33:00 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2876 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:33:00 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2876 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:33:00 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2876 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:33:00 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2876 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:33:00 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2876 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:33:00 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2876 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:33:00 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=2876 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:33:05 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:33:05 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:33:05 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:33:05 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:33:05 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:33:05 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:33:05 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:33:05 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:33:05 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:33:05 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:33:05 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:33:05 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:33:05 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:33:05 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:33:05 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:33:05 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:33:05 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:33:05 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:33:05 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:33:05 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:33:05 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:33:05 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:33:05 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:33:05 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:33:05 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:33:05 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:33:05 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:33:05 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:33:05 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:33:05 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:33:05 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:33:05 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:33:05 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:33:05 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:33:05 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:33:05 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:33:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:33:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:33:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:33:05 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:33:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:33:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:33:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:33:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:33:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:33:05 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:33:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:33:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:33:05 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:33:05 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:33:05 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:33:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:33:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:33:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:33:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:33:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:33:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:33:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:33:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:33:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:33:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:33:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:33:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:33:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:33:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:33:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:33:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:33:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:33:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:33:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:33:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:33:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:33:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:33:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:33:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:33:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:33:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:33:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:33:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:33:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:33:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:33:06 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:33:06 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:33:06 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:33:06 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:33:06 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:33:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:33:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:33:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:33:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:33:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:33:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:33:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:33:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:33:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:33:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:33:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:33:06 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:33:06 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:33:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:33:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:33:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:33:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:33:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:33:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:33:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:33:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:33:06 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:33:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:33:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:33:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:33:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:33:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:33:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:33:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:33:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:33:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:33:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:33:06 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:33:06 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:33:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:33:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:33:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:33:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:33:07 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:33:07 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-27 05:33:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:33:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:33:07 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 05:33:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:33:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:33:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:33:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:33:07 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:33:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:33:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:33:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:33:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:33:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:33:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:33:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:33:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:33:07 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:33:07 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:33:07 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:33:07 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:33:07 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:33:07 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:33:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:33:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:33:07 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 05:33:08 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:33:08 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:33:08 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:33:08 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:33:08 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 05:33:08 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 05:33:09 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:33:09 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:33:09 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:33:09 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:33:09 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 05:33:09 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 05:33:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:33:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:33:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:33:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:33:10 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 05:33:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:33:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:33:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:33:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:33:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:33:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:33:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:33:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:33:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:33:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:33:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:33:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:33:10 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:33:10 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:33:10 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:33:10 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:33:10 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:33:10 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-27 05:33:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:33:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:33:10 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 05:33:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:33:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:33:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:33:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:33:11 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 05:33:11 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 05:33:12 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 05:33:12 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 05:33:13 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 05:33:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:33:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:33:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:33:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:33:13 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:33:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:33:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:33:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:33:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:33:13 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:33:13 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:33:13 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:33:13 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:33:13 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:33:13 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:33:13 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:33:13 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1605 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:33:13 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1605 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:33:13 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1605 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:33:13 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1605 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:33:13 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1605 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:33:13 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1605 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:33:13 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1605 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:33:18 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:33:18 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:33:18 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:33:18 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:33:18 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:33:18 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:33:18 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:33:18 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:33:18 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:33:18 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:33:18 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:33:18 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:33:18 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:33:18 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:33:18 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:33:18 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:33:18 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:33:18 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:33:18 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:33:18 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:33:18 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:33:18 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:33:18 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:33:18 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:33:18 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:33:18 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:33:18 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:33:18 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:33:18 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:33:18 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:33:18 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:33:18 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:33:18 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:33:18 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:33:18 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:33:18 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:33:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:33:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:33:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:33:18 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:33:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:33:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:33:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:33:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:33:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:33:18 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:33:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:33:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:33:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:33:18 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:33:18 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:33:18 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:33:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:33:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:33:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:33:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:33:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:33:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:33:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:33:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:33:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:33:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:33:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:33:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:33:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:33:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:33:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:33:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:33:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:33:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:33:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:33:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:33:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:33:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:33:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:33:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:33:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:33:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:33:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:33:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:33:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:33:18 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:33:19 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:33:19 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:33:19 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:33:19 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:33:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:33:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:33:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:33:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:33:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:33:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:33:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:33:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:33:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:33:19 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:33:19 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:33:19 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:33:19 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:33:19 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:33:19 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:33:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:33:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:33:19 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:33:19 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:33:19 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:33:19 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:33:19 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:33:19 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 05:33:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:33:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:33:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:33:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:33:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:33:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:33:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:33:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:33:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:33:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:33:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:33:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:33:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:33:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:33:20 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:33:20 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:33:20 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:33:20 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-27 05:33:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:33:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:33:20 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 05:33:20 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:33:20 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:33:20 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:33:20 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:33:20 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 05:33:21 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 05:33:21 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:33:21 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:33:21 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:33:21 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:33:21 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 05:33:22 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 05:33:22 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:33:22 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:33:22 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:33:22 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:33:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:33:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:33:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:33:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:33:22 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:33:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:33:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:33:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:33:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:33:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:33:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:33:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:33:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:33:22 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:33:22 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:33:22 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:33:22 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:33:22 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:33:22 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:33:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:33:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:33:22 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 05:33:23 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 05:33:23 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:33:23 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:33:23 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:33:23 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:33:23 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 05:33:24 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 05:33:24 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 05:33:25 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 05:33:25 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 05:33:26 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 05:33:26 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 05:33:27 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 05:33:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:33:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:33:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:33:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:33:27 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 05:33:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:33:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:33:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:33:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:33:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:33:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:33:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:33:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:33:27 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:33:27 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:33:27 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:33:27 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:33:27 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:33:27 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-27 05:33:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:33:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:33:28 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 05:33:28 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 05:33:29 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 05:33:29 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-27 05:33:30 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-27 05:33:30 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-27 05:33:30 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-27 05:33:31 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-27 05:33:31 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-27 05:33:32 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-27 05:33:32 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-27 05:33:33 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-27 05:33:33 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-27 05:33:34 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-27 05:33:34 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-27 05:33:35 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-27 05:33:35 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-27 05:33:36 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-27 05:33:36 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-27 05:33:37 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2025-04-27 05:33:37 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2025-04-27 05:33:38 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2025-04-27 05:33:38 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2025-04-27 05:33:39 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2025-04-27 05:33:39 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2025-04-27 05:33:40 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2025-04-27 05:33:40 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2025-04-27 05:33:40 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2025-04-27 05:33:41 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2025-04-27 05:33:41 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2025-04-27 05:33:42 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2025-04-27 05:33:42 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2025-04-27 05:33:43 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2025-04-27 05:33:43 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2025-04-27 05:33:44 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2025-04-27 05:33:44 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2025-04-27 05:33:45 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2025-04-27 05:33:45 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2025-04-27 05:33:46 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2025-04-27 05:33:46 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2025-04-27 05:33:47 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2025-04-27 05:33:47 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2025-04-27 05:33:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:33:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:33:47 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:33:47 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:33:47 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:33:47 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:33:47 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:33:47 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:33:47 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:33:47 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:33:47 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:33:47 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:33:47 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:33:47 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:33:47 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=6230 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:33:47 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=6230 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:33:47 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=6230 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:33:47 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=6230 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:33:47 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=6230 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:33:47 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=6230 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:33:47 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=6230 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:33:52 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:33:52 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:33:52 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:33:52 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:33:52 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:33:52 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:33:52 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:33:52 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:33:52 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:33:52 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:33:52 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:33:52 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:33:52 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:33:52 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:33:52 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:33:52 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:33:52 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:33:52 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:33:52 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:33:52 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:33:52 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:33:52 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:33:52 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:33:52 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:33:52 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:33:52 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:33:52 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:33:52 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:33:52 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:33:52 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:33:52 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:33:52 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:33:52 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:33:52 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:33:52 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:33:52 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:33:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:33:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:33:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:33:52 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:33:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:33:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:33:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:33:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:33:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:33:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:33:52 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:33:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:33:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:33:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:33:52 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:33:52 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:33:52 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:33:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:33:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:33:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:33:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:33:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:33:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:33:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:33:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:33:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:33:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:33:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:33:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:33:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:33:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:33:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:33:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:33:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:33:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:33:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:33:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:33:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:33:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:33:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:33:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:33:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:33:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:33:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:33:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:33:52 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:33:53 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:33:53 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:33:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:33:53 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:33:53 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:33:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:33:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:33:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:33:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:33:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:33:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:33:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:33:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:33:53 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:33:53 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:33:53 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:33:53 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:33:53 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:33:53 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:33:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:33:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:33:53 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:33:53 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:33:53 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:33:53 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:33:53 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:33:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:33:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:33:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:33:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:33:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:33:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:33:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:33:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:33:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:33:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:33:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:33:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:33:53 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:33:53 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:33:53 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:33:53 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:33:53 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:33:53 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-27 05:33:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:33:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:33:54 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 05:33:54 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 05:33:54 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:33:54 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:33:54 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:33:54 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:33:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:33:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:33:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:33:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:33:54 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:33:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:33:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:33:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:33:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:33:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:33:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:33:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:33:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:33:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:33:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:33:54 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:33:54 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:33:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:33:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:33:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:33:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:33:55 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 05:33:55 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 05:33:55 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:33:55 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:33:55 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:33:55 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:33:56 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 05:33:56 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 05:33:56 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:33:56 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:33:56 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:33:56 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:33:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:33:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:33:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:33:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:33:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:33:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:33:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:33:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:33:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:33:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:33:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:33:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:33:56 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:33:56 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:33:56 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:33:56 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:33:56 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:33:56 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-27 05:33:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:33:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:33:56 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 05:33:57 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 05:33:57 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:33:57 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:33:57 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:33:57 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:33:57 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 05:33:58 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 05:33:58 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 05:33:59 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 05:33:59 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 05:34:00 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 05:34:00 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 05:34:01 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 05:34:01 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 05:34:02 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 05:34:02 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 05:34:03 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 05:34:03 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-27 05:34:04 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-27 05:34:04 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-27 05:34:05 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-27 05:34:05 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-27 05:34:06 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-27 05:34:06 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-27 05:34:06 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-27 05:34:07 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-27 05:34:07 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-27 05:34:08 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-27 05:34:08 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-27 05:34:09 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-27 05:34:09 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-27 05:34:10 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-27 05:34:10 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-27 05:34:11 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2025-04-27 05:34:11 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2025-04-27 05:34:12 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2025-04-27 05:34:12 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2025-04-27 05:34:13 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2025-04-27 05:34:13 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2025-04-27 05:34:14 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2025-04-27 05:34:14 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2025-04-27 05:34:15 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2025-04-27 05:34:15 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2025-04-27 05:34:16 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2025-04-27 05:34:16 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2025-04-27 05:34:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:34:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:34:16 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:34:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:34:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:34:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:34:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:34:16 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:34:16 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:34:16 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:34:16 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:34:16 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:34:16 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:34:16 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:34:16 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=5189 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:34:16 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=5189 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:34:16 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=5189 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:34:16 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=5189 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:34:16 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=5189 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:34:21 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:34:21 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:34:21 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:34:21 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:34:21 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:34:21 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:34:21 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:34:21 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:34:21 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:34:21 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:34:21 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:34:21 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:34:21 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:34:21 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:34:21 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:34:21 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:34:21 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:34:21 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:34:21 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:34:21 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:34:21 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:34:21 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:34:21 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:34:21 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:34:21 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:34:21 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:34:21 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:34:21 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:34:21 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:34:21 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:34:21 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:34:21 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:34:21 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:34:21 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:34:21 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:34:21 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:34:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:34:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:34:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:34:21 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:34:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:34:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:34:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:34:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:34:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:34:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:34:21 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:34:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:34:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:34:21 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:34:21 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:34:21 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:34:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:34:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:34:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:34:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:34:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:34:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:34:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:34:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:34:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:34:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:34:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:34:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:34:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:34:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:34:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:34:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:34:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:34:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:34:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:34:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:34:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:34:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:34:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:34:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:34:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:34:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:34:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:34:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:34:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:34:21 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:34:22 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:34:22 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:34:22 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:34:22 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:34:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:34:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:34:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:34:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:34:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:34:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:34:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:34:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:34:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:34:22 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:34:22 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:34:22 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:34:22 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:34:22 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:34:22 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:34:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:34:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:34:22 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:34:22 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:34:22 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:34:22 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:34:22 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:34:23 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 05:34:23 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 05:34:23 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:34:23 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:34:23 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:34:23 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:34:24 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 05:34:24 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 05:34:24 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:34:24 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:34:24 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:34:24 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:34:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:34:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:34:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:34:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:34:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:34:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:34:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:34:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:34:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:34:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:34:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:34:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:34:24 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:34:24 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:34:24 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:34:24 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:34:25 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:34:25 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-27 05:34:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:34:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:34:25 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 05:34:25 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 05:34:25 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:34:25 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:34:25 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:34:25 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:34:26 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 05:34:26 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 05:34:26 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:34:26 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:34:26 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:34:26 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:34:27 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 05:34:27 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 05:34:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:34:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:34:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:34:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:34:27 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:34:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:34:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:34:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:34:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:34:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:34:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:34:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:34:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:34:27 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:34:27 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:34:27 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:34:27 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:34:27 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:34:27 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:34:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:34:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:34:28 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 05:34:28 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 05:34:29 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 05:34:29 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 05:34:30 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 05:34:30 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 05:34:31 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 05:34:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:34:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:34:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:34:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:34:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:34:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:34:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:34:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:34:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:34:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:34:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:34:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:34:31 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:34:31 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:34:31 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:34:31 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:34:31 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:34:31 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-27 05:34:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:34:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:34:31 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 05:34:31 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 05:34:32 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 05:34:32 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-27 05:34:33 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-27 05:34:33 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-27 05:34:34 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-27 05:34:34 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-27 05:34:35 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-27 05:34:35 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-27 05:34:36 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-27 05:34:36 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-27 05:34:37 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-27 05:34:37 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-27 05:34:38 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-27 05:34:38 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-27 05:34:39 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-27 05:34:39 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-27 05:34:40 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-27 05:34:40 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2025-04-27 05:34:41 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2025-04-27 05:34:41 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2025-04-27 05:34:42 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2025-04-27 05:34:42 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2025-04-27 05:34:43 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2025-04-27 05:34:43 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2025-04-27 05:34:43 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2025-04-27 05:34:44 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2025-04-27 05:34:44 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2025-04-27 05:34:45 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2025-04-27 05:34:45 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2025-04-27 05:34:46 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2025-04-27 05:34:46 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2025-04-27 05:34:47 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2025-04-27 05:34:47 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2025-04-27 05:34:48 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2025-04-27 05:34:48 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2025-04-27 05:34:49 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2025-04-27 05:34:49 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2025-04-27 05:34:50 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2025-04-27 05:34:50 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2025-04-27 05:34:51 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2025-04-27 05:34:51 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:34:51 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:34:51 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:34:51 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:34:51 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:34:51 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:34:51 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:34:51 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:34:51 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:34:51 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:34:51 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:34:51 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:34:51 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:34:51 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:34:56 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:34:56 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:34:56 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:34:56 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:34:56 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:34:56 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:34:56 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:34:56 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:34:56 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:34:56 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:34:56 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:34:56 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:34:56 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:34:56 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:34:56 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:34:56 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:34:56 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:34:56 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:34:56 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:34:56 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:34:56 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:34:56 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:34:56 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:34:56 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:34:56 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:34:56 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:34:56 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:34:56 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:34:56 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:34:56 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:34:56 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:34:56 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:34:56 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:34:56 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:34:56 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:34:56 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:34:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:34:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:34:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:34:56 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:34:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:34:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:34:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:34:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:34:56 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:34:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:34:56 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:34:56 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:34:56 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:34:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:34:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:34:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:34:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:34:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:34:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:34:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:34:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:34:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:34:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:34:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:34:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:34:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:34:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:34:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:34:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:34:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:34:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:34:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:34:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:34:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:34:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:34:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:34:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:34:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:34:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:34:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:34:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:34:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:34:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:34:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:34:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:34:56 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:34:56 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:34:56 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:34:56 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:34:56 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:34:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:34:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:34:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:34:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:34:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:34:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:34:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:34:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:34:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:34:56 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:34:56 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:34:56 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:34:56 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:34:56 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:34:56 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:34:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:34:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:34:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:34:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:34:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:34:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:34:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:34:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:34:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:34:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:34:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:34:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:34:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:34:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:34:57 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:34:57 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:34:57 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:34:57 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:34:57 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:34:57 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-27 05:34:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:34:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:34:57 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:34:57 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:34:57 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:34:57 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:34:57 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:34:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:34:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:34:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:34:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:34:57 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:34:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:34:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:34:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:34:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:34:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:34:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:34:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:34:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:34:57 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:34:57 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:34:57 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:34:57 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:34:57 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:34:57 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:34:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:34:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:34:57 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 05:34:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:34:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:34:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:34:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:34:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:34:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:34:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:34:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:34:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:34:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:34:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:34:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:34:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:34:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:34:58 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:34:58 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:34:58 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:34:58 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-27 05:34:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:34:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:34:58 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 05:34:58 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:34:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:34:58 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:34:58 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:34:58 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 05:34:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:34:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:34:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:34:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:34:58 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:34:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:34:58 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:34:58 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:34:58 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:34:58 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:34:58 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:34:58 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:34:58 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:34:58 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:34:58 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=533 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:34:58 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:34:58 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:34:58 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=533 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:34:58 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=533 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:34:58 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=533 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:34:58 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=534 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:34:58 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=534 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:34:58 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=534 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:34:58 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=534 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:34:58 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=534 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:34:58 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=534 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:34:58 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=534 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:34:58 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=534 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:34:58 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=535 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:34:58 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=535 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:34:58 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=535 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:34:58 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=535 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:34:58 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=535 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:34:58 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=535 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:34:58 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=535 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:34:58 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=535 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:35:03 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:35:03 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:35:03 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:35:03 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:35:03 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:35:03 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:35:03 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:35:03 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:35:03 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:35:03 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:35:03 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:35:03 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:35:03 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:35:03 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:35:03 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:35:03 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:35:03 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:35:03 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:35:03 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:35:03 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:35:03 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:35:03 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:35:03 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:35:03 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:35:03 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:35:03 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:35:03 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:35:03 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:35:03 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:35:03 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:35:03 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:35:03 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:35:03 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:35:03 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:35:03 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:35:03 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:35:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:35:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:35:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:35:03 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:35:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:35:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:35:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:35:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:35:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:35:03 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:35:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:35:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:35:03 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:35:03 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:35:03 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:35:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:35:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:35:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:35:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:35:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:35:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:35:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:35:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:35:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:35:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:35:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:35:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:35:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:35:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:35:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:35:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:35:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:35:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:35:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:35:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:35:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:35:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:35:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:35:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:35:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:35:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:35:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:35:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:35:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:35:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:35:03 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:35:04 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:35:04 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:35:04 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:35:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:35:04 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:35:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:35:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:35:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:35:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:35:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:35:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:35:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:35:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:35:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:35:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:35:04 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:35:04 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:35:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:35:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:35:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:35:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:35:04 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:35:04 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:35:04 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:35:04 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:35:04 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:35:05 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 05:35:05 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 05:35:05 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:35:05 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:35:05 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:35:05 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:35:06 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 05:35:06 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 05:35:06 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:35:06 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:35:06 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:35:06 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:35:07 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 05:35:07 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 05:35:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:35:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:35:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:35:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:35:08 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 05:35:08 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 05:35:08 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:35:08 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:35:08 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:35:08 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:35:09 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 05:35:09 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 05:35:09 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 05:35:10 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 05:35:10 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 05:35:11 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 05:35:11 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 05:35:12 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 05:35:12 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 05:35:13 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 05:35:13 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 05:35:14 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 05:35:14 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-27 05:35:15 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-27 05:35:15 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-27 05:35:16 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-27 05:35:16 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-27 05:35:17 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-27 05:35:17 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-27 05:35:18 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-27 05:35:18 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-27 05:35:18 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-27 05:35:19 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-27 05:35:19 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-27 05:35:20 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-27 05:35:20 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-27 05:35:21 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-27 05:35:21 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-27 05:35:22 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2025-04-27 05:35:22 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2025-04-27 05:35:23 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2025-04-27 05:35:23 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2025-04-27 05:35:24 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2025-04-27 05:35:24 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2025-04-27 05:35:25 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2025-04-27 05:35:25 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2025-04-27 05:35:26 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2025-04-27 05:35:26 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2025-04-27 05:35:27 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2025-04-27 05:35:27 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2025-04-27 05:35:28 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2025-04-27 05:35:28 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2025-04-27 05:35:28 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2025-04-27 05:35:29 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2025-04-27 05:35:29 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2025-04-27 05:35:30 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2025-04-27 05:35:30 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2025-04-27 05:35:31 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2025-04-27 05:35:31 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2025-04-27 05:35:32 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2025-04-27 05:35:32 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2025-04-27 05:35:33 [DEBUG] clck_gen.py:102 IND CLOCK 6324
2025-04-27 05:35:33 [DEBUG] clck_gen.py:102 IND CLOCK 6426
2025-04-27 05:35:34 [DEBUG] clck_gen.py:102 IND CLOCK 6528
2025-04-27 05:35:34 [DEBUG] clck_gen.py:102 IND CLOCK 6630
2025-04-27 05:35:35 [DEBUG] clck_gen.py:102 IND CLOCK 6732
2025-04-27 05:35:35 [DEBUG] clck_gen.py:102 IND CLOCK 6834
2025-04-27 05:35:36 [DEBUG] clck_gen.py:102 IND CLOCK 6936
2025-04-27 05:35:36 [DEBUG] clck_gen.py:102 IND CLOCK 7038
2025-04-27 05:35:37 [DEBUG] clck_gen.py:102 IND CLOCK 7140
2025-04-27 05:35:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:35:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:35:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:35:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:35:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:35:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:35:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:35:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:35:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:35:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:35:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:35:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:35:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:35:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:35:37 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:35:37 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:35:37 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:35:37 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-27 05:35:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:35:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:35:37 [DEBUG] clck_gen.py:102 IND CLOCK 7242
2025-04-27 05:35:38 [DEBUG] clck_gen.py:102 IND CLOCK 7344
2025-04-27 05:35:38 [DEBUG] clck_gen.py:102 IND CLOCK 7446
2025-04-27 05:35:38 [DEBUG] clck_gen.py:102 IND CLOCK 7548
2025-04-27 05:35:39 [DEBUG] clck_gen.py:102 IND CLOCK 7650
2025-04-27 05:35:39 [DEBUG] clck_gen.py:102 IND CLOCK 7752
2025-04-27 05:35:40 [DEBUG] clck_gen.py:102 IND CLOCK 7854
2025-04-27 05:35:40 [DEBUG] clck_gen.py:102 IND CLOCK 7956
2025-04-27 05:35:41 [DEBUG] clck_gen.py:102 IND CLOCK 8058
2025-04-27 05:35:41 [DEBUG] clck_gen.py:102 IND CLOCK 8160
2025-04-27 05:35:42 [DEBUG] clck_gen.py:102 IND CLOCK 8262
2025-04-27 05:35:42 [DEBUG] clck_gen.py:102 IND CLOCK 8364
2025-04-27 05:35:43 [DEBUG] clck_gen.py:102 IND CLOCK 8466
2025-04-27 05:35:43 [DEBUG] clck_gen.py:102 IND CLOCK 8568
2025-04-27 05:35:44 [DEBUG] clck_gen.py:102 IND CLOCK 8670
2025-04-27 05:35:44 [DEBUG] clck_gen.py:102 IND CLOCK 8772
2025-04-27 05:35:45 [DEBUG] clck_gen.py:102 IND CLOCK 8874
2025-04-27 05:35:45 [DEBUG] clck_gen.py:102 IND CLOCK 8976
2025-04-27 05:35:46 [DEBUG] clck_gen.py:102 IND CLOCK 9078
2025-04-27 05:35:46 [DEBUG] clck_gen.py:102 IND CLOCK 9180
2025-04-27 05:35:47 [DEBUG] clck_gen.py:102 IND CLOCK 9282
2025-04-27 05:35:47 [DEBUG] clck_gen.py:102 IND CLOCK 9384
2025-04-27 05:35:48 [DEBUG] clck_gen.py:102 IND CLOCK 9486
2025-04-27 05:35:48 [DEBUG] clck_gen.py:102 IND CLOCK 9588
2025-04-27 05:35:48 [DEBUG] clck_gen.py:102 IND CLOCK 9690
2025-04-27 05:35:49 [DEBUG] clck_gen.py:102 IND CLOCK 9792
2025-04-27 05:35:49 [DEBUG] clck_gen.py:102 IND CLOCK 9894
2025-04-27 05:35:50 [DEBUG] clck_gen.py:102 IND CLOCK 9996
2025-04-27 05:35:50 [DEBUG] clck_gen.py:102 IND CLOCK 10098
2025-04-27 05:35:51 [DEBUG] clck_gen.py:102 IND CLOCK 10200
2025-04-27 05:35:51 [DEBUG] clck_gen.py:102 IND CLOCK 10302
2025-04-27 05:35:52 [DEBUG] clck_gen.py:102 IND CLOCK 10404
2025-04-27 05:35:52 [DEBUG] clck_gen.py:102 IND CLOCK 10506
2025-04-27 05:35:53 [DEBUG] clck_gen.py:102 IND CLOCK 10608
2025-04-27 05:35:53 [DEBUG] clck_gen.py:102 IND CLOCK 10710
2025-04-27 05:35:54 [DEBUG] clck_gen.py:102 IND CLOCK 10812
2025-04-27 05:35:54 [DEBUG] clck_gen.py:102 IND CLOCK 10914
2025-04-27 05:35:55 [DEBUG] clck_gen.py:102 IND CLOCK 11016
2025-04-27 05:35:55 [DEBUG] clck_gen.py:102 IND CLOCK 11118
2025-04-27 05:35:56 [DEBUG] clck_gen.py:102 IND CLOCK 11220
2025-04-27 05:35:56 [DEBUG] clck_gen.py:102 IND CLOCK 11322
2025-04-27 05:35:57 [DEBUG] clck_gen.py:102 IND CLOCK 11424
2025-04-27 05:35:57 [DEBUG] clck_gen.py:102 IND CLOCK 11526
2025-04-27 05:35:58 [DEBUG] clck_gen.py:102 IND CLOCK 11628
2025-04-27 05:35:58 [DEBUG] clck_gen.py:102 IND CLOCK 11730
2025-04-27 05:35:58 [DEBUG] clck_gen.py:102 IND CLOCK 11832
2025-04-27 05:35:59 [DEBUG] clck_gen.py:102 IND CLOCK 11934
2025-04-27 05:35:59 [DEBUG] clck_gen.py:102 IND CLOCK 12036
2025-04-27 05:36:00 [DEBUG] clck_gen.py:102 IND CLOCK 12138
2025-04-27 05:36:00 [DEBUG] clck_gen.py:102 IND CLOCK 12240
2025-04-27 05:36:01 [DEBUG] clck_gen.py:102 IND CLOCK 12342
2025-04-27 05:36:01 [DEBUG] clck_gen.py:102 IND CLOCK 12444
2025-04-27 05:36:02 [DEBUG] clck_gen.py:102 IND CLOCK 12546
2025-04-27 05:36:02 [DEBUG] clck_gen.py:102 IND CLOCK 12648
2025-04-27 05:36:03 [DEBUG] clck_gen.py:102 IND CLOCK 12750
2025-04-27 05:36:03 [DEBUG] clck_gen.py:102 IND CLOCK 12852
2025-04-27 05:36:04 [DEBUG] clck_gen.py:102 IND CLOCK 12954
2025-04-27 05:36:04 [DEBUG] clck_gen.py:102 IND CLOCK 13056
2025-04-27 05:36:05 [DEBUG] clck_gen.py:102 IND CLOCK 13158
2025-04-27 05:36:05 [DEBUG] clck_gen.py:102 IND CLOCK 13260
2025-04-27 05:36:06 [DEBUG] clck_gen.py:102 IND CLOCK 13362
2025-04-27 05:36:06 [DEBUG] clck_gen.py:102 IND CLOCK 13464
2025-04-27 05:36:07 [DEBUG] clck_gen.py:102 IND CLOCK 13566
2025-04-27 05:36:07 [DEBUG] clck_gen.py:102 IND CLOCK 13668
2025-04-27 05:36:08 [DEBUG] clck_gen.py:102 IND CLOCK 13770
2025-04-27 05:36:08 [DEBUG] clck_gen.py:102 IND CLOCK 13872
2025-04-27 05:36:08 [DEBUG] clck_gen.py:102 IND CLOCK 13974
2025-04-27 05:36:09 [DEBUG] clck_gen.py:102 IND CLOCK 14076
2025-04-27 05:36:09 [DEBUG] clck_gen.py:102 IND CLOCK 14178
2025-04-27 05:36:10 [DEBUG] clck_gen.py:102 IND CLOCK 14280
2025-04-27 05:36:10 [DEBUG] clck_gen.py:102 IND CLOCK 14382
2025-04-27 05:36:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:36:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:36:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:36:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:36:11 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:36:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:36:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:36:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:36:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:36:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:36:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:36:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:36:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:36:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:36:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:36:11 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:36:11 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:36:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:36:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:36:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:36:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:36:11 [DEBUG] clck_gen.py:102 IND CLOCK 14484
2025-04-27 05:36:11 [DEBUG] clck_gen.py:102 IND CLOCK 14586
2025-04-27 05:36:12 [DEBUG] clck_gen.py:102 IND CLOCK 14688
2025-04-27 05:36:12 [DEBUG] clck_gen.py:102 IND CLOCK 14790
2025-04-27 05:36:13 [DEBUG] clck_gen.py:102 IND CLOCK 14892
2025-04-27 05:36:13 [DEBUG] clck_gen.py:102 IND CLOCK 14994
2025-04-27 05:36:14 [DEBUG] clck_gen.py:102 IND CLOCK 15096
2025-04-27 05:36:14 [DEBUG] clck_gen.py:102 IND CLOCK 15198
2025-04-27 05:36:15 [DEBUG] clck_gen.py:102 IND CLOCK 15300
2025-04-27 05:36:15 [DEBUG] clck_gen.py:102 IND CLOCK 15402
2025-04-27 05:36:16 [DEBUG] clck_gen.py:102 IND CLOCK 15504
2025-04-27 05:36:16 [DEBUG] clck_gen.py:102 IND CLOCK 15606
2025-04-27 05:36:17 [DEBUG] clck_gen.py:102 IND CLOCK 15708
2025-04-27 05:36:17 [DEBUG] clck_gen.py:102 IND CLOCK 15810
2025-04-27 05:36:18 [DEBUG] clck_gen.py:102 IND CLOCK 15912
2025-04-27 05:36:18 [DEBUG] clck_gen.py:102 IND CLOCK 16014
2025-04-27 05:36:18 [DEBUG] clck_gen.py:102 IND CLOCK 16116
2025-04-27 05:36:19 [DEBUG] clck_gen.py:102 IND CLOCK 16218
2025-04-27 05:36:19 [DEBUG] clck_gen.py:102 IND CLOCK 16320
2025-04-27 05:36:20 [DEBUG] clck_gen.py:102 IND CLOCK 16422
2025-04-27 05:36:20 [DEBUG] clck_gen.py:102 IND CLOCK 16524
2025-04-27 05:36:21 [DEBUG] clck_gen.py:102 IND CLOCK 16626
2025-04-27 05:36:21 [DEBUG] clck_gen.py:102 IND CLOCK 16728
2025-04-27 05:36:22 [DEBUG] clck_gen.py:102 IND CLOCK 16830
2025-04-27 05:36:22 [DEBUG] clck_gen.py:102 IND CLOCK 16932
2025-04-27 05:36:23 [DEBUG] clck_gen.py:102 IND CLOCK 17034
2025-04-27 05:36:23 [DEBUG] clck_gen.py:102 IND CLOCK 17136
2025-04-27 05:36:24 [DEBUG] clck_gen.py:102 IND CLOCK 17238
2025-04-27 05:36:24 [DEBUG] clck_gen.py:102 IND CLOCK 17340
2025-04-27 05:36:25 [DEBUG] clck_gen.py:102 IND CLOCK 17442
2025-04-27 05:36:25 [DEBUG] clck_gen.py:102 IND CLOCK 17544
2025-04-27 05:36:26 [DEBUG] clck_gen.py:102 IND CLOCK 17646
2025-04-27 05:36:26 [DEBUG] clck_gen.py:102 IND CLOCK 17748
2025-04-27 05:36:27 [DEBUG] clck_gen.py:102 IND CLOCK 17850
2025-04-27 05:36:27 [DEBUG] clck_gen.py:102 IND CLOCK 17952
2025-04-27 05:36:28 [DEBUG] clck_gen.py:102 IND CLOCK 18054
2025-04-27 05:36:28 [DEBUG] clck_gen.py:102 IND CLOCK 18156
2025-04-27 05:36:29 [DEBUG] clck_gen.py:102 IND CLOCK 18258
2025-04-27 05:36:29 [DEBUG] clck_gen.py:102 IND CLOCK 18360
2025-04-27 05:36:29 [DEBUG] clck_gen.py:102 IND CLOCK 18462
2025-04-27 05:36:30 [DEBUG] clck_gen.py:102 IND CLOCK 18564
2025-04-27 05:36:30 [DEBUG] clck_gen.py:102 IND CLOCK 18666
2025-04-27 05:36:31 [DEBUG] clck_gen.py:102 IND CLOCK 18768
2025-04-27 05:36:31 [DEBUG] clck_gen.py:102 IND CLOCK 18870
2025-04-27 05:36:32 [DEBUG] clck_gen.py:102 IND CLOCK 18972
2025-04-27 05:36:32 [DEBUG] clck_gen.py:102 IND CLOCK 19074
2025-04-27 05:36:33 [DEBUG] clck_gen.py:102 IND CLOCK 19176
2025-04-27 05:36:33 [DEBUG] clck_gen.py:102 IND CLOCK 19278
2025-04-27 05:36:34 [DEBUG] clck_gen.py:102 IND CLOCK 19380
2025-04-27 05:36:34 [DEBUG] clck_gen.py:102 IND CLOCK 19482
2025-04-27 05:36:35 [DEBUG] clck_gen.py:102 IND CLOCK 19584
2025-04-27 05:36:35 [DEBUG] clck_gen.py:102 IND CLOCK 19686
2025-04-27 05:36:36 [DEBUG] clck_gen.py:102 IND CLOCK 19788
2025-04-27 05:36:36 [DEBUG] clck_gen.py:102 IND CLOCK 19890
2025-04-27 05:36:37 [DEBUG] clck_gen.py:102 IND CLOCK 19992
2025-04-27 05:36:37 [DEBUG] clck_gen.py:102 IND CLOCK 20094
2025-04-27 05:36:38 [DEBUG] clck_gen.py:102 IND CLOCK 20196
2025-04-27 05:36:38 [DEBUG] clck_gen.py:102 IND CLOCK 20298
2025-04-27 05:36:39 [DEBUG] clck_gen.py:102 IND CLOCK 20400
2025-04-27 05:36:39 [DEBUG] clck_gen.py:102 IND CLOCK 20502
2025-04-27 05:36:39 [DEBUG] clck_gen.py:102 IND CLOCK 20604
2025-04-27 05:36:40 [DEBUG] clck_gen.py:102 IND CLOCK 20706
2025-04-27 05:36:40 [DEBUG] clck_gen.py:102 IND CLOCK 20808
2025-04-27 05:36:41 [DEBUG] clck_gen.py:102 IND CLOCK 20910
2025-04-27 05:36:41 [DEBUG] clck_gen.py:102 IND CLOCK 21012
2025-04-27 05:36:42 [DEBUG] clck_gen.py:102 IND CLOCK 21114
2025-04-27 05:36:42 [DEBUG] clck_gen.py:102 IND CLOCK 21216
2025-04-27 05:36:43 [DEBUG] clck_gen.py:102 IND CLOCK 21318
2025-04-27 05:36:43 [DEBUG] clck_gen.py:102 IND CLOCK 21420
2025-04-27 05:36:44 [DEBUG] clck_gen.py:102 IND CLOCK 21522
2025-04-27 05:36:44 [DEBUG] clck_gen.py:102 IND CLOCK 21624
2025-04-27 05:36:45 [DEBUG] clck_gen.py:102 IND CLOCK 21726
2025-04-27 05:36:45 [DEBUG] clck_gen.py:102 IND CLOCK 21828
2025-04-27 05:36:46 [DEBUG] clck_gen.py:102 IND CLOCK 21930
2025-04-27 05:36:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:36:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:36:46 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:36:46 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:36:46 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:36:46 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:36:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:36:46 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:36:46 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:36:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:36:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:36:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:36:46 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:36:46 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:36:46 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:36:46 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:36:46 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:36:46 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-27 05:36:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:36:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:36:46 [DEBUG] clck_gen.py:102 IND CLOCK 22032
2025-04-27 05:36:47 [DEBUG] clck_gen.py:102 IND CLOCK 22134
2025-04-27 05:36:47 [DEBUG] clck_gen.py:102 IND CLOCK 22236
2025-04-27 05:36:48 [DEBUG] clck_gen.py:102 IND CLOCK 22338
2025-04-27 05:36:48 [DEBUG] clck_gen.py:102 IND CLOCK 22440
2025-04-27 05:36:49 [DEBUG] clck_gen.py:102 IND CLOCK 22542
2025-04-27 05:36:49 [DEBUG] clck_gen.py:102 IND CLOCK 22644
2025-04-27 05:36:49 [DEBUG] clck_gen.py:102 IND CLOCK 22746
2025-04-27 05:36:50 [DEBUG] clck_gen.py:102 IND CLOCK 22848
2025-04-27 05:36:50 [DEBUG] clck_gen.py:102 IND CLOCK 22950
2025-04-27 05:36:51 [DEBUG] clck_gen.py:102 IND CLOCK 23052
2025-04-27 05:36:51 [DEBUG] clck_gen.py:102 IND CLOCK 23154
2025-04-27 05:36:52 [DEBUG] clck_gen.py:102 IND CLOCK 23256
2025-04-27 05:36:52 [DEBUG] clck_gen.py:102 IND CLOCK 23358
2025-04-27 05:36:53 [DEBUG] clck_gen.py:102 IND CLOCK 23460
2025-04-27 05:36:53 [DEBUG] clck_gen.py:102 IND CLOCK 23562
2025-04-27 05:36:54 [DEBUG] clck_gen.py:102 IND CLOCK 23664
2025-04-27 05:36:54 [DEBUG] clck_gen.py:102 IND CLOCK 23766
2025-04-27 05:36:55 [DEBUG] clck_gen.py:102 IND CLOCK 23868
2025-04-27 05:36:55 [DEBUG] clck_gen.py:102 IND CLOCK 23970
2025-04-27 05:36:56 [DEBUG] clck_gen.py:102 IND CLOCK 24072
2025-04-27 05:36:56 [DEBUG] clck_gen.py:102 IND CLOCK 24174
2025-04-27 05:36:57 [DEBUG] clck_gen.py:102 IND CLOCK 24276
2025-04-27 05:36:57 [DEBUG] clck_gen.py:102 IND CLOCK 24378
2025-04-27 05:36:58 [DEBUG] clck_gen.py:102 IND CLOCK 24480
2025-04-27 05:36:58 [DEBUG] clck_gen.py:102 IND CLOCK 24582
2025-04-27 05:36:59 [DEBUG] clck_gen.py:102 IND CLOCK 24684
2025-04-27 05:36:59 [DEBUG] clck_gen.py:102 IND CLOCK 24786
2025-04-27 05:36:59 [DEBUG] clck_gen.py:102 IND CLOCK 24888
2025-04-27 05:37:00 [DEBUG] clck_gen.py:102 IND CLOCK 24990
2025-04-27 05:37:00 [DEBUG] clck_gen.py:102 IND CLOCK 25092
2025-04-27 05:37:01 [DEBUG] clck_gen.py:102 IND CLOCK 25194
2025-04-27 05:37:01 [DEBUG] clck_gen.py:102 IND CLOCK 25296
2025-04-27 05:37:02 [DEBUG] clck_gen.py:102 IND CLOCK 25398
2025-04-27 05:37:02 [DEBUG] clck_gen.py:102 IND CLOCK 25500
2025-04-27 05:37:03 [DEBUG] clck_gen.py:102 IND CLOCK 25602
2025-04-27 05:37:03 [DEBUG] clck_gen.py:102 IND CLOCK 25704
2025-04-27 05:37:04 [DEBUG] clck_gen.py:102 IND CLOCK 25806
2025-04-27 05:37:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:37:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:37:04 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:37:04 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:37:04 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:37:04 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:37:04 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:37:04 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:37:04 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:37:04 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:37:04 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:37:04 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=25866 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:37:04 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:37:04 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:37:04 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:37:04 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=25866 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:37:04 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=25866 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:37:04 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=25866 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:37:04 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=25866 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:37:04 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=25866 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:37:04 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=25866 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:37:09 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:37:09 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:37:09 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:37:09 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:37:09 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:37:09 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:37:09 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:37:09 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:37:09 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:37:09 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:37:09 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:37:09 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:37:09 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:37:09 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:37:09 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:37:09 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:37:09 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:37:09 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:37:09 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:37:09 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:37:09 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:37:09 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:37:09 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:37:09 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:37:09 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:37:09 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:37:09 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:37:09 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:37:09 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:37:09 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:37:09 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:37:09 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:37:09 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:37:09 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:37:09 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:37:09 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:37:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:37:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:37:09 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:37:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:37:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:37:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:37:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:37:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:37:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:37:09 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:37:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:37:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:37:09 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:37:09 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:37:09 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:37:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:37:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:37:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:37:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:37:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:37:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:37:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:37:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:37:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:37:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:37:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:37:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:37:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:37:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:37:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:37:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:37:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:37:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:37:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:37:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:37:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:37:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:37:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:37:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:37:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:37:09 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:37:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:37:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:37:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:37:09 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:37:09 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:37:09 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:37:09 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:37:09 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:37:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:37:14 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:37:14 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:37:14 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:37:14 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:37:14 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:37:14 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:37:14 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:37:14 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:37:14 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:37:14 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:37:14 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:37:14 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:37:14 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:37:14 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:37:14 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:37:14 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:37:14 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:37:14 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:37:14 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:37:14 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:37:14 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:37:14 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:37:14 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:37:14 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:37:14 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:37:14 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:37:14 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:37:14 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:37:14 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:37:14 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:37:14 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:37:14 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:37:14 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:37:14 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:37:14 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:37:14 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:37:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:37:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:37:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:37:14 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:37:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:37:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:37:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:37:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:37:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:37:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:37:14 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:37:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:37:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:37:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:37:14 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:37:14 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:37:14 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:37:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:37:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:37:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:37:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:37:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:37:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:37:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:37:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:37:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:37:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:37:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:37:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:37:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:37:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:37:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:37:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:37:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:37:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:37:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:37:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:37:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:37:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:37:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:37:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:37:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:37:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:37:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:37:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:37:14 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:37:15 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:37:15 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:37:15 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:37:15 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:37:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:37:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:37:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:37:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:37:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:37:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:37:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:37:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:37:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:37:15 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:37:15 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:37:15 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:37:15 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:37:15 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:37:15 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:37:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:37:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:37:15 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:37:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:37:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:37:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:37:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:37:16 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 05:37:16 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 05:37:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:37:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:37:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:37:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:37:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:37:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:37:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:37:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:37:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:37:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:37:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:37:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:37:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:37:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:37:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:37:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:37:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:37:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:37:16 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:37:16 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:37:16 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:37:16 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-27 05:37:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:37:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:37:17 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 05:37:17 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 05:37:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:37:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:37:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:37:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:37:18 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 05:37:18 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 05:37:18 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:37:18 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:37:18 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:37:18 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:37:18 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 05:37:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:37:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:37:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:37:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:37:19 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:37:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:37:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:37:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:37:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:37:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:37:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:37:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:37:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:37:19 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:37:19 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:37:19 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:37:19 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:37:19 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:37:19 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:37:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:37:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:37:19 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 05:37:19 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:37:19 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:37:19 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:37:19 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:37:19 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 05:37:20 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 05:37:20 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 05:37:21 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 05:37:21 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 05:37:22 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 05:37:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:37:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:37:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:37:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:37:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:37:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:37:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:37:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:37:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:37:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:37:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:37:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:37:22 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:37:22 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:37:22 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:37:22 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:37:22 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:37:22 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-27 05:37:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:37:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:37:22 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 05:37:23 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 05:37:23 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 05:37:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:37:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:37:23 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:37:23 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:37:23 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:37:23 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:37:23 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:37:23 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:37:23 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:37:23 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:37:23 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:37:23 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:37:23 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:37:23 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:37:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1959 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:37:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1959 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:37:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1959 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:37:28 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:37:28 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:37:28 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:37:28 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:37:28 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:37:28 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:37:28 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:37:28 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:37:28 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:37:28 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:37:28 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:37:28 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:37:28 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:37:28 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:37:28 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:37:28 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:37:28 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:37:28 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:37:28 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:37:28 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:37:28 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:37:28 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:37:28 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:37:28 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:37:28 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:37:28 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:37:28 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:37:28 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:37:28 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:37:28 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:37:28 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:37:28 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:37:28 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:37:28 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:37:28 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:37:28 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:37:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:37:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:37:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:37:28 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:37:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:37:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:37:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:37:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:37:28 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:37:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:37:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:37:28 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:37:28 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:37:28 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:37:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:37:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:37:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:37:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:37:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:37:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:37:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:37:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:37:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:37:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:37:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:37:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:37:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:37:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:37:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:37:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:37:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:37:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:37:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:37:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:37:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:37:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:37:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:37:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:37:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:37:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:37:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:37:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:37:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:37:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:37:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:37:28 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:37:29 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:37:29 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:37:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:37:29 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:37:29 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:37:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:37:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:37:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:37:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:37:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:37:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:37:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:37:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:37:29 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:37:29 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:37:29 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:37:29 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:37:29 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:37:29 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:37:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:37:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:37:29 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:37:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:37:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:37:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:37:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:37:30 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 05:37:30 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 05:37:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:37:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:37:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:37:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:37:31 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 05:37:31 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 05:37:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:37:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:37:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:37:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:37:32 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 05:37:32 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 05:37:32 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:37:32 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:37:32 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:37:32 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:37:33 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 05:37:33 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 05:37:33 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:37:33 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:37:33 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:37:33 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:37:34 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 05:37:34 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 05:37:35 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 05:37:35 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 05:37:36 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 05:37:36 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 05:37:36 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 05:37:37 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 05:37:37 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 05:37:38 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 05:37:38 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 05:37:39 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 05:37:39 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-27 05:37:40 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-27 05:37:40 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-27 05:37:41 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-27 05:37:41 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-27 05:37:42 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-27 05:37:42 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-27 05:37:43 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-27 05:37:43 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-27 05:37:44 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-27 05:37:44 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-27 05:37:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:37:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:37:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:37:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:37:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:37:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:37:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:37:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:37:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:37:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:37:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:37:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:37:44 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:37:44 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:37:44 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:37:44 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:37:44 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:37:44 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-27 05:37:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:37:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:37:45 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-27 05:37:45 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-27 05:37:45 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-27 05:37:46 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-27 05:37:46 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-27 05:37:47 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2025-04-27 05:37:47 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2025-04-27 05:37:48 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2025-04-27 05:37:48 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2025-04-27 05:37:49 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2025-04-27 05:37:49 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2025-04-27 05:37:50 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2025-04-27 05:37:50 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2025-04-27 05:37:51 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2025-04-27 05:37:51 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2025-04-27 05:37:52 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2025-04-27 05:37:52 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2025-04-27 05:37:53 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2025-04-27 05:37:53 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2025-04-27 05:37:54 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2025-04-27 05:37:54 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2025-04-27 05:37:55 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2025-04-27 05:37:55 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2025-04-27 05:37:56 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2025-04-27 05:37:56 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2025-04-27 05:37:56 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2025-04-27 05:37:57 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2025-04-27 05:37:57 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2025-04-27 05:37:58 [DEBUG] clck_gen.py:102 IND CLOCK 6324
2025-04-27 05:37:58 [DEBUG] clck_gen.py:102 IND CLOCK 6426
2025-04-27 05:37:59 [DEBUG] clck_gen.py:102 IND CLOCK 6528
2025-04-27 05:37:59 [DEBUG] clck_gen.py:102 IND CLOCK 6630
2025-04-27 05:38:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:38:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:38:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:38:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:38:00 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:38:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:38:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:38:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:38:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:38:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:38:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:38:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:38:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:38:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:38:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:38:00 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:38:00 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:38:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:38:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:38:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:38:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:38:00 [DEBUG] clck_gen.py:102 IND CLOCK 6732
2025-04-27 05:38:00 [DEBUG] clck_gen.py:102 IND CLOCK 6834
2025-04-27 05:38:01 [DEBUG] clck_gen.py:102 IND CLOCK 6936
2025-04-27 05:38:01 [DEBUG] clck_gen.py:102 IND CLOCK 7038
2025-04-27 05:38:02 [DEBUG] clck_gen.py:102 IND CLOCK 7140
2025-04-27 05:38:02 [DEBUG] clck_gen.py:102 IND CLOCK 7242
2025-04-27 05:38:03 [DEBUG] clck_gen.py:102 IND CLOCK 7344
2025-04-27 05:38:03 [DEBUG] clck_gen.py:102 IND CLOCK 7446
2025-04-27 05:38:04 [DEBUG] clck_gen.py:102 IND CLOCK 7548
2025-04-27 05:38:04 [DEBUG] clck_gen.py:102 IND CLOCK 7650
2025-04-27 05:38:05 [DEBUG] clck_gen.py:102 IND CLOCK 7752
2025-04-27 05:38:05 [DEBUG] clck_gen.py:102 IND CLOCK 7854
2025-04-27 05:38:06 [DEBUG] clck_gen.py:102 IND CLOCK 7956
2025-04-27 05:38:06 [DEBUG] clck_gen.py:102 IND CLOCK 8058
2025-04-27 05:38:06 [DEBUG] clck_gen.py:102 IND CLOCK 8160
2025-04-27 05:38:07 [DEBUG] clck_gen.py:102 IND CLOCK 8262
2025-04-27 05:38:07 [DEBUG] clck_gen.py:102 IND CLOCK 8364
2025-04-27 05:38:08 [DEBUG] clck_gen.py:102 IND CLOCK 8466
2025-04-27 05:38:08 [DEBUG] clck_gen.py:102 IND CLOCK 8568
2025-04-27 05:38:09 [DEBUG] clck_gen.py:102 IND CLOCK 8670
2025-04-27 05:38:09 [DEBUG] clck_gen.py:102 IND CLOCK 8772
2025-04-27 05:38:10 [DEBUG] clck_gen.py:102 IND CLOCK 8874
2025-04-27 05:38:10 [DEBUG] clck_gen.py:102 IND CLOCK 8976
2025-04-27 05:38:11 [DEBUG] clck_gen.py:102 IND CLOCK 9078
2025-04-27 05:38:11 [DEBUG] clck_gen.py:102 IND CLOCK 9180
2025-04-27 05:38:12 [DEBUG] clck_gen.py:102 IND CLOCK 9282
2025-04-27 05:38:12 [DEBUG] clck_gen.py:102 IND CLOCK 9384
2025-04-27 05:38:13 [DEBUG] clck_gen.py:102 IND CLOCK 9486
2025-04-27 05:38:13 [DEBUG] clck_gen.py:102 IND CLOCK 9588
2025-04-27 05:38:14 [DEBUG] clck_gen.py:102 IND CLOCK 9690
2025-04-27 05:38:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:38:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:38:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:38:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:38:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:38:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:38:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:38:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:38:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:38:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:38:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:38:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:38:14 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:38:14 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:38:14 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:38:14 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:38:14 [DEBUG] clck_gen.py:102 IND CLOCK 9792
2025-04-27 05:38:14 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:38:14 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-27 05:38:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:38:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:38:15 [DEBUG] clck_gen.py:102 IND CLOCK 9894
2025-04-27 05:38:15 [DEBUG] clck_gen.py:102 IND CLOCK 9996
2025-04-27 05:38:16 [DEBUG] clck_gen.py:102 IND CLOCK 10098
2025-04-27 05:38:16 [DEBUG] clck_gen.py:102 IND CLOCK 10200
2025-04-27 05:38:16 [DEBUG] clck_gen.py:102 IND CLOCK 10302
2025-04-27 05:38:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:38:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:38:17 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:38:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:38:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:38:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:38:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:38:17 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:38:17 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:38:17 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:38:17 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:38:17 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:38:17 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:38:17 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:38:17 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=10390 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:38:17 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=10390 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:38:17 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=10390 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:38:17 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=10390 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:38:17 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=10390 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:38:17 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=10391 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:38:17 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=10391 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:38:17 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=10391 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:38:17 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=10391 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:38:17 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=10391 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:38:17 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=10391 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:38:17 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=10391 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:38:17 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=10391 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:38:22 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:38:22 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:38:22 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:38:22 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:38:22 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:38:22 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:38:22 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:38:22 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:38:22 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:38:22 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:38:22 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:38:22 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:38:22 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:38:22 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:38:22 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:38:22 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:38:22 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:38:22 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:38:22 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:38:22 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:38:22 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:38:22 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:38:22 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:38:22 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:38:22 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:38:22 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:38:22 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:38:22 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:38:22 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:38:22 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:38:22 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:38:22 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:38:22 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:38:22 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:38:22 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:38:22 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:38:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:38:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:38:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:38:22 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:38:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:38:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:38:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:38:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:38:22 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:38:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:38:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:38:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:38:22 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:38:22 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:38:22 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:38:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:38:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:38:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:38:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:38:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:38:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:38:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:38:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:38:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:38:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:38:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:38:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:38:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:38:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:38:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:38:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:38:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:38:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:38:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:38:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:38:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:38:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:38:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:38:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:38:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:38:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:38:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:38:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:38:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:38:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:38:22 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:38:22 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:38:22 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:38:22 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:38:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:38:22 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:38:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:38:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:38:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:38:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:38:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:38:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:38:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:38:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:38:22 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:38:22 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:38:22 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:38:22 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:38:23 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:38:23 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:38:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:38:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:38:23 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:38:23 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:38:23 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:38:23 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:38:23 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:38:23 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 05:38:24 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 05:38:24 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:38:24 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:38:24 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:38:24 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:38:24 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 05:38:25 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 05:38:25 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:38:25 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:38:25 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:38:25 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:38:25 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 05:38:26 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 05:38:26 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:38:26 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:38:26 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:38:26 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:38:26 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 05:38:27 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 05:38:27 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:38:27 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:38:27 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:38:27 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:38:27 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 05:38:28 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 05:38:28 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 05:38:29 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 05:38:29 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 05:38:30 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 05:38:30 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 05:38:31 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 05:38:31 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 05:38:31 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 05:38:32 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 05:38:32 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 05:38:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:38:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:38:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:38:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:38:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:38:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:38:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:38:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:38:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:38:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:38:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:38:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:38:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:38:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:38:33 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:38:33 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:38:33 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:38:33 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-27 05:38:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:38:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:38:33 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-27 05:38:33 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-27 05:38:34 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-27 05:38:34 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-27 05:38:35 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-27 05:38:35 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-27 05:38:36 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-27 05:38:36 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-27 05:38:37 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-27 05:38:37 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-27 05:38:38 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-27 05:38:38 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-27 05:38:39 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-27 05:38:39 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-27 05:38:40 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-27 05:38:40 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-27 05:38:41 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2025-04-27 05:38:41 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2025-04-27 05:38:42 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2025-04-27 05:38:42 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2025-04-27 05:38:42 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2025-04-27 05:38:43 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2025-04-27 05:38:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:38:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:38:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:38:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:38:43 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:38:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:38:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:38:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:38:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:38:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:38:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:38:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:38:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:38:43 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:38:43 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:38:43 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:38:43 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:38:43 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:38:43 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:38:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:38:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:38:43 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2025-04-27 05:38:44 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2025-04-27 05:38:44 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2025-04-27 05:38:45 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2025-04-27 05:38:45 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2025-04-27 05:38:46 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2025-04-27 05:38:46 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2025-04-27 05:38:47 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2025-04-27 05:38:47 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2025-04-27 05:38:48 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2025-04-27 05:38:48 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2025-04-27 05:38:49 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2025-04-27 05:38:49 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2025-04-27 05:38:50 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2025-04-27 05:38:50 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2025-04-27 05:38:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:38:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:38:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:38:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:38:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:38:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:38:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:38:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:38:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:38:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:38:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:38:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:38:50 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:38:50 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:38:50 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:38:50 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:38:50 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:38:50 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-27 05:38:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:38:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:38:51 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2025-04-27 05:38:51 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2025-04-27 05:38:52 [DEBUG] clck_gen.py:102 IND CLOCK 6324
2025-04-27 05:38:52 [DEBUG] clck_gen.py:102 IND CLOCK 6426
2025-04-27 05:38:52 [DEBUG] clck_gen.py:102 IND CLOCK 6528
2025-04-27 05:38:53 [DEBUG] clck_gen.py:102 IND CLOCK 6630
2025-04-27 05:38:53 [DEBUG] clck_gen.py:102 IND CLOCK 6732
2025-04-27 05:38:54 [DEBUG] clck_gen.py:102 IND CLOCK 6834
2025-04-27 05:38:54 [DEBUG] clck_gen.py:102 IND CLOCK 6936
2025-04-27 05:38:55 [DEBUG] clck_gen.py:102 IND CLOCK 7038
2025-04-27 05:38:55 [DEBUG] clck_gen.py:102 IND CLOCK 7140
2025-04-27 05:38:56 [DEBUG] clck_gen.py:102 IND CLOCK 7242
2025-04-27 05:38:56 [DEBUG] clck_gen.py:102 IND CLOCK 7344
2025-04-27 05:38:57 [DEBUG] clck_gen.py:102 IND CLOCK 7446
2025-04-27 05:38:57 [DEBUG] clck_gen.py:102 IND CLOCK 7548
2025-04-27 05:38:58 [DEBUG] clck_gen.py:102 IND CLOCK 7650
2025-04-27 05:38:58 [DEBUG] clck_gen.py:102 IND CLOCK 7752
2025-04-27 05:38:59 [DEBUG] clck_gen.py:102 IND CLOCK 7854
2025-04-27 05:38:59 [DEBUG] clck_gen.py:102 IND CLOCK 7956
2025-04-27 05:39:00 [DEBUG] clck_gen.py:102 IND CLOCK 8058
2025-04-27 05:39:00 [DEBUG] clck_gen.py:102 IND CLOCK 8160
2025-04-27 05:39:01 [DEBUG] clck_gen.py:102 IND CLOCK 8262
2025-04-27 05:39:01 [DEBUG] clck_gen.py:102 IND CLOCK 8364
2025-04-27 05:39:02 [DEBUG] clck_gen.py:102 IND CLOCK 8466
2025-04-27 05:39:02 [DEBUG] clck_gen.py:102 IND CLOCK 8568
2025-04-27 05:39:03 [DEBUG] clck_gen.py:102 IND CLOCK 8670
2025-04-27 05:39:03 [DEBUG] clck_gen.py:102 IND CLOCK 8772
2025-04-27 05:39:03 [DEBUG] clck_gen.py:102 IND CLOCK 8874
2025-04-27 05:39:04 [DEBUG] clck_gen.py:102 IND CLOCK 8976
2025-04-27 05:39:04 [DEBUG] clck_gen.py:102 IND CLOCK 9078
2025-04-27 05:39:05 [DEBUG] clck_gen.py:102 IND CLOCK 9180
2025-04-27 05:39:05 [DEBUG] clck_gen.py:102 IND CLOCK 9282
2025-04-27 05:39:06 [DEBUG] clck_gen.py:102 IND CLOCK 9384
2025-04-27 05:39:06 [DEBUG] clck_gen.py:102 IND CLOCK 9486
2025-04-27 05:39:07 [DEBUG] clck_gen.py:102 IND CLOCK 9588
2025-04-27 05:39:07 [DEBUG] clck_gen.py:102 IND CLOCK 9690
2025-04-27 05:39:08 [DEBUG] clck_gen.py:102 IND CLOCK 9792
2025-04-27 05:39:08 [DEBUG] clck_gen.py:102 IND CLOCK 9894
2025-04-27 05:39:09 [DEBUG] clck_gen.py:102 IND CLOCK 9996
2025-04-27 05:39:09 [DEBUG] clck_gen.py:102 IND CLOCK 10098
2025-04-27 05:39:10 [DEBUG] clck_gen.py:102 IND CLOCK 10200
2025-04-27 05:39:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:39:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:39:10 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:39:10 [DEBUG] clck_gen.py:102 IND CLOCK 10302
2025-04-27 05:39:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:39:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:39:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:39:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:39:10 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:39:10 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:39:10 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:39:10 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:39:10 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:39:10 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:39:10 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:39:15 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:39:15 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:39:15 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:39:15 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:39:15 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:39:15 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:39:15 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:39:15 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:39:15 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:39:15 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:39:15 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:39:15 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:39:15 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:39:15 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:39:15 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:39:15 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:39:15 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:39:15 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:39:15 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:39:15 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:39:15 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:39:15 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:39:15 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:39:15 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:39:15 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:39:15 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:39:15 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:39:15 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:39:15 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:39:15 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:39:15 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:39:15 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:39:15 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:39:15 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:39:15 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:39:15 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:39:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:39:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:39:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:39:15 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:39:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:39:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:39:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:39:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:39:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:39:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:39:15 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:39:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:39:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:39:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:39:15 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:39:15 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:39:15 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:39:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:39:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:39:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:39:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:39:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:39:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:39:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:39:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:39:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:39:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:39:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:39:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:39:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:39:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:39:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:39:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:39:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:39:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:39:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:39:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:39:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:39:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:39:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:39:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:39:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:39:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:39:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:39:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:39:15 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:39:16 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:39:16 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:39:16 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:39:16 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:39:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:39:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:39:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:39:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:39:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:39:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:39:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:39:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:39:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:39:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:39:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:39:16 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:39:16 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:39:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:39:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:39:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:39:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:39:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:39:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:39:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:39:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:39:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:39:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:39:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:39:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:39:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:39:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:39:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:39:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:39:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:39:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:39:16 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:39:16 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:39:16 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:39:16 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:39:16 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-27 05:39:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:39:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:39:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:39:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:39:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:39:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:39:17 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 05:39:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:39:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:39:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:39:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:39:17 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:39:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:39:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:39:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:39:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:39:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:39:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:39:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:39:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:39:17 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:39:17 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:39:17 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:39:17 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:39:17 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:39:17 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:39:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:39:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:39:17 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 05:39:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:39:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:39:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:39:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:39:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:39:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:39:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:39:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:39:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:39:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:39:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:39:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:39:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:39:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:39:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:39:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:39:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:39:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:39:18 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:39:18 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:39:18 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:39:18 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-27 05:39:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:39:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:39:18 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 05:39:18 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 05:39:18 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:39:18 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:39:18 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:39:18 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:39:19 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 05:39:19 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 05:39:19 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:39:19 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:39:19 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:39:19 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:39:20 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 05:39:20 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 05:39:20 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:39:20 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:39:20 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:39:20 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:39:20 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 05:39:21 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 05:39:21 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 05:39:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:39:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:39:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:39:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:39:22 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:39:22 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:39:22 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:39:22 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:39:22 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:39:22 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:39:22 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:39:22 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:39:22 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:39:22 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1379 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:39:22 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:39:22 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:39:22 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:39:22 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1379 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:39:22 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1379 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:39:22 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1379 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:39:22 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1379 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:39:22 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=1379 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:39:27 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:39:27 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:39:27 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:39:27 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:39:27 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:39:27 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:39:27 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:39:27 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:39:27 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:39:27 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:39:27 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:39:27 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:39:27 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:39:27 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:39:27 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:39:27 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:39:27 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:39:27 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:39:27 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:39:27 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:39:27 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:39:27 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:39:27 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:39:27 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:39:27 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:39:27 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:39:27 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:39:27 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:39:27 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:39:27 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:39:27 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:39:27 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:39:27 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:39:27 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:39:27 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:39:27 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:39:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:39:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:39:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:39:27 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:39:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:39:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:39:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:39:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:39:27 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:39:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:39:27 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:39:27 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:39:27 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:39:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:39:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:39:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:39:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:39:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:39:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:39:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:39:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:39:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:39:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:39:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:39:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:39:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:39:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:39:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:39:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:39:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:39:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:39:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:39:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:39:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:39:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:39:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:39:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:39:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:39:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:39:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:39:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:39:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:39:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:39:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:39:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:39:27 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:39:27 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:39:27 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:39:27 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:39:27 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:39:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:39:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:39:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:39:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:39:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:39:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:39:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:39:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:39:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:39:27 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:39:27 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:39:27 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:39:27 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:39:27 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:39:27 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:39:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:39:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:39:28 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:39:28 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:39:28 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:39:28 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:39:28 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:39:28 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 05:39:29 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 05:39:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:39:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:39:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:39:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:39:29 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 05:39:30 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 05:39:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:39:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:39:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:39:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:39:30 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 05:39:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:39:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:39:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:39:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:39:30 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 05:39:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:39:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:39:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:39:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:39:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:39:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:39:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:39:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:39:31 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:39:31 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:39:31 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:39:31 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:39:31 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:39:31 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-27 05:39:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:39:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:39:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:39:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:39:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:39:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:39:31 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 05:39:31 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 05:39:32 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:39:32 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:39:32 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:39:32 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:39:32 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 05:39:32 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 05:39:33 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 05:39:33 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 05:39:34 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 05:39:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:39:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:39:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:39:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:39:34 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:39:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:39:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:39:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:39:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:39:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:39:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:39:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:39:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:39:34 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:39:34 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:39:34 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:39:34 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:39:34 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:39:34 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:39:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:39:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:39:34 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 05:39:35 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 05:39:35 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 05:39:36 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 05:39:36 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 05:39:37 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 05:39:37 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 05:39:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:39:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:39:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:39:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:39:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:39:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:39:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:39:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:39:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:39:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:39:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:39:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:39:38 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:39:38 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:39:38 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:39:38 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:39:38 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:39:38 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-27 05:39:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:39:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:39:38 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-27 05:39:38 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-27 05:39:39 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-27 05:39:39 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-27 05:39:40 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-27 05:39:40 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-27 05:39:40 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-27 05:39:41 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-27 05:39:41 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-27 05:39:42 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-27 05:39:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:39:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:39:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:39:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:39:42 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:39:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:39:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:39:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:39:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:39:42 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:39:42 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:39:42 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:39:42 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:39:42 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3286 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:39:42 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:39:42 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:39:42 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:39:42 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3286 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:39:42 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3286 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:39:42 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3286 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:39:42 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3287 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:39:42 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3287 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:39:42 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3287 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:39:42 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3287 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:39:42 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3287 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:39:42 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3287 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:39:42 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3287 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:39:42 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3287 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:39:42 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3288 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:39:42 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3288 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:39:42 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3288 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:39:42 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3288 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:39:42 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3288 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:39:42 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3288 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:39:42 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3288 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:39:42 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3288 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:39:47 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:39:47 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:39:47 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:39:47 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:39:47 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:39:47 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:39:47 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:39:47 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:39:47 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:39:47 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:39:47 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:39:47 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:39:47 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:39:47 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:39:47 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:39:47 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:39:47 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:39:47 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:39:47 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:39:47 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:39:47 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:39:47 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:39:47 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:39:47 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:39:47 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:39:47 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:39:47 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:39:47 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:39:47 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:39:47 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:39:47 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:39:47 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:39:47 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:39:47 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:39:47 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:39:47 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:39:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:39:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:39:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:39:47 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:39:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:39:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:39:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:39:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:39:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:39:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:39:47 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:39:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:39:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:39:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:39:47 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:39:47 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:39:47 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:39:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:39:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:39:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:39:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:39:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:39:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:39:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:39:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:39:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:39:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:39:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:39:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:39:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:39:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:39:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:39:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:39:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:39:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:39:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:39:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:39:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:39:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:39:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:39:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:39:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:39:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:39:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:39:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:39:47 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:39:48 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:39:48 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:39:48 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:39:48 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:39:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:39:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:39:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:39:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:39:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:39:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:39:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:39:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:39:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:39:48 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:39:48 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:39:48 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:39:48 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:39:48 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:39:48 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:39:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:39:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:39:48 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:39:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:39:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:39:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:39:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:39:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:39:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:39:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:39:48 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:39:48 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:39:48 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:39:48 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:39:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:39:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:39:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:39:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:39:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:39:48 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:39:48 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:39:48 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:39:48 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:39:48 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:39:48 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-27 05:39:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:39:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:39:48 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 05:39:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:39:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:39:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:39:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:39:49 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:39:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:39:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:39:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:39:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:39:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:39:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:39:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:39:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:39:49 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:39:49 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:39:49 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:39:49 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:39:49 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:39:49 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:39:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:39:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:39:49 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 05:39:49 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:39:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:39:49 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:39:49 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:39:49 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 05:39:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:39:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:39:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:39:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:39:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:39:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:39:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:39:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:39:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:39:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:39:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:39:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:39:50 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:39:50 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:39:50 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:39:50 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:39:50 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:39:50 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-27 05:39:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:39:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:39:50 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 05:39:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:39:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:39:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:39:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:39:50 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 05:39:51 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 05:39:51 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:39:51 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:39:51 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:39:51 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:39:51 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 05:39:52 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 05:39:52 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:39:52 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:39:52 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:39:52 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:39:52 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 05:39:53 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 05:39:53 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 05:39:54 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 05:39:54 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 05:39:55 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 05:39:55 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 05:39:56 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 05:39:56 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 05:39:57 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 05:39:57 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 05:39:58 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 05:39:58 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-27 05:39:58 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-27 05:39:59 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-27 05:39:59 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-27 05:40:00 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-27 05:40:00 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-27 05:40:01 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-27 05:40:01 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-27 05:40:02 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-27 05:40:02 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-27 05:40:03 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-27 05:40:03 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-27 05:40:04 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-27 05:40:04 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-27 05:40:05 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-27 05:40:05 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-27 05:40:06 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2025-04-27 05:40:06 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2025-04-27 05:40:07 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2025-04-27 05:40:07 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2025-04-27 05:40:07 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2025-04-27 05:40:08 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2025-04-27 05:40:08 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2025-04-27 05:40:09 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2025-04-27 05:40:09 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2025-04-27 05:40:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:40:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:40:10 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:40:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:40:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:40:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:40:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:40:10 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:40:10 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:40:10 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:40:10 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:40:10 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:40:10 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:40:10 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:40:10 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4892 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:40:10 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4892 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:40:10 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4892 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:40:10 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4892 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:40:10 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4892 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:40:10 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=4892 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:40:15 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:40:15 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:40:15 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:40:15 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:40:15 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:40:15 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:40:15 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:40:15 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:40:15 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:40:15 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:40:15 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:40:15 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:40:15 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:40:15 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:40:15 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:40:15 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:40:15 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:40:15 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:40:15 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:40:15 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:40:15 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:40:15 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:40:15 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:40:15 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:40:15 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:40:15 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:40:15 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:40:15 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:40:15 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:40:15 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:40:15 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:40:15 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:40:15 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:40:15 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:40:15 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:40:15 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:40:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:40:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:40:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:40:15 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:40:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:40:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:40:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:40:15 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:40:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:40:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:40:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:40:15 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:40:15 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:40:15 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:40:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:40:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:40:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:40:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:40:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:40:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:40:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:40:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:40:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:40:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:40:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:40:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:40:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:40:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:40:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:40:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:40:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:40:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:40:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:40:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:40:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:40:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:40:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:40:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:40:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:40:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:40:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:40:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:40:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:40:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:40:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:40:15 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:40:15 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:40:15 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:40:15 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:40:15 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:40:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:40:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:40:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:40:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:40:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:40:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:40:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:40:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:40:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:40:15 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:40:15 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:40:15 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:40:15 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:40:15 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:40:15 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:40:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:40:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:40:16 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:40:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:40:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:40:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:40:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:40:16 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 05:40:17 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 05:40:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:40:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:40:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:40:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:40:17 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 05:40:18 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 05:40:18 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:40:18 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:40:18 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:40:18 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:40:18 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 05:40:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:40:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:40:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:40:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:40:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:40:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:40:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:40:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:40:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:40:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:40:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:40:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:40:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:40:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:40:18 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:40:18 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:40:18 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:40:18 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-27 05:40:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:40:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:40:19 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 05:40:19 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:40:19 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:40:19 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:40:19 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:40:19 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 05:40:20 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 05:40:20 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:40:20 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:40:20 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:40:20 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:40:20 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 05:40:21 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 05:40:21 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 05:40:22 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 05:40:22 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 05:40:23 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 05:40:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:40:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:40:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:40:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:40:23 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:40:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:40:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:40:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:40:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:40:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:40:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:40:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:40:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:40:23 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:40:23 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:40:23 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:40:23 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:40:23 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:40:23 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:40:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:40:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:40:23 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 05:40:23 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 05:40:24 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 05:40:24 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 05:40:25 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 05:40:25 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 05:40:26 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-27 05:40:26 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-27 05:40:27 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-27 05:40:27 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-27 05:40:28 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-27 05:40:28 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-27 05:40:29 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-27 05:40:29 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-27 05:40:30 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-27 05:40:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:40:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:40:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:40:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:40:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:40:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:40:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:40:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:40:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:40:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:40:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:40:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:40:30 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:40:30 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:40:30 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:40:30 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:40:30 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:40:30 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-27 05:40:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:40:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:40:30 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-27 05:40:31 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-27 05:40:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:40:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:40:31 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:40:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:40:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:40:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:40:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:40:31 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:40:31 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:40:31 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:40:31 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:40:31 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:40:31 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:40:31 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:40:31 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3387 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:40:31 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3387 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:40:31 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3387 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:40:31 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3387 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:40:31 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3387 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:40:36 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:40:36 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:40:36 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:40:36 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:40:36 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:40:36 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:40:36 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:40:36 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:40:36 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:40:36 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:40:36 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:40:36 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:40:36 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:40:36 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:40:36 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:40:36 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:40:36 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:40:36 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:40:36 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:40:36 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:40:36 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:40:36 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:40:36 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:40:36 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:40:36 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:40:36 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:40:36 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:40:36 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:40:36 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:40:36 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:40:36 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:40:36 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:40:36 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:40:36 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:40:36 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:40:36 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:40:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:40:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:40:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:40:36 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:40:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:40:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:40:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:40:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:40:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:40:36 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:40:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:40:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:40:36 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:40:36 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:40:36 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:40:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:40:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:40:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:40:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:40:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:40:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:40:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:40:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:40:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:40:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:40:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:40:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:40:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:40:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:40:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:40:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:40:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:40:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:40:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:40:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:40:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:40:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:40:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:40:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:40:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:40:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:40:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:40:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:40:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:40:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:40:36 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:40:36 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:40:36 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:40:36 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:40:36 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:40:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:40:36 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:40:36 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:40:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:40:36 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:40:36 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:40:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:40:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:40:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:40:36 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:40:36 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:40:36 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:40:36 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:40:36 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:40:36 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:40:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:40:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:40:37 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:40:37 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:40:37 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:40:37 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:40:37 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:40:37 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 05:40:38 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 05:40:38 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:40:38 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:40:38 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:40:38 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:40:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:40:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:40:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:40:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:40:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:40:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:40:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:40:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:40:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:40:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:40:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:40:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:40:38 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:40:38 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:40:38 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:40:38 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:40:38 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:40:38 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-27 05:40:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:40:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:40:38 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 05:40:39 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 05:40:39 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:40:39 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:40:39 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:40:39 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:40:39 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 05:40:40 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 05:40:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:40:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:40:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:40:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:40:40 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 05:40:41 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 05:40:41 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:40:41 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:40:41 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:40:41 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:40:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:40:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:40:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:40:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:40:41 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:40:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:40:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:40:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:40:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:40:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:40:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:40:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:40:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:40:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:40:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:40:41 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:40:41 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:40:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:40:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:40:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:40:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:40:41 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 05:40:41 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 05:40:42 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 05:40:42 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 05:40:43 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 05:40:43 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 05:40:44 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 05:40:44 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 05:40:45 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 05:40:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:40:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:40:45 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:40:45 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:40:45 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:40:45 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:40:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:40:45 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:40:45 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:40:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:40:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:40:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:40:45 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:40:45 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:40:45 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:40:45 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:40:45 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.127.22:6700) Recv SETFH cmd
2025-04-27 05:40:45 [INFO] transceiver.py:201 (MS@172.18.127.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-27 05:40:45 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 05:40:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:40:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:40:46 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 05:40:46 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 05:40:47 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-27 05:40:47 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-27 05:40:48 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-27 05:40:48 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-27 05:40:49 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-27 05:40:49 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-27 05:40:50 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-27 05:40:50 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-27 05:40:51 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-27 05:40:51 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-27 05:40:51 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-27 05:40:52 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-27 05:40:52 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-27 05:40:53 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-27 05:40:53 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-27 05:40:54 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-27 05:40:54 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2025-04-27 05:40:55 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2025-04-27 05:40:55 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2025-04-27 05:40:56 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2025-04-27 05:40:56 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2025-04-27 05:40:57 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2025-04-27 05:40:57 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2025-04-27 05:40:58 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2025-04-27 05:40:58 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2025-04-27 05:40:59 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2025-04-27 05:40:59 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2025-04-27 05:41:00 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2025-04-27 05:41:00 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2025-04-27 05:41:00 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2025-04-27 05:41:01 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2025-04-27 05:41:01 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2025-04-27 05:41:02 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2025-04-27 05:41:02 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2025-04-27 05:41:03 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2025-04-27 05:41:03 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2025-04-27 05:41:04 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2025-04-27 05:41:04 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2025-04-27 05:41:05 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2025-04-27 05:41:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:41:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:41:05 [INFO] transceiver.py:205 (MS@172.18.127.22:6700) Frequency hopping disabled
2025-04-27 05:41:05 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:41:05 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:41:05 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:41:05 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:41:05 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:41:05 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:41:05 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:41:05 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:41:05 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:41:05 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:41:05 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:41:10 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:41:10 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:41:10 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:41:10 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:41:10 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:41:10 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:41:10 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:41:10 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:41:10 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:41:10 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:41:10 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:41:10 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:41:10 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:41:10 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:41:10 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:41:10 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:41:10 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:41:10 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:41:10 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:41:10 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:41:10 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:41:10 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:41:10 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:41:10 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:41:10 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:41:10 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:41:10 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:41:10 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:41:10 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:41:10 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:41:10 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:41:10 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:41:10 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:41:10 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:41:10 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:41:10 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:41:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:41:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:41:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:41:10 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:41:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:41:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:41:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:41:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:41:10 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:41:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:41:10 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:41:10 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:41:10 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:41:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:41:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:41:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:41:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:41:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:41:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:41:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:41:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:41:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:41:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:41:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:41:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:41:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:41:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:41:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:41:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:41:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:41:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:41:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:41:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:41:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:41:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:41:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:41:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:41:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:41:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:41:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:41:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:41:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:41:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:41:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:41:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:41:10 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:41:11 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:41:11 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:41:11 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:41:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:11 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:41:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:11 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:41:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:41:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:41:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:41:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:41:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:12 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 05:41:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:41:12 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:41:12 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:41:12 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:41:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:41:12 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:41:12 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:41:12 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:41:12 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=397 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:41:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:41:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:41:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:41:12 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=397 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:41:12 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=397 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:41:12 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=397 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:41:12 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=397 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:41:17 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:41:17 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:41:17 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:41:17 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:41:17 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:41:17 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:41:17 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:41:17 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:41:17 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:41:17 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:41:17 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:41:17 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:41:17 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:41:17 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:41:17 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:41:17 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:41:17 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:41:17 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:41:17 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:41:17 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:41:17 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:41:17 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:41:17 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:41:17 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:41:17 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:41:17 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:41:17 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:41:17 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:41:17 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:41:17 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:41:17 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:41:17 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:41:17 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:41:17 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:41:17 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:41:17 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:41:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:41:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:41:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:41:17 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:41:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:41:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:41:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:41:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:41:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:41:17 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:41:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:41:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:41:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:41:17 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:41:17 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:41:17 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:41:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:41:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:41:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:41:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:41:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:41:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:41:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:41:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:41:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:41:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:41:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:41:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:41:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:41:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:41:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:41:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:41:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:41:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:41:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:41:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:41:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:41:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:41:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:41:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:41:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:41:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:41:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:41:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:41:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:41:17 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:41:18 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:41:18 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:41:18 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:41:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:18 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:41:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:18 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:41:18 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:41:18 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:41:18 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:41:18 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:41:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:19 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 05:41:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:19 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:41:19 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:41:19 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:41:19 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:41:19 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:41:19 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:41:19 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:41:19 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:41:19 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:41:19 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:41:19 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:41:19 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=403 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:41:19 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=403 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:41:19 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=403 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:41:19 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=403 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:41:19 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=403 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:41:19 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=403 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:41:19 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=403 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:41:24 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:41:24 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:41:24 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:41:24 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:41:24 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:41:24 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:41:24 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:41:24 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:41:24 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:41:24 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:41:24 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:41:24 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:41:24 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:41:24 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:41:24 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:41:24 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:41:24 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:41:24 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:41:24 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:41:24 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:41:24 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:41:24 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:41:24 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:41:24 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:41:24 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:41:24 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:41:24 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:41:24 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:41:24 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:41:24 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:41:24 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:41:24 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:41:24 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:41:24 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:41:24 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:41:24 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:41:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:41:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:41:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:41:24 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:41:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:41:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:41:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:41:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:41:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:41:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:41:24 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:41:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:41:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:41:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:41:24 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:41:24 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:41:24 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:41:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:41:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:41:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:41:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:41:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:41:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:41:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:41:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:41:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:41:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:41:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:41:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:41:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:41:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:41:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:41:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:41:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:41:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:41:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:41:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:41:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:41:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:41:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:41:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:41:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:41:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:41:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:41:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:41:24 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:41:25 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:41:25 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:41:25 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:41:25 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:41:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:25 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:41:25 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:41:25 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:41:25 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:41:25 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:41:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:26 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 05:41:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:26 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:41:26 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:41:26 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:41:26 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:41:26 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:41:26 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:41:26 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:41:26 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:41:26 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:41:26 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:41:26 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:41:26 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=402 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:41:26 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=402 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:41:26 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=402 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:41:26 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=402 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:41:26 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=402 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:41:26 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=402 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:41:26 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=402 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:41:31 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:41:31 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:41:31 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:41:31 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:41:31 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:41:31 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:41:31 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:41:31 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:41:31 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:41:31 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:41:31 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:41:31 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:41:31 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:41:31 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:41:31 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:41:31 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:41:31 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:41:31 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:41:31 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:41:31 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:41:31 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:41:31 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:41:31 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:41:31 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:41:31 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:41:31 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:41:31 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:41:31 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:41:31 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:41:31 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:41:31 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:41:31 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:41:31 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:41:31 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:41:31 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:41:31 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:41:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:41:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:41:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:41:31 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:41:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:41:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:41:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:41:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:41:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:41:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:41:31 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:41:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:41:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:41:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:41:31 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:41:31 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:41:31 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:41:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:41:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:41:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:41:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:41:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:41:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:41:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:41:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:41:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:41:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:41:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:41:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:41:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:41:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:41:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:41:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:41:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:41:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:41:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:41:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:41:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:41:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:41:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:41:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:41:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:41:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:41:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:41:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:41:31 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:41:31 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:41:32 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:41:32 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:41:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:32 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:41:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:32 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:41:32 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:41:32 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:41:32 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:41:32 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:41:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:32 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 05:41:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:33 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:41:33 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:41:33 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:41:33 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:41:33 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:41:33 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:41:33 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:41:33 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:41:33 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:41:33 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:41:33 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:41:33 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=403 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:41:33 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=403 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:41:33 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=403 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:41:33 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=403 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:41:33 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=403 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:41:33 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=403 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:41:33 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=403 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:41:33 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=404 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:41:33 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=404 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:41:33 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=404 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:41:33 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=404 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:41:33 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=404 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:41:33 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=404 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:41:33 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=404 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:41:33 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=404 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:41:38 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:41:38 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:41:38 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:41:38 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:41:38 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:41:38 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:41:38 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:41:38 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:41:38 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:41:38 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:41:38 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:41:38 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:41:38 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:41:38 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:41:38 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:41:38 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:41:38 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:41:38 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:41:38 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:41:38 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:41:38 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:41:38 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:41:38 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:41:38 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:41:38 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:41:38 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:41:38 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:41:38 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:41:38 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:41:38 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:41:38 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:41:38 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:41:38 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:41:38 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:41:38 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:41:38 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:41:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:41:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:41:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:41:38 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:41:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:41:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:41:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:41:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:41:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:41:38 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:41:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:41:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:41:38 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:41:38 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:41:38 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:41:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:41:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:41:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:41:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:41:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:41:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:41:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:41:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:41:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:41:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:41:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:41:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:41:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:41:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:41:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:41:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:41:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:41:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:41:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:41:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:41:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:41:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:41:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:41:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:41:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:41:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:41:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:41:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:41:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:41:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:41:38 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:41:38 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:41:38 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:41:38 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:41:38 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:41:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:41:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:39 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:41:39 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:41:39 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:41:39 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:41:39 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:41:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:39 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 05:41:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:41:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:41:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:41:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:41:40 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:41:40 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:41:40 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:41:40 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:41:40 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=408 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:41:40 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:41:40 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:41:40 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:41:45 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:41:45 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:41:45 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:41:45 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:41:45 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:41:45 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:41:45 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:41:45 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:41:45 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:41:45 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:41:45 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:41:45 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:41:45 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:41:45 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:41:45 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:41:45 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:41:45 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:41:45 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:41:45 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:41:45 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:41:45 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:41:45 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:41:45 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:41:45 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:41:45 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:41:45 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:41:45 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:41:45 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:41:45 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:41:45 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:41:45 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:41:45 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:41:45 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:41:45 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:41:45 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:41:45 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:41:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:41:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:41:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:41:45 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:41:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:41:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:41:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:41:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:41:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:41:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:41:45 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:41:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:41:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:41:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:41:45 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:41:45 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:41:45 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:41:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:41:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:41:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:41:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:41:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:41:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:41:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:41:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:41:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:41:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:41:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:41:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:41:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:41:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:41:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:41:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:41:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:41:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:41:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:41:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:41:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:41:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:41:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:41:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:41:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:41:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:41:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:41:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:41:45 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:41:45 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:41:45 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:41:45 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:41:45 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:41:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:41:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:46 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:41:46 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:41:46 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:41:46 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:41:46 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:41:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:46 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 05:41:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:47 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:41:47 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:41:47 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:41:47 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:41:47 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:41:47 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:41:47 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:41:47 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:41:47 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=404 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:41:47 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:41:47 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:41:47 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:41:47 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=404 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:41:52 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:41:52 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:41:52 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:41:52 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:41:52 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:41:52 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:41:52 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:41:52 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:41:52 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:41:52 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:41:52 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:41:52 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:41:52 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:41:52 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:41:52 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:41:52 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:41:52 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:41:52 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:41:52 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:41:52 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:41:52 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:41:52 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:41:52 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:41:52 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:41:52 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:41:52 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:41:52 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:41:52 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:41:52 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:41:52 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:41:52 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:41:52 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:41:52 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:41:52 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:41:52 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:41:52 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:41:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:41:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:41:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:41:52 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:41:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:41:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:41:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:41:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:41:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:41:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:41:52 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:41:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:41:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:41:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:41:52 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:41:52 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:41:52 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:41:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:41:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:41:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:41:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:41:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:41:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:41:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:41:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:41:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:41:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:41:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:41:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:41:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:41:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:41:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:41:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:41:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:41:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:41:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:41:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:41:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:41:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:41:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:41:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:41:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:41:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:41:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:41:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:41:52 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:41:52 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:41:52 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:41:52 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:41:52 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:41:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:41:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:53 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:41:53 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:41:53 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:41:53 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:41:53 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:41:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:53 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 05:41:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:54 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:41:54 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:41:54 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:41:54 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:41:54 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:41:54 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:41:54 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:41:54 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:41:54 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:41:54 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=402 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:41:54 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:41:54 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:41:54 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=402 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:41:54 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=402 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:41:54 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=402 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:41:54 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=403 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:41:54 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=403 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:41:54 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=403 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:41:54 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=403 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:41:54 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=403 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:41:54 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=403 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:41:54 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=403 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:41:54 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=403 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:41:59 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:41:59 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:41:59 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:41:59 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:41:59 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:41:59 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:41:59 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:41:59 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:41:59 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:41:59 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:41:59 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:41:59 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:41:59 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:41:59 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:41:59 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:41:59 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:41:59 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:41:59 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:41:59 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:41:59 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:41:59 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:41:59 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:41:59 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:41:59 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:41:59 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:41:59 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:41:59 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:41:59 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:41:59 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:41:59 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:41:59 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:41:59 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:41:59 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:41:59 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:41:59 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:41:59 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:41:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:41:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:41:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:41:59 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:41:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:41:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:41:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:41:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:41:59 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:41:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:41:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:41:59 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:41:59 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:41:59 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:41:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:41:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:41:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:41:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:41:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:41:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:41:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:41:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:41:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:41:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:41:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:41:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:41:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:41:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:41:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:41:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:41:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:41:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:41:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:41:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:41:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:41:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:41:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:41:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:41:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:41:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:41:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:41:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:41:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:41:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:41:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:41:59 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:41:59 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:41:59 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:41:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:59 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:41:59 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:41:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:41:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:41:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:41:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:41:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:41:59 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:41:59 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:41:59 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:41:59 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:41:59 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:41:59 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:41:59 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:41:59 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=135 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:41:59 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=135 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:41:59 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=135 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:41:59 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=135 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:41:59 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=135 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:41:59 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=135 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:41:59 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=135 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:42:04 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:42:04 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:42:04 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:42:04 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:42:04 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:42:04 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:42:04 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:42:04 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:42:04 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:42:04 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:42:04 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:42:04 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:42:04 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:42:04 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:42:04 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:42:04 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:42:04 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:42:04 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:42:04 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:42:04 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:42:04 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:42:04 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:42:04 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:42:04 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:42:04 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:42:04 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:42:04 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:42:04 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:42:04 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:42:04 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:42:04 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:42:04 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:42:04 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:42:04 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:42:04 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:42:04 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:42:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:42:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:42:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:42:04 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:42:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:42:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:42:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:42:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:42:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:42:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:42:04 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:42:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:42:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:42:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:42:04 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:42:04 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:42:04 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:42:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:42:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:42:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:42:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:42:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:42:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:42:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:42:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:42:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:42:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:42:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:42:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:42:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:42:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:42:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:42:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:42:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:42:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:42:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:42:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:42:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:42:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:42:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:42:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:42:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:42:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:42:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:42:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:42:04 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:42:05 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:42:05 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:42:05 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:42:05 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:42:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:05 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:42:05 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:42:05 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:42:05 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:42:05 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:42:05 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:42:05 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:42:05 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:42:05 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:42:05 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:42:05 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:42:10 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:42:10 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:42:10 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:42:10 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:42:10 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:42:10 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:42:10 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:42:10 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:42:10 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:42:10 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:42:10 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:42:10 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:42:10 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:42:10 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:42:10 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:42:10 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:42:10 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:42:10 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:42:10 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:42:10 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:42:10 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:42:10 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:42:10 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:42:10 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:42:10 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:42:10 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:42:10 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:42:10 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:42:10 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:42:10 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:42:10 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:42:10 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:42:10 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:42:10 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:42:10 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:42:10 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:42:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:42:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:42:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:42:10 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:42:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:42:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:42:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:42:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:42:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:42:10 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:42:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:42:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:42:10 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:42:10 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:42:10 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:42:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:42:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:42:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:42:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:42:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:42:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:42:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:42:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:42:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:42:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:42:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:42:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:42:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:42:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:42:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:42:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:42:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:42:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:42:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:42:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:42:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:42:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:42:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:42:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:42:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:42:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:42:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:42:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:42:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:42:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:42:10 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:42:11 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:42:11 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:42:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:11 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:42:11 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:42:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:42:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:42:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:42:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:42:11 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:42:11 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:42:11 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:42:11 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:42:11 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:42:11 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:42:11 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:42:11 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=136 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:42:11 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=136 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:42:11 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=136 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:42:11 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=136 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:42:11 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=136 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:42:11 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=136 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:42:11 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=136 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:42:11 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=136 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:42:16 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:42:16 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:42:16 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:42:16 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:42:16 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:42:16 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:42:16 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:42:16 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:42:16 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:42:16 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:42:16 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:42:16 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:42:16 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:42:16 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:42:16 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:42:16 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:42:16 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:42:16 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:42:16 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:42:16 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:42:16 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:42:16 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:42:16 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:42:16 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:42:16 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:42:16 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:42:16 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:42:16 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:42:16 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:42:16 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:42:16 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:42:16 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:42:16 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:42:16 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:42:16 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:42:16 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:42:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:42:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:42:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:42:16 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:42:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:42:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:42:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:42:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:42:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:42:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:42:16 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:42:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:42:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:42:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:42:16 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:42:16 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:42:16 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:42:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:42:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:42:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:42:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:42:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:42:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:42:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:42:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:42:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:42:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:42:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:42:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:42:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:42:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:42:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:42:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:42:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:42:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:42:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:42:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:42:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:42:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:42:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:42:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:42:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:42:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:42:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:42:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:42:16 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:42:16 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:42:16 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:42:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:16 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:42:16 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:42:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:42:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:42:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:42:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:42:16 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:42:16 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:42:16 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:42:16 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:42:16 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:42:16 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:42:16 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:42:16 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=134 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:42:16 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=134 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:42:16 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=134 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:42:16 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=134 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:42:16 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=134 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:42:16 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=134 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:42:21 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:42:21 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:42:21 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:42:21 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:42:21 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:42:21 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:42:21 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:42:21 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:42:21 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:42:21 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:42:21 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:42:21 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:42:21 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:42:21 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:42:21 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:42:21 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:42:21 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:42:21 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:42:21 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:42:21 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:42:21 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:42:21 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:42:21 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:42:21 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:42:21 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:42:21 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:42:21 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:42:21 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:42:21 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:42:21 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:42:21 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:42:21 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:42:21 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:42:21 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:42:21 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:42:21 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:42:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:42:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:42:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:42:21 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:42:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:42:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:42:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:42:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:42:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:42:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:42:21 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:42:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:42:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:42:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:42:21 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:42:21 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:42:21 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:42:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:42:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:42:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:42:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:42:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:42:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:42:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:42:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:42:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:42:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:42:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:42:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:42:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:42:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:42:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:42:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:42:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:42:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:42:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:42:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:42:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:42:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:42:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:42:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:42:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:42:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:42:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:42:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:42:21 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:42:22 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:42:22 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:42:22 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:42:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:22 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:42:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:42:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:22 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:42:22 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:42:22 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:42:22 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:42:22 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:42:22 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:42:22 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:42:22 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:42:22 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:42:22 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:42:22 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:42:22 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=134 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:42:22 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=134 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:42:22 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=134 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:42:22 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=134 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:42:22 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=134 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:42:22 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=134 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:42:22 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=134 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:42:27 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:42:27 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:42:27 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:42:27 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:42:27 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:42:27 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:42:27 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:42:27 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:42:27 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:42:27 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:42:27 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:42:27 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:42:27 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:42:27 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:42:27 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:42:27 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:42:27 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:42:27 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:42:27 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:42:27 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:42:27 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:42:27 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:42:27 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:42:27 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:42:27 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:42:27 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:42:27 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:42:27 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:42:27 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:42:27 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:42:27 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:42:27 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:42:27 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:42:27 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:42:27 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:42:27 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:42:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:42:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:42:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:42:27 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:42:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:42:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:42:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:42:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:42:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:42:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:42:27 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:42:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:42:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:42:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:42:27 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:42:27 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:42:27 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:42:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:42:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:42:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:42:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:42:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:42:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:42:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:42:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:42:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:42:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:42:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:42:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:42:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:42:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:42:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:42:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:42:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:42:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:42:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:42:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:42:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:42:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:42:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:42:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:42:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:42:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:42:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:42:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:42:27 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:42:28 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:42:28 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:42:28 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:42:28 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:42:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:42:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:28 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:42:28 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:42:28 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:42:28 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:42:28 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:42:28 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:42:28 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:42:28 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:42:28 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:42:28 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:42:28 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:42:33 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:42:33 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:42:33 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:42:33 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:42:33 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:42:33 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:42:33 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:42:33 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:42:33 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:42:33 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:42:33 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:42:33 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:42:33 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:42:33 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:42:33 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:42:33 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:42:33 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:42:33 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:42:33 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:42:33 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:42:33 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:42:33 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:42:33 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:42:33 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:42:33 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:42:33 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:42:33 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:42:33 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:42:33 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:42:33 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:42:33 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:42:33 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:42:33 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:42:33 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:42:33 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:42:33 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:42:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:42:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:42:33 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:42:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:42:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:42:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:42:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:42:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:42:33 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:42:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:42:33 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:42:33 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:42:33 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:42:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:42:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:42:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:42:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:42:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:42:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:42:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:42:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:42:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:42:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:42:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:42:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:42:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:42:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:42:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:42:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:42:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:42:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:42:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:42:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:42:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:42:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:42:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:42:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:42:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:42:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:42:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:42:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:42:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:42:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:42:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:42:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:42:33 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:42:33 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:42:33 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:42:33 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:42:33 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:42:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:42:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:33 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:42:33 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:42:33 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:42:33 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:42:33 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:42:33 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:42:33 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:42:33 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:42:33 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=136 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:42:33 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:42:33 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:42:33 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:42:33 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=136 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:42:33 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=136 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:42:33 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=136 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:42:33 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=136 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:42:38 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:42:38 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:42:38 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:42:38 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:42:38 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:42:38 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:42:38 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:42:38 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:42:38 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:42:38 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:42:38 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:42:38 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:42:38 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:42:38 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:42:38 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:42:38 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:42:38 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:42:38 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:42:38 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:42:38 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:42:38 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:42:38 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:42:38 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:42:38 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:42:38 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:42:38 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:42:38 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:42:38 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:42:38 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:42:38 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:42:38 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:42:38 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:42:38 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:42:38 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:42:38 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:42:38 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:42:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:42:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:42:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:42:38 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:42:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:42:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:42:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:42:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:42:38 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:42:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:42:38 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:42:38 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:42:38 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:42:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:42:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:42:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:42:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:42:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:42:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:42:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:42:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:42:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:42:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:42:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:42:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:42:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:42:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:42:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:42:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:42:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:42:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:42:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:42:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:42:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:42:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:42:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:42:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:42:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:42:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:42:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:42:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:42:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:42:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:42:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:42:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:42:38 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:42:39 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:42:39 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:42:39 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:42:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:39 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:42:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:42:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:42:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:42:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:42:39 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:42:39 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:42:39 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:42:39 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:42:39 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:42:39 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:42:39 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:42:39 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:42:39 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:42:40 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 05:42:40 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 05:42:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:42:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:42:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:42:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:42:41 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 05:42:41 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 05:42:41 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:42:41 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:42:41 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:42:41 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:42:42 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 05:42:42 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 05:42:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:42:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:42:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:42:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:42:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:42:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:42:42 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:42:42 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:42:42 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:42:42 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:42:42 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:42:42 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:42:42 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:42:42 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=859 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:42:42 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=859 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:42:42 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=859 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:42:42 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=859 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:42:42 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=859 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:42:42 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=859 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:42:42 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=860 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:42:42 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=860 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:42:42 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=860 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:42:42 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=860 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:42:42 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=860 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:42:42 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=860 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:42:42 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=860 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:42:42 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=860 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:42:48 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:42:48 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:42:48 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:42:48 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:42:48 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:42:48 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:42:48 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:42:48 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:42:48 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:42:48 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:42:48 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:42:48 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:42:48 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:42:48 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:42:48 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:42:48 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:42:48 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:42:48 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:42:48 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:42:48 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:42:48 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:42:48 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:42:48 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:42:48 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:42:48 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:42:48 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:42:48 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:42:48 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:42:48 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:42:48 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:42:48 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:42:48 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:42:48 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:42:48 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:42:48 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:42:48 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:42:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:42:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:42:48 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:42:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:42:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:42:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:42:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:42:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:42:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:42:48 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:42:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:42:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:42:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:42:48 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:42:48 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:42:48 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:42:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:42:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:42:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:42:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:42:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:42:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:42:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:42:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:42:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:42:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:42:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:42:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:42:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:42:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:42:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:42:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:42:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:42:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:42:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:42:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:42:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:42:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:42:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:42:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:42:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:42:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:42:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:42:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:42:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:42:48 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:42:48 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:42:48 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:42:48 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:42:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:48 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:42:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:42:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:42:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:42:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:42:48 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:42:48 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:42:48 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:42:48 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:42:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD HANDOVER
2025-04-27 05:42:48 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:42:48 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:42:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:42:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:42:49 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:42:49 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:42:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:42:49 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:42:49 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:42:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:42:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:42:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:42:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:42:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:42:49 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:42:49 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:42:49 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:42:49 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:42:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:42:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:42:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:42:49 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:42:49 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:42:49 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:42:49 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:42:49 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:42:49 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:42:49 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:42:49 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:42:49 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:42:49 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:42:49 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=249 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:42:49 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=249 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:42:49 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=249 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:42:49 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=249 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:42:49 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=249 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:42:49 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=249 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:42:49 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=249 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:42:54 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:42:54 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:42:54 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:42:54 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:42:54 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:42:54 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:42:54 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:42:54 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:42:54 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:42:54 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:42:54 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:42:54 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:42:54 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:42:54 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:42:54 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:42:54 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:42:54 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:42:54 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:42:54 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:42:54 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:42:54 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:42:54 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:42:54 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:42:54 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:42:54 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:42:54 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:42:54 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:42:54 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:42:54 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:42:54 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:42:54 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:42:54 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:42:54 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:42:54 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:42:54 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:42:54 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:42:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:42:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:42:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:42:54 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:42:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:42:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:42:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:42:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:42:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:42:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:42:54 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:42:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:42:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:42:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:42:54 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:42:54 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:42:54 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:42:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:42:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:42:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:42:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:42:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:42:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:42:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:42:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:42:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:42:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:42:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:42:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:42:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:42:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:42:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:42:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:42:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:42:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:42:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:42:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:42:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:42:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:42:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:42:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:42:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:42:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:42:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:42:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:42:54 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:42:54 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:42:54 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:42:54 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:42:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:54 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:42:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:42:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:42:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:42:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:42:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:42:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:42:54 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:42:54 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:42:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD HANDOVER
2025-04-27 05:42:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:42:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:42:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:42:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:42:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:42:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:42:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:42:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:42:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:42:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:42:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:42:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:42:54 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:42:54 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:42:55 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:42:55 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:42:55 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:42:55 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:42:55 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:42:55 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 05:42:56 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 05:42:56 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:42:56 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:42:56 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:42:56 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:42:56 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 05:42:57 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-27 05:42:57 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:42:57 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:42:57 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:42:57 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:42:57 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-27 05:42:58 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-27 05:42:58 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:42:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:42:58 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:42:58 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:42:58 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-27 05:42:59 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-27 05:42:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:42:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:42:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:42:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:42:59 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-27 05:42:59 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-27 05:43:00 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-27 05:43:00 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-27 05:43:01 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-27 05:43:01 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-27 05:43:02 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-27 05:43:02 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-27 05:43:03 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-27 05:43:03 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-27 05:43:04 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-27 05:43:04 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-27 05:43:05 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-27 05:43:05 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-27 05:43:06 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-27 05:43:06 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-27 05:43:07 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-27 05:43:07 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-27 05:43:08 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-27 05:43:08 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-27 05:43:08 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-27 05:43:09 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-27 05:43:09 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-27 05:43:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:43:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:43:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:43:10 [WARNING] transceiver.py:250 (MS@172.18.127.22:6700) RX TRXD message (fn=3432 tn=2 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:43:10 [WARNING] transceiver.py:250 (MS@172.18.127.22:6700) RX TRXD message (fn=3432 tn=3 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:43:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:43:10 [WARNING] transceiver.py:250 (MS@172.18.127.22:6700) RX TRXD message (fn=3432 tn=4 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:43:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:43:10 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:43:10 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:43:10 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:43:10 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:43:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:43:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:43:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:43:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:43:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:43:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:43:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:43:10 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:43:10 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:43:10 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:43:10 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:43:10 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:43:10 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:43:10 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:43:10 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3440 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:43:10 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3440 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:43:10 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3440 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:43:10 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3440 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:43:10 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3440 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:43:10 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=3440 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:43:15 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:43:15 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:43:15 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:43:15 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:43:15 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:43:15 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:43:15 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:43:15 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:43:15 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:43:15 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:43:15 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:43:15 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:43:15 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:43:15 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:43:15 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:43:15 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:43:15 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:43:15 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:43:15 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:43:15 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:43:15 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:43:15 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:43:15 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:43:15 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:43:15 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:43:15 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:43:15 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:43:15 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:43:15 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:43:15 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:43:15 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:43:15 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:43:15 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:43:15 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:43:15 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:43:15 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:43:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:43:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:43:15 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:43:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:43:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:43:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:43:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:43:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:43:15 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:43:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:43:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:43:15 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:43:15 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:43:15 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:43:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:43:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:43:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:43:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:43:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:43:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:43:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:43:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:43:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:43:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:43:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:43:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:43:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:43:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:43:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:43:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:43:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:43:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:43:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:43:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:43:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:43:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:43:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:43:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:43:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:43:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:43:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:43:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:43:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:43:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:43:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:43:15 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:43:15 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:43:15 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:43:15 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:43:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:43:15 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:43:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:43:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:43:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:43:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:43:15 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:43:15 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:43:15 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:43:15 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:43:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD HANDOVER
2025-04-27 05:43:15 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:43:15 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:43:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:43:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:43:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:43:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD HANDOVER
2025-04-27 05:43:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:43:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:43:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:43:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:43:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:43:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:43:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:43:16 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:43:16 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:43:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:43:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:43:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:43:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:43:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:43:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:43:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:43:16 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:43:16 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:43:16 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:43:16 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:43:16 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:43:16 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:43:16 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=198 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:43:16 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:43:16 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=198 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:43:16 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=198 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:43:16 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=198 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:43:21 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:43:21 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:43:21 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:43:21 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:43:21 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:43:21 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:43:21 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:43:21 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:43:21 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:43:21 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:43:21 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:43:21 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:43:21 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:43:21 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:43:21 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:43:21 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:43:21 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:43:21 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:43:21 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:43:21 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:43:21 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:43:21 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:43:21 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:43:21 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:43:21 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:43:21 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:43:21 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:43:21 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:43:21 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:43:21 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:43:21 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:43:21 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:43:21 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:43:21 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:43:21 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:43:21 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:43:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:43:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:43:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:43:21 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:43:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:43:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:43:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:43:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:43:21 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:43:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:43:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:43:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:43:21 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:43:21 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:43:21 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:43:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:43:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:43:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:43:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:43:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:43:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:43:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:43:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:43:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:43:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:43:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:43:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:43:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:43:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:43:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:43:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:43:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:43:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:43:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:43:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:43:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:43:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:43:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:43:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:43:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:43:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:43:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:43:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:43:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:43:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:43:21 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-27 05:43:21 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-27 05:43:21 [DEBUG] fake_trx.py:272 (BTS@172.18.127.20:5700) Recv FAKE_TOA cmd
2025-04-27 05:43:21 [DEBUG] fake_trx.py:291 (BTS@172.18.127.20:5700) Recv FAKE_RSSI cmd
2025-04-27 05:43:21 [DEBUG] fake_trx.py:316 (BTS@172.18.127.20:5700) Recv FAKE_CI cmd
2025-04-27 05:43:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:43:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:43:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:43:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:43:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:43:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:43:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:43:21 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:43:21 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:43:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD HANDOVER
2025-04-27 05:43:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:43:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:43:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:43:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:43:22 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-27 05:43:22 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:43:22 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:43:22 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:43:22 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:43:22 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-27 05:43:23 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-27 05:43:23 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:43:23 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:43:23 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:43:23 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:43:23 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-27 05:43:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:43:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:43:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:43:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD ECHO
2025-04-27 05:43:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.127.22:6700) Ignore CMD SETSLOT
2025-04-27 05:43:23 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.127.22:6700) Recv RXTUNE cmd
2025-04-27 05:43:23 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.127.22:6700) Recv TXTUNE cmd
2025-04-27 05:43:23 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.127.22:6700) Recv POWERON CMD
2025-04-27 05:43:23 [INFO] ctrl_if_trx.py:109 (MS@172.18.127.22:6700) Starting transceiver...
2025-04-27 05:43:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD NOHANDOVER
2025-04-27 05:43:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.127.22:6700) Recv POWEROFF cmd
2025-04-27 05:43:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.127.22:6700) Stopping transceiver...
2025-04-27 05:43:23 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.127.20:5700) Recv SETPOWER cmd
2025-04-27 05:43:23 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.127.20:5700/1) Recv SETPOWER cmd
2025-04-27 05:43:23 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.127.20:5700/2) Recv SETPOWER cmd
2025-04-27 05:43:23 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.127.20:5700/3) Recv SETPOWER cmd
2025-04-27 05:43:23 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:43:23 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:43:23 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:43:23 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:43:23 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:43:23 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:43:23 [INFO] transceiver.py:239 Stopping clock generator
2025-04-27 05:43:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=564 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:43:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=564 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:43:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=564 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:43:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=565 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:43:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=565 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:43:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=565 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:43:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=565 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:43:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=565 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:43:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=565 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:43:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=565 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:43:23 [WARNING] transceiver.py:250 (BTS@172.18.127.20:5700) RX TRXD message (ver=1 fn=565 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-27 05:43:28 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:43:28 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:43:28 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:43:28 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:43:28 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:43:28 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:43:28 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:43:28 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:43:28 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.127.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:43:28 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.127.20:5700) Recv SETFORMAT cmd
2025-04-27 05:43:28 [INFO] ctrl_if_trx.py:201 (BTS@172.18.127.20:5700) TRXD header version 1 -> 1
2025-04-27 05:43:28 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.127.20:5700/1) Recv RXTUNE cmd
2025-04-27 05:43:28 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.127.20:5700/1) Recv TXTUNE cmd
2025-04-27 05:43:28 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:43:28 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.127.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:43:28 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:43:28 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.127.20:5700/1) Recv NOMTXPOWER cmd
2025-04-27 05:43:28 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.127.20:5700/1) Recv SETFORMAT cmd
2025-04-27 05:43:28 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.127.20:5700/1) TRXD header version 1 -> 1
2025-04-27 05:43:28 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.127.20:5700/2) Recv RXTUNE cmd
2025-04-27 05:43:28 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.127.20:5700/2) Recv TXTUNE cmd
2025-04-27 05:43:28 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:43:28 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.127.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:43:28 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:43:28 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.127.20:5700/2) Recv NOMTXPOWER cmd
2025-04-27 05:43:28 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.127.20:5700/2) Recv SETFORMAT cmd
2025-04-27 05:43:28 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.127.20:5700/2) TRXD header version 1 -> 1
2025-04-27 05:43:28 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.127.20:5700/3) Recv RXTUNE cmd
2025-04-27 05:43:28 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.127.20:5700/3) Recv TXTUNE cmd
2025-04-27 05:43:28 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:43:28 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.127.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-27 05:43:28 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:43:28 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.127.20:5700/3) Recv NOMTXPOWER cmd
2025-04-27 05:43:28 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.127.20:5700/3) Recv SETFORMAT cmd
2025-04-27 05:43:28 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.127.20:5700/3) TRXD header version 1 -> 1
2025-04-27 05:43:28 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.127.20:5700) Recv RXTUNE cmd
2025-04-27 05:43:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETTSC
2025-04-27 05:43:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETTSC
2025-04-27 05:43:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETTSC
2025-04-27 05:43:28 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.127.20:5700) Recv TXTUNE cmd
2025-04-27 05:43:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETRXGAIN
2025-04-27 05:43:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETRXGAIN
2025-04-27 05:43:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETRXGAIN
2025-04-27 05:43:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETTSC
2025-04-27 05:43:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:43:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:43:28 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.127.20:5700) Recv NOMTXPOWER cmd
2025-04-27 05:43:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:43:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:43:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:43:28 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.127.20:5700) Recv POWERON CMD
2025-04-27 05:43:28 [INFO] ctrl_if_trx.py:109 (BTS@172.18.127.20:5700) Starting transceiver...
2025-04-27 05:43:28 [INFO] transceiver.py:236 Starting clock generator
2025-04-27 05:43:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:43:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:43:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:43:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETRXGAIN
2025-04-27 05:43:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:43:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:43:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:43:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:43:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:43:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:43:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:43:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:43:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:43:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:43:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:43:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:43:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:43:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:43:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.127.20:5700/1) Ignore CMD SETSLOT
2025-04-27 05:43:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:43:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:43:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:43:28 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.127.20:5700/1) Recv RFMUTE cmd
2025-04-27 05:43:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.127.20:5700/2) Ignore CMD SETSLOT
2025-04-27 05:43:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:43:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:43:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:43:28 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.127.20:5700/2) Recv RFMUTE cmd
2025-04-27 05:43:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.127.20:5700) Ignore CMD SETSLOT
2025-04-27 05:43:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.127.20:5700/3) Ignore CMD SETSLOT
2025-04-27 05:43:28 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.127.20:5700) Recv RFMUTE cmd
2025-04-27 05:43:28 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.127.20:5700/3) Recv RFMUTE cmd
2025-04-27 05:43:28 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.127.20:5700) Recv POWEROFF cmd
2025-04-27 05:43:28 [INFO] ctrl_if_trx.py:117 (BTS@172.18.127.20:5700) Stopping transceiver...
2025-04-27 05:43:28 [INFO] transceiver.py:239 Stopping clock generator