#701 (Feb 5, 2026, 2:47:31 PM)

Started by timer

This run spent:

• 1 min 30 sec waiting;
• 39 min build duration;
• 40 min total from scheduled to completion.

• origin/master

• MSC_Tests.TC_ho_inter_bsc
• MSC_Tests_ASCI.TC_assign_fail
• MSC_Tests_ASCI.TC_complete_vbs
• MSC_Tests.TC_lu_imsi_timeout_tmsi_realloc
• MSC_Tests_Iu.TC_iu_lu_imsi_timeout_tmsi_realloc
• MSC_Tests_Iu.TC_iu_cmserv_imsi_unknown
• MSC_Tests_Iu.TC_iu_lu_and_mt_sms_paging_repeated
• MSC_Tests_Iu.TC_iu_lu_with_invalid_mcc_mnc

1. bts: f_TC_tx_power_ramp_adm_state_change(): drop unused last_rx_lvl (details)
2. bts: f_TC_acch_overpower(): use f_wait_ramp_up() (details)
3. bts: fix verdict string in f_verify_ramp_up() (details)