#653 (Dec 19, 2025, 2:46:00 PM)

Started by timer

This run spent:

• 4 ms waiting;
• 38 min build duration;
• 38 min total from scheduled to completion.

• origin/master

• MSC_Tests_ASCI.TC_assign_fail
• MSC_Tests_ASCI.TC_complete_vgcs
• MSC_Tests_ASCI.TC_complete_vbs
• MSC_Tests.TC_lu_imsi_timeout_tmsi_realloc
• MSC_Tests_Iu.TC_iu_lu_imsi_timeout_tmsi_realloc
• MSC_Tests_Iu.TC_iu_cmserv_imsi_unknown
• MSC_Tests_Iu.TC_iu_lu_and_mt_sms_paging_repeated
• MSC_Tests_Iu.TC_iu_lu_with_invalid_mcc_mnc

1. RAN_Emulation: Support Tx RESET retries in RANAP (details)
2. BSSAP_LE_Emulation: Support Tx RESET retries (details)
3. BSSAP(_LE)/RANAP: Proper counting of RESET retries (details)